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61305a96 BH |
1 | #ifndef __POWERNV_PCI_H |
2 | #define __POWERNV_PCI_H | |
3 | ||
4 | struct pci_dn; | |
5 | ||
6 | enum pnv_phb_type { | |
aa0c033f GS |
7 | PNV_PHB_P5IOC2 = 0, |
8 | PNV_PHB_IODA1 = 1, | |
9 | PNV_PHB_IODA2 = 2, | |
61305a96 BH |
10 | }; |
11 | ||
cee72d5b BH |
12 | /* Precise PHB model for error management */ |
13 | enum pnv_phb_model { | |
14 | PNV_PHB_MODEL_UNKNOWN, | |
15 | PNV_PHB_MODEL_P5IOC2, | |
16 | PNV_PHB_MODEL_P7IOC, | |
aa0c033f | 17 | PNV_PHB_MODEL_PHB3, |
cee72d5b BH |
18 | }; |
19 | ||
5c9d6d75 | 20 | #define PNV_PCI_DIAG_BUF_SIZE 8192 |
7ebdf956 GS |
21 | #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ |
22 | #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ | |
23 | #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ | |
262af557 GC |
24 | #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ |
25 | #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ | |
cee72d5b | 26 | |
184cd4a3 | 27 | /* Data associated with a PE, including IOMMU tracking etc.. */ |
4cce9550 | 28 | struct pnv_phb; |
184cd4a3 | 29 | struct pnv_ioda_pe { |
7ebdf956 | 30 | unsigned long flags; |
4cce9550 | 31 | struct pnv_phb *phb; |
7ebdf956 | 32 | |
184cd4a3 BH |
33 | /* A PE can be associated with a single device or an |
34 | * entire bus (& children). In the former case, pdev | |
35 | * is populated, in the later case, pbus is. | |
36 | */ | |
37 | struct pci_dev *pdev; | |
38 | struct pci_bus *pbus; | |
39 | ||
40 | /* Effective RID (device RID for a device PE and base bus | |
41 | * RID with devfn 0 for a bus PE) | |
42 | */ | |
43 | unsigned int rid; | |
44 | ||
45 | /* PE number */ | |
46 | unsigned int pe_number; | |
47 | ||
48 | /* "Weight" assigned to the PE for the sake of DMA resource | |
49 | * allocations | |
50 | */ | |
51 | unsigned int dma_weight; | |
52 | ||
184cd4a3 BH |
53 | /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ |
54 | int tce32_seg; | |
55 | int tce32_segcount; | |
56 | struct iommu_table tce32_table; | |
8e0a1611 | 57 | phys_addr_t tce_inval_reg_phys; |
184cd4a3 | 58 | |
cd15b048 BH |
59 | /* 64-bit TCE bypass region */ |
60 | bool tce_bypass_enabled; | |
61 | uint64_t tce_bypass_base; | |
184cd4a3 BH |
62 | |
63 | /* MSIs. MVE index is identical for for 32 and 64 bit MSI | |
64 | * and -1 if not supported. (It's actually identical to the | |
65 | * PE number) | |
66 | */ | |
67 | int mve_number; | |
68 | ||
262af557 GC |
69 | /* PEs in compound case */ |
70 | struct pnv_ioda_pe *master; | |
71 | struct list_head slaves; | |
72 | ||
184cd4a3 | 73 | /* Link in list of PE#s */ |
7ebdf956 GS |
74 | struct list_head dma_link; |
75 | struct list_head list; | |
184cd4a3 BH |
76 | }; |
77 | ||
8747f363 GS |
78 | /* IOC dependent EEH operations */ |
79 | #ifdef CONFIG_EEH | |
80 | struct pnv_eeh_ops { | |
8747f363 GS |
81 | int (*set_option)(struct eeh_pe *pe, int option); |
82 | int (*get_state)(struct eeh_pe *pe); | |
83 | int (*reset)(struct eeh_pe *pe, int option); | |
8747f363 GS |
84 | int (*configure_bridge)(struct eeh_pe *pe); |
85 | int (*next_error)(struct eeh_pe **pe); | |
86 | }; | |
87 | #endif /* CONFIG_EEH */ | |
88 | ||
f5bc6b70 GS |
89 | #define PNV_PHB_FLAG_EEH (1 << 0) |
90 | ||
61305a96 BH |
91 | struct pnv_phb { |
92 | struct pci_controller *hose; | |
93 | enum pnv_phb_type type; | |
cee72d5b | 94 | enum pnv_phb_model model; |
8747f363 | 95 | u64 hub_id; |
61305a96 | 96 | u64 opal_id; |
f5bc6b70 | 97 | int flags; |
61305a96 | 98 | void __iomem *regs; |
db1266c8 | 99 | int initialized; |
61305a96 BH |
100 | spinlock_t lock; |
101 | ||
8747f363 GS |
102 | #ifdef CONFIG_EEH |
103 | struct pnv_eeh_ops *eeh_ops; | |
8747f363 GS |
104 | #endif |
105 | ||
37c367f2 | 106 | #ifdef CONFIG_DEBUG_FS |
7f52a526 | 107 | int has_dbgfs; |
37c367f2 GS |
108 | struct dentry *dbgfs; |
109 | #endif | |
110 | ||
c1a2562a | 111 | #ifdef CONFIG_PCI_MSI |
c1a2562a | 112 | unsigned int msi_base; |
c1a2562a | 113 | unsigned int msi32_support; |
fb1b55d6 | 114 | struct msi_bitmap msi_bmp; |
c1a2562a BH |
115 | #endif |
116 | int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, | |
137436c9 GS |
117 | unsigned int hwirq, unsigned int virq, |
118 | unsigned int is_64, struct msi_msg *msg); | |
61305a96 | 119 | void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); |
cd15b048 BH |
120 | int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev, |
121 | u64 dma_mask); | |
fe7e85c6 GS |
122 | u64 (*dma_get_required_mask)(struct pnv_phb *phb, |
123 | struct pci_dev *pdev); | |
61305a96 BH |
124 | void (*fixup_phb)(struct pci_controller *hose); |
125 | u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); | |
73ed148a | 126 | void (*shutdown)(struct pnv_phb *phb); |
262af557 | 127 | int (*init_m64)(struct pnv_phb *phb); |
5ef73567 | 128 | void (*reserve_m64_pe)(struct pnv_phb *phb); |
262af557 | 129 | int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all); |
49dec922 GS |
130 | int (*get_pe_state)(struct pnv_phb *phb, int pe_no); |
131 | void (*freeze_pe)(struct pnv_phb *phb, int pe_no); | |
132 | int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); | |
61305a96 BH |
133 | |
134 | union { | |
135 | struct { | |
136 | struct iommu_table iommu_table; | |
137 | } p5ioc2; | |
184cd4a3 BH |
138 | |
139 | struct { | |
140 | /* Global bridge info */ | |
141 | unsigned int total_pe; | |
36954dc7 | 142 | unsigned int reserved_pe; |
262af557 GC |
143 | |
144 | /* 32-bit MMIO window */ | |
184cd4a3 BH |
145 | unsigned int m32_size; |
146 | unsigned int m32_segsize; | |
147 | unsigned int m32_pci_base; | |
262af557 GC |
148 | |
149 | /* 64-bit MMIO window */ | |
150 | unsigned int m64_bar_idx; | |
151 | unsigned long m64_size; | |
152 | unsigned long m64_segsize; | |
153 | unsigned long m64_base; | |
154 | unsigned long m64_bar_alloc; | |
155 | ||
156 | /* IO ports */ | |
184cd4a3 BH |
157 | unsigned int io_size; |
158 | unsigned int io_segsize; | |
159 | unsigned int io_pci_base; | |
160 | ||
161 | /* PE allocation bitmap */ | |
162 | unsigned long *pe_alloc; | |
163 | ||
164 | /* M32 & IO segment maps */ | |
165 | unsigned int *m32_segmap; | |
166 | unsigned int *io_segmap; | |
167 | struct pnv_ioda_pe *pe_array; | |
168 | ||
137436c9 GS |
169 | /* IRQ chip */ |
170 | int irq_chip_init; | |
171 | struct irq_chip irq_chip; | |
172 | ||
7ebdf956 GS |
173 | /* Sorted list of used PE's based |
174 | * on the sequence of creation | |
175 | */ | |
176 | struct list_head pe_list; | |
177 | ||
184cd4a3 BH |
178 | /* Reverse map of PEs, will have to extend if |
179 | * we are to support more than 256 PEs, indexed | |
180 | * bus { bus, devfn } | |
181 | */ | |
182 | unsigned char pe_rmap[0x10000]; | |
183 | ||
184 | /* 32-bit TCE tables allocation */ | |
185 | unsigned long tce32_count; | |
186 | ||
187 | /* Total "weight" for the sake of DMA resources | |
188 | * allocation | |
189 | */ | |
190 | unsigned int dma_weight; | |
191 | unsigned int dma_pe_count; | |
192 | ||
193 | /* Sorted list of used PE's, sorted at | |
194 | * boot for resource allocation purposes | |
195 | */ | |
7ebdf956 | 196 | struct list_head pe_dma_list; |
184cd4a3 | 197 | } ioda; |
61305a96 | 198 | }; |
cee72d5b | 199 | |
ca1de5de | 200 | /* PHB and hub status structure */ |
cee72d5b BH |
201 | union { |
202 | unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; | |
203 | struct OpalIoP7IOCPhbErrorData p7ioc; | |
93aef2a7 | 204 | struct OpalIoPhb3ErrorData phb3; |
ca1de5de | 205 | struct OpalIoP7IOCErrorData hub_diag; |
cee72d5b | 206 | } diag; |
ca1de5de | 207 | |
61305a96 BH |
208 | }; |
209 | ||
210 | extern struct pci_ops pnv_pci_ops; | |
8747f363 GS |
211 | #ifdef CONFIG_EEH |
212 | extern struct pnv_eeh_ops ioda_eeh_ops; | |
213 | #endif | |
61305a96 | 214 | |
93aef2a7 GS |
215 | void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, |
216 | unsigned char *log_buff); | |
9bf41be6 GS |
217 | int pnv_pci_cfg_read(struct device_node *dn, |
218 | int where, int size, u32 *val); | |
219 | int pnv_pci_cfg_write(struct device_node *dn, | |
220 | int where, int size, u32 val); | |
61305a96 BH |
221 | extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
222 | void *tce_mem, u64 tce_size, | |
8fa5d454 | 223 | u64 dma_offset, unsigned page_shift); |
61305a96 | 224 | extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); |
184cd4a3 | 225 | extern void pnv_pci_init_ioda_hub(struct device_node *np); |
aa0c033f | 226 | extern void pnv_pci_init_ioda2_phb(struct device_node *np); |
4cce9550 | 227 | extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, |
3ad26e5c | 228 | __be64 *startp, __be64 *endp, bool rm); |
d92a208d | 229 | extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); |
361f2a2a | 230 | extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option); |
73ed148a | 231 | |
61305a96 | 232 | #endif /* __POWERNV_PCI_H */ |