[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / platforms / powernv / pci.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

#include <linux/iommu.h>
#include <asm/iommu.h>
#include <asm/msi_bitmap.h>

struct pci_dn;

/* Maximum possible number of ATSD MMIO registers per NPU */
#define NV_NMMU_ATSD_REGS 8

enum pnv_phb_type {
	PNV_PHB_IODA1	= 0,
	PNV_PHB_IODA2	= 1,
	PNV_PHB_NPU	= 2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
	PNV_PHB_MODEL_NPU,
	PNV_PHB_MODEL_NPU2,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/

/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
#define PNV_IODA_STOPPED_STATE	0x8000000000000000

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;
	int			device_count;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
#ifdef CONFIG_PCI_IOV
	struct pci_dev          *parent_dev;
#endif
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	struct iommu_table_group table_group;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* PEs in compound case */
	struct pnv_ioda_pe	*master;
	struct list_head	slaves;

	/* PCI peer-to-peer*/
	int			p2p_initiator_count;

	/* Link in list of PE#s */
	struct list_head	list;
};

#define PNV_PHB_FLAG_EEH	(1 << 0)
#define PNV_PHB_FLAG_CXL	(1 << 1) /* Real PHB supporting the cxl kernel API */

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	int			flags;
	void __iomem		*regs;
	u64			regs_phys;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_DEBUG_FS
	int			has_dbgfs;
	struct dentry		*dbgfs;
#endif

#ifdef CONFIG_PCI_MSI
	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	void (*fixup_phb)(struct pci_controller *hose);
	int (*init_m64)(struct pnv_phb *phb);
	void (*reserve_m64_pe)(struct pci_bus *bus,
			       unsigned long *pe_bitmap, bool all);
	struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

	struct {
		/* Global bridge info */
		unsigned int		total_pe_num;
		unsigned int		reserved_pe_idx;
		unsigned int		root_pe_idx;
		bool			root_pe_populated;

		/* 32-bit MMIO window */
		unsigned int		m32_size;
		unsigned int		m32_segsize;
		unsigned int		m32_pci_base;

		/* 64-bit MMIO window */
		unsigned int		m64_bar_idx;
		unsigned long		m64_size;
		unsigned long		m64_segsize;
		unsigned long		m64_base;
		unsigned long		m64_bar_alloc;

		/* IO ports */
		unsigned int		io_size;
		unsigned int		io_segsize;
		unsigned int		io_pci_base;

		/* PE allocation */
		struct mutex		pe_alloc_mutex;
		unsigned long		*pe_alloc;
		struct pnv_ioda_pe	*pe_array;

		/* M32 & IO segment maps */
		unsigned int		*m64_segmap;
		unsigned int		*m32_segmap;
		unsigned int		*io_segmap;

		/* DMA32 segment maps - IODA1 only */
		unsigned int		dma32_count;
		unsigned int		*dma32_segmap;

		/* IRQ chip */
		int			irq_chip_init;
		struct irq_chip		irq_chip;

		/* Sorted list of used PE's based
		 * on the sequence of creation
		 */
		struct list_head	pe_list;
		struct mutex            pe_list_mutex;

		/* Reverse map of PEs, indexed by {bus, devfn} */
		unsigned int		pe_rmap[0x10000];
	} ioda;

	/* PHB and hub diagnostics */
	unsigned int		diag_data_size;
	u8			*diag_data;

	/* Nvlink2 data */
	struct npu {
		int index;
		__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
		unsigned int mmio_atsd_count;

		/* Bitmask for MMIO register usage */
		unsigned long mmio_atsd_usage;
	} npu;

#ifdef CONFIG_CXL_BASE
	struct cxl_afu *cxl_afu;
#endif
	int p2p_target_count;
};

extern struct pci_ops pnv_pci_ops;
extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
		unsigned long uaddr, enum dma_data_direction direction,
		unsigned long attrs);
extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction);
extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct pci_dn *pdn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct pci_dn *pdn,
		      int where, int size, u32 val);
extern struct iommu_table *pnv_pci_table_alloc(int nid);

extern long pnv_pci_link_table_and_group(int node, int num,
		struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset, unsigned page_shift);
extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_init_npu_phb(struct device_node *np);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);

extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);

extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
			    const char *fmt, ...);
#define pe_err(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
#define pe_warn(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
#define pe_info(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)

/* Nvlink functions */
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
		struct iommu_table *tbl);
extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
extern int pnv_npu2_init(struct pnv_phb *phb);

/* cxl functions */
extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
extern void pnv_cxl_disable_device(struct pci_dev *dev);
extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);


/* phb ops (cxl switches these when enabling the kernel api on the phb) */
extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
61305a96 BH	2	#ifndef __POWERNV_PCI_H
	3	#define __POWERNV_PCI_H
	4
f456834a IM	5	#include <linux/iommu.h>
	6	#include <asm/iommu.h>
	7	#include <asm/msi_bitmap.h>
	8
61305a96 BH	9	struct pci_dn;
61305a96 BH	10
1ab66d1f AP	11	/* Maximum possible number of ATSD MMIO registers per NPU */
	12	#define NV_NMMU_ATSD_REGS 8
	13
61305a96	14	enum pnv_phb_type {
2de50e96 RC	15	PNV_PHB_IODA1 = 0,
	16	PNV_PHB_IODA2 = 1,
	17	PNV_PHB_NPU = 2,
61305a96 BH	18	};
61305a96 BH	19
cee72d5b BH	20	/* Precise PHB model for error management */
	21	enum pnv_phb_model {
	22	PNV_PHB_MODEL_UNKNOWN,
cee72d5b	23	PNV_PHB_MODEL_P7IOC,
aa0c033f	24	PNV_PHB_MODEL_PHB3,
5d2aa710	25	PNV_PHB_MODEL_NPU,
616badd2	26	PNV_PHB_MODEL_NPU2,
cee72d5b BH	27	};
cee72d5b BH	28
5c9d6d75	29	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	30	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	31	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	32	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
262af557 GC	33	#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
262af557 GC	34	#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
781a868f	35	#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
cee72d5b	36
31bbd45a RC	37	/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
	38	#define PNV_IODA_STOPPED_STATE 0x8000000000000000
	39
184cd4a3	40	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	41	struct pnv_phb;
184cd4a3	42	struct pnv_ioda_pe {
7ebdf956	43	unsigned long flags;
4cce9550	44	struct pnv_phb *phb;
c5f7700b	45	int device_count;
7ebdf956	46
184cd4a3 BH	47	/* A PE can be associated with a single device or an
	48	* entire bus (& children). In the former case, pdev
	49	* is populated, in the later case, pbus is.
	50	*/
781a868f WY	51	#ifdef CONFIG_PCI_IOV
	52	struct pci_dev *parent_dev;
	53	#endif
184cd4a3 BH	54	struct pci_dev *pdev;
	55	struct pci_bus *pbus;
	56
	57	/* Effective RID (device RID for a device PE and base bus
	58	* RID with devfn 0 for a bus PE)
	59	*/
	60	unsigned int rid;
	61
	62	/* PE number */
	63	unsigned int pe_number;
	64
184cd4a3	65	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
b348aa65	66	struct iommu_table_group table_group;
184cd4a3	67
cd15b048 BH	68	/* 64-bit TCE bypass region */
	69	bool tce_bypass_enabled;
	70	uint64_t tce_bypass_base;
184cd4a3 BH	71
	72	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	73	* and -1 if not supported. (It's actually identical to the
	74	* PE number)
	75	*/
	76	int mve_number;
	77
262af557 GC	78	/* PEs in compound case */
	79	struct pnv_ioda_pe *master;
	80	struct list_head slaves;
	81
25529100 FB	82	/* PCI peer-to-peer*/
	83	int p2p_initiator_count;
	84
184cd4a3	85	/* Link in list of PE#s */
7ebdf956	86	struct list_head list;
184cd4a3 BH	87	};
184cd4a3 BH	88
f5bc6b70	89	#define PNV_PHB_FLAG_EEH (1 << 0)
4361b034	90	#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
f5bc6b70	91
61305a96 BH	92	struct pnv_phb {
	93	struct pci_controller *hose;
	94	enum pnv_phb_type type;
cee72d5b	95	enum pnv_phb_model model;
8747f363	96	u64 hub_id;
61305a96	97	u64 opal_id;
f5bc6b70	98	int flags;
61305a96	99	void __iomem *regs;
fd141d1a	100	u64 regs_phys;
db1266c8	101	int initialized;
61305a96 BH	102	spinlock_t lock;
61305a96 BH	103
37c367f2	104	#ifdef CONFIG_DEBUG_FS
7f52a526	105	int has_dbgfs;
37c367f2 GS	106	struct dentry *dbgfs;
	107	#endif
	108
c1a2562a	109	#ifdef CONFIG_PCI_MSI
c1a2562a	110	unsigned int msi_base;
c1a2562a	111	unsigned int msi32_support;
fb1b55d6	112	struct msi_bitmap msi_bmp;
c1a2562a BH	113	#endif
c1a2562a BH	114	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	115	unsigned int hwirq, unsigned int virq,
137436c9 GS	116	unsigned int is_64, struct msi_msg *msg);
61305a96 BH	117	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
61305a96 BH	118	void (fixup_phb)(struct pci_controller hose);
262af557	119	int (init_m64)(struct pnv_phb phb);
96a2f92b GS	120	void (reserve_m64_pe)(struct pci_bus bus,
96a2f92b GS	121	unsigned long *pe_bitmap, bool all);
1e916772	122	struct pnv_ioda_pe (pick_m64_pe)(struct pci_bus *bus, bool all);
49dec922 GS	123	int (get_pe_state)(struct pnv_phb phb, int pe_no);
	124	void (freeze_pe)(struct pnv_phb phb, int pe_no);
	125	int (unfreeze_pe)(struct pnv_phb phb, int pe_no, int opt);
61305a96	126
2de50e96 RC	127	struct {
2de50e96 RC	128	/* Global bridge info */
92b8f137 GS	129	unsigned int total_pe_num;
92b8f137 GS	130	unsigned int reserved_pe_idx;
63803c39 GS	131	unsigned int root_pe_idx;
63803c39 GS	132	bool root_pe_populated;
2de50e96 RC	133
	134	/* 32-bit MMIO window */
	135	unsigned int m32_size;
	136	unsigned int m32_segsize;
	137	unsigned int m32_pci_base;
	138
	139	/* 64-bit MMIO window */
	140	unsigned int m64_bar_idx;
	141	unsigned long m64_size;
	142	unsigned long m64_segsize;
	143	unsigned long m64_base;
	144	unsigned long m64_bar_alloc;
	145
	146	/* IO ports */
	147	unsigned int io_size;
	148	unsigned int io_segsize;
	149	unsigned int io_pci_base;
	150
13ce7598	151	/* PE allocation */
2de50e96	152	struct mutex pe_alloc_mutex;
13ce7598 GS	153	unsigned long *pe_alloc;
13ce7598 GS	154	struct pnv_ioda_pe *pe_array;
2de50e96 RC	155
2de50e96 RC	156	/* M32 & IO segment maps */
93289d8c	157	unsigned int *m64_segmap;
2de50e96 RC	158	unsigned int *m32_segmap;
2de50e96 RC	159	unsigned int *io_segmap;
2de50e96	160
2b923ed1 GS	161	/* DMA32 segment maps - IODA1 only */
	162	unsigned int dma32_count;
	163	unsigned int *dma32_segmap;
	164
2de50e96 RC	165	/* IRQ chip */
	166	int irq_chip_init;
	167	struct irq_chip irq_chip;
	168
	169	/* Sorted list of used PE's based
	170	* on the sequence of creation
	171	*/
	172	struct list_head pe_list;
	173	struct mutex pe_list_mutex;
	174
c127562a GS	175	/* Reverse map of PEs, indexed by {bus, devfn} */
c127562a GS	176	unsigned int pe_rmap[0x10000];
2de50e96	177	} ioda;
cee72d5b	178
5cb1f8fd RC	179	/* PHB and hub diagnostics */
	180	unsigned int diag_data_size;
	181	u8 *diag_data;
ca1de5de	182
1ab66d1f AP	183	/* Nvlink2 data */
	184	struct npu {
	185	int index;
	186	__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
	187	unsigned int mmio_atsd_count;
	188
	189	/* Bitmask for MMIO register usage */
	190	unsigned long mmio_atsd_usage;
	191	} npu;
	192
4361b034 IM	193	#ifdef CONFIG_CXL_BASE
	194	struct cxl_afu *cxl_afu;
	195	#endif
25529100	196	int p2p_target_count;
61305a96 BH	197	};
	198
	199	extern struct pci_ops pnv_pci_ops;
da004c36 AK	200	extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
da004c36 AK	201	unsigned long uaddr, enum dma_data_direction direction,
00085f1e	202	unsigned long attrs);
da004c36	203	extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
05c6cfb9 AK	204	extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
05c6cfb9 AK	205	unsigned long hpa, enum dma_data_direction direction);
da004c36	206	extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
61305a96	207
93aef2a7 GS	208	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	209	unsigned char *log_buff);
3532a741	210	int pnv_pci_cfg_read(struct pci_dn *pdn,
9bf41be6	211	int where, int size, u32 *val);
3532a741	212	int pnv_pci_cfg_write(struct pci_dn *pdn,
9bf41be6	213	int where, int size, u32 val);
0eaf4def AK	214	extern struct iommu_table *pnv_pci_table_alloc(int nid);
	215
	216	extern long pnv_pci_link_table_and_group(int node, int num,
	217	struct iommu_table *tbl,
	218	struct iommu_table_group *table_group);
	219	extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
	220	struct iommu_table_group *table_group);
61305a96 BH	221	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
61305a96 BH	222	void *tce_mem, u64 tce_size,
8fa5d454	223	u64 dma_offset, unsigned page_shift);
184cd4a3	224	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	225	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
5d2aa710	226	extern void pnv_pci_init_npu_phb(struct device_node *np);
d92a208d	227	extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
cadf364d	228	extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
73ed148a	229
92ae0353	230	extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
1bc74f1c	231	extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
92ae0353 DA	232	extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
92ae0353 DA	233	extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
f456834a IM	234	extern struct pnv_ioda_pe pnv_ioda_get_pe(struct pci_dev dev);
f456834a IM	235	extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
4361b034	236	extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
25529100	237	extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
92ae0353	238
7d623e42 AK	239	extern void pe_level_printk(const struct pnv_ioda_pe pe, const char level,
	240	const char *fmt, ...);
	241	#define pe_err(pe, fmt, ...) \
	242	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
	243	#define pe_warn(pe, fmt, ...) \
	244	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
	245	#define pe_info(pe, fmt, ...) \
	246	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
	247
5d2aa710	248	/* Nvlink functions */
f9f83456	249	extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
6b3d12a9	250	extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
b5cb9ab1 AK	251	extern struct pnv_ioda_pe pnv_pci_npu_setup_iommu(struct pnv_ioda_pe npe);
	252	extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
	253	struct iommu_table *tbl);
	254	extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
	255	extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
	256	extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
1ab66d1f	257	extern int pnv_npu2_init(struct pnv_phb *phb);
4361b034 IM	258
	259	/* cxl functions */
	260	extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
	261	extern void pnv_cxl_disable_device(struct pci_dev *dev);
a2f67d5e IM	262	extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
a2f67d5e IM	263	extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
4361b034 IM	264
	265
	266	/* phb ops (cxl switches these when enabling the kernel api on the phb) */
	267	extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
	268
61305a96	269	#endif /* __POWERNV_PCI_H */