[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / platforms / powernv / setup.c

/*
 * PowerNV setup code.
 *
 * Copyright 2011 IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <linux/cpu.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/interrupt.h>
#include <linux/bug.h>
#include <linux/pci.h>
#include <linux/cpufreq.h>

#include <asm/machdep.h>
#include <asm/firmware.h>
#include <asm/xics.h>
#include <asm/xive.h>
#include <asm/opal.h>
#include <asm/kexec.h>
#include <asm/smp.h>
#include <asm/tm.h>
#include <asm/setup.h>
#include <asm/security_features.h>

#include "powernv.h"


static bool fw_feature_is(const char *state, const char *name,
			  struct device_node *fw_features)
{
	struct device_node *np;
	bool rc = false;

	np = of_get_child_by_name(fw_features, name);
	if (np) {
		rc = of_property_read_bool(np, state);
		of_node_put(np);
	}

	return rc;
}

static void init_fw_feat_flags(struct device_node *np)
{
	if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
		security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);

	if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
		security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);

	if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
		security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);

	if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
		security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);

	if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
		security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);

	if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
		security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);

	/*
	 * The features below are enabled by default, so we instead look to see
	 * if firmware has *disabled* them, and clear them if so.
	 */
	if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
		security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);

	if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
		security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);

	if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
		security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);

	if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
		security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
}

static void pnv_setup_rfi_flush(void)
{
	struct device_node *np, *fw_features;
	enum l1d_flush_type type;
	bool enable;

	/* Default to fallback in case fw-features are not available */
	type = L1D_FLUSH_FALLBACK;

	np = of_find_node_by_name(NULL, "ibm,opal");
	fw_features = of_get_child_by_name(np, "fw-features");
	of_node_put(np);

	if (fw_features) {
		init_fw_feat_flags(fw_features);
		of_node_put(fw_features);

		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
			type = L1D_FLUSH_MTTRIG;

		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
			type = L1D_FLUSH_ORI;
	}

	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
		 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR)   || \
		  security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));

	setup_rfi_flush(type, enable);
}

static void __init pnv_setup_arch(void)
{
	set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);

	pnv_setup_rfi_flush();
	setup_stf_barrier();

	/* Initialize SMP */
	pnv_smp_init();

	/* Setup PCI */
	pnv_pci_init();

	/* Setup RTC and NVRAM callbacks */
	if (firmware_has_feature(FW_FEATURE_OPAL))
		opal_nvram_init();

	/* Enable NAP mode */
	powersave_nap = 1;

	/* XXX PMCS */
}

static void __init pnv_init(void)
{
	/*
	 * Initialize the LPC bus now so that legacy serial
	 * ports can be found on it
	 */
	opal_lpc_init();

#ifdef CONFIG_HVC_OPAL
	if (firmware_has_feature(FW_FEATURE_OPAL))
		hvc_opal_init_early();
	else
#endif
		add_preferred_console("hvc", 0, NULL);
}

static void __init pnv_init_IRQ(void)
{
	/* Try using a XIVE if available, otherwise use a XICS */
	if (!xive_native_init())
		xics_init();

	WARN_ON(!ppc_md.get_irq);
}

static void pnv_show_cpuinfo(struct seq_file *m)
{
	struct device_node *root;
	const char *model = "";

	root = of_find_node_by_path("/");
	if (root)
		model = of_get_property(root, "model", NULL);
	seq_printf(m, "machine\t\t: PowerNV %s\n", model);
	if (firmware_has_feature(FW_FEATURE_OPAL))
		seq_printf(m, "firmware\t: OPAL\n");
	else
		seq_printf(m, "firmware\t: BML\n");
	of_node_put(root);
	if (radix_enabled())
		seq_printf(m, "MMU\t\t: Radix\n");
	else
		seq_printf(m, "MMU\t\t: Hash\n");
}

static void pnv_prepare_going_down(void)
{
	/*
	 * Disable all notifiers from OPAL, we can't
	 * service interrupts anymore anyway
	 */
	opal_event_shutdown();

	/* Soft disable interrupts */
	local_irq_disable();

	/*
	 * Return secondary CPUs to firwmare if a flash update
	 * is pending otherwise we will get all sort of error
	 * messages about CPU being stuck etc.. This will also
	 * have the side effect of hard disabling interrupts so
	 * past this point, the kernel is effectively dead.
	 */
	opal_flash_term_callback();
}

static void  __noreturn pnv_restart(char *cmd)
{
	long rc = OPAL_BUSY;

	pnv_prepare_going_down();

	while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
		rc = opal_cec_reboot();
		if (rc == OPAL_BUSY_EVENT)
			opal_poll_events(NULL);
		else
			mdelay(10);
	}
	for (;;)
		opal_poll_events(NULL);
}

static void __noreturn pnv_power_off(void)
{
	long rc = OPAL_BUSY;

	pnv_prepare_going_down();

	while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
		rc = opal_cec_power_down(0);
		if (rc == OPAL_BUSY_EVENT)
			opal_poll_events(NULL);
		else
			mdelay(10);
	}
	for (;;)
		opal_poll_events(NULL);
}

static void __noreturn pnv_halt(void)
{
	pnv_power_off();
}

static void pnv_progress(char *s, unsigned short hex)
{
}

static void pnv_shutdown(void)
{
	/* Let the PCI code clear up IODA tables */
	pnv_pci_shutdown();

	/*
	 * Stop OPAL activity: Unregister all OPAL interrupts so they
	 * don't fire up while we kexec and make sure all potentially
	 * DMA'ing ops are complete (such as dump retrieval).
	 */
	opal_shutdown();
}

#ifdef CONFIG_KEXEC_CORE
static void pnv_kexec_wait_secondaries_down(void)
{
	int my_cpu, i, notified = -1;

	my_cpu = get_cpu();

	for_each_online_cpu(i) {
		uint8_t status;
		int64_t rc, timeout = 1000;

		if (i == my_cpu)
			continue;

		for (;;) {
			rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
						   &status);
			if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
				break;
			barrier();
			if (i != notified) {
				printk(KERN_INFO "kexec: waiting for cpu %d "
				       "(physical %d) to enter OPAL\n",
				       i, paca[i].hw_cpu_id);
				notified = i;
			}

			/*
			 * On crash secondaries might be unreachable or hung,
			 * so timeout if we've waited too long
			 * */
			mdelay(1);
			if (timeout-- == 0) {
				printk(KERN_ERR "kexec: timed out waiting for "
				       "cpu %d (physical %d) to enter OPAL\n",
				       i, paca[i].hw_cpu_id);
				break;
			}
		}
	}
}

static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
{
	u64 reinit_flags;

	if (xive_enabled())
		xive_kexec_teardown_cpu(secondary);
	else
		xics_kexec_teardown_cpu(secondary);

	/* On OPAL, we return all CPUs to firmware */
	if (!firmware_has_feature(FW_FEATURE_OPAL))
		return;

	if (secondary) {
		/* Return secondary CPUs to firmware on OPAL v3 */
		mb();
		get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
		mb();

		/* Return the CPU to OPAL */
		opal_return_cpu();
	} else {
		/* Primary waits for the secondaries to have reached OPAL */
		pnv_kexec_wait_secondaries_down();

		/* Switch XIVE back to emulation mode */
		if (xive_enabled())
			xive_shutdown();

		/*
		 * We might be running as little-endian - now that interrupts
		 * are disabled, reset the HILE bit to big-endian so we don't
		 * take interrupts in the wrong endian later
		 *
		 * We reinit to enable both radix and hash on P9 to ensure
		 * the mode used by the next kernel is always supported.
		 */
		reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
		if (cpu_has_feature(CPU_FTR_ARCH_300))
			reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
				OPAL_REINIT_CPUS_MMU_HASH;
		opal_reinit_cpus(reinit_flags);
	}
}
#endif /* CONFIG_KEXEC_CORE */

#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
static unsigned long pnv_memory_block_size(void)
{
	return 256UL * 1024 * 1024;
}
#endif

static void __init pnv_setup_machdep_opal(void)
{
	ppc_md.get_boot_time = opal_get_boot_time;
	ppc_md.restart = pnv_restart;
	pm_power_off = pnv_power_off;
	ppc_md.halt = pnv_halt;
	/* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
	ppc_md.machine_check_exception = opal_machine_check;
	ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
	ppc_md.hmi_exception_early = opal_hmi_exception_early;
	ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
}

static int __init pnv_probe(void)
{
	if (!of_machine_is_compatible("ibm,powernv"))
		return 0;

	if (firmware_has_feature(FW_FEATURE_OPAL))
		pnv_setup_machdep_opal();

	pr_debug("PowerNV detected !\n");

	pnv_init();

	return 1;
}

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
void __init pnv_tm_init(void)
{
	if (!firmware_has_feature(FW_FEATURE_OPAL) ||
	    !pvr_version_is(PVR_POWER9) ||
	    early_cpu_has_feature(CPU_FTR_TM))
		return;

	if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
		return;

	pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
	cur_cpu_spec->cpu_features |= CPU_FTR_TM;
	/* Make sure "normal" HTM is off (it should be) */
	cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
	/* Turn on no suspend mode, and HTM no SC */
	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
					    PPC_FEATURE2_HTM_NOSC;
	tm_suspend_disabled = true;
}
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */

/*
 * Returns the cpu frequency for 'cpu' in Hz. This is used by
 * /proc/cpuinfo
 */
static unsigned long pnv_get_proc_freq(unsigned int cpu)
{
	unsigned long ret_freq;

	ret_freq = cpufreq_get(cpu) * 1000ul;

	/*
	 * If the backend cpufreq driver does not exist,
         * then fallback to old way of reporting the clockrate.
	 */
	if (!ret_freq)
		ret_freq = ppc_proc_freq;
	return ret_freq;
}

define_machine(powernv) {
	.name			= "PowerNV",
	.probe			= pnv_probe,
	.setup_arch		= pnv_setup_arch,
	.init_IRQ		= pnv_init_IRQ,
	.show_cpuinfo		= pnv_show_cpuinfo,
	.get_proc_freq          = pnv_get_proc_freq,
	.progress		= pnv_progress,
	.machine_shutdown	= pnv_shutdown,
	.power_save             = NULL,
	.calibrate_decr		= generic_calibrate_decr,
#ifdef CONFIG_KEXEC_CORE
	.kexec_cpu_down		= pnv_kexec_cpu_down,
#endif
#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
	.memory_block_size	= pnv_memory_block_size,
#endif
};
Commit	Line	Data
55190f88 BH	1	/*
	2	* PowerNV setup code.
	3	*
	4	* Copyright 2011 IBM Corp.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#undef DEBUG
	13
	14	#include <linux/cpu.h>
	15	#include <linux/errno.h>
	16	#include <linux/sched.h>
	17	#include <linux/kernel.h>
	18	#include <linux/tty.h>
	19	#include <linux/reboot.h>
	20	#include <linux/init.h>
	21	#include <linux/console.h>
	22	#include <linux/delay.h>
	23	#include <linux/irq.h>
	24	#include <linux/seq_file.h>
	25	#include <linux/of.h>
26a2056e	26	#include <linux/of_fdt.h>
55190f88 BH	27	#include <linux/interrupt.h>
55190f88 BH	28	#include <linux/bug.h>
cd15b048	29	#include <linux/pci.h>
fb5153d0	30	#include <linux/cpufreq.h>
55190f88 BH	31
	32	#include <asm/machdep.h>
	33	#include <asm/firmware.h>
	34	#include <asm/xics.h>
243e2511	35	#include <asm/xive.h>
daea1175	36	#include <asm/opal.h>
13906db6	37	#include <asm/kexec.h>
b2a80878	38	#include <asm/smp.h>
54820530	39	#include <asm/tm.h>
6e032b35	40	#include <asm/setup.h>
cbbfac27	41	#include <asm/security_features.h>
55190f88 BH	42
	43	#include "powernv.h"
	44
cbbfac27 ME	45
	46	static bool fw_feature_is(const char state, const char name,
	47	struct device_node *fw_features)
	48	{
	49	struct device_node *np;
	50	bool rc = false;
	51
	52	np = of_get_child_by_name(fw_features, name);
	53	if (np) {
	54	rc = of_property_read_bool(np, state);
	55	of_node_put(np);
	56	}
	57
	58	return rc;
	59	}
	60
	61	static void init_fw_feat_flags(struct device_node *np)
	62	{
	63	if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
	64	security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
	65
	66	if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
	67	security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
	68
d45982af	69	if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
cbbfac27 ME	70	security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
	71
	72	if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
	73	security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
	74
	75	if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
	76	security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
	77
	78	if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
	79	security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
	80
	81	/*
	82	* The features below are enabled by default, so we instead look to see
	83	* if firmware has disabled them, and clear them if so.
	84	*/
	85	if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
	86	security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
	87
	88	if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
	89	security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
	90
	91	if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
	92	security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
	93
	94	if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
	95	security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
	96	}
	97
6e032b35 OH	98	static void pnv_setup_rfi_flush(void)
	99	{
	100	struct device_node np, fw_features;
	101	enum l1d_flush_type type;
d45982af	102	bool enable;
6e032b35 OH	103
	104	/* Default to fallback in case fw-features are not available */
	105	type = L1D_FLUSH_FALLBACK;
6e032b35 OH	106
	107	np = of_find_node_by_name(NULL, "ibm,opal");
	108	fw_features = of_get_child_by_name(np, "fw-features");
	109	of_node_put(np);
	110
	111	if (fw_features) {
cbbfac27	112	init_fw_feat_flags(fw_features);
d45982af	113	of_node_put(fw_features);
cbbfac27	114
d45982af	115	if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
6e032b35 OH	116	type = L1D_FLUSH_MTTRIG;
6e032b35 OH	117
d45982af	118	if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
6e032b35	119	type = L1D_FLUSH_ORI;
6e032b35 OH	120	}
6e032b35 OH	121
d45982af ME	122	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
	123	(security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) \|\| \
	124	security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
	125
	126	setup_rfi_flush(type, enable);
6e032b35 OH	127	}
6e032b35 OH	128
55190f88 BH	129	static void __init pnv_setup_arch(void)
55190f88 BH	130	{
4817fc32 AB	131	set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
4817fc32 AB	132
6e032b35	133	pnv_setup_rfi_flush();
cc437c1d	134	setup_stf_barrier();
6e032b35	135
55190f88 BH	136	/* Initialize SMP */
	137	pnv_smp_init();
	138
61305a96 BH	139	/* Setup PCI */
61305a96 BH	140	pnv_pci_init();
55190f88	141
628daa8d BH	142	/* Setup RTC and NVRAM callbacks */
	143	if (firmware_has_feature(FW_FEATURE_OPAL))
	144	opal_nvram_init();
55190f88 BH	145
	146	/* Enable NAP mode */
	147	powersave_nap = 1;
	148
	149	/* XXX PMCS */
	150	}
	151
f2d57694	152	static void __init pnv_init(void)
55190f88	153	{
3fafe9c2 BH	154	/*
	155	* Initialize the LPC bus now so that legacy serial
	156	* ports can be found on it
	157	*/
	158	opal_lpc_init();
	159
daea1175 BH	160	#ifdef CONFIG_HVC_OPAL
	161	if (firmware_has_feature(FW_FEATURE_OPAL))
	162	hvc_opal_init_early();
	163	else
	164	#endif
	165	add_preferred_console("hvc", 0, NULL);
55190f88 BH	166	}
	167
	168	static void __init pnv_init_IRQ(void)
	169	{
243e2511 BH	170	/* Try using a XIVE if available, otherwise use a XICS */
	171	if (!xive_native_init())
	172	xics_init();
55190f88 BH	173
	174	WARN_ON(!ppc_md.get_irq);
	175	}
	176
	177	static void pnv_show_cpuinfo(struct seq_file *m)
	178	{
	179	struct device_node *root;
	180	const char *model = "";
	181
	182	root = of_find_node_by_path("/");
	183	if (root)
	184	model = of_get_property(root, "model", NULL);
	185	seq_printf(m, "machine\t\t: PowerNV %s\n", model);
e4d54f71 SS	186	if (firmware_has_feature(FW_FEATURE_OPAL))
e4d54f71 SS	187	seq_printf(m, "firmware\t: OPAL\n");
14a43e69 BH	188	else
14a43e69 BH	189	seq_printf(m, "firmware\t: BML\n");
55190f88	190	of_node_put(root);
3a4c2601 AK	191	if (radix_enabled())
	192	seq_printf(m, "MMU\t\t: Radix\n");
	193	else
	194	seq_printf(m, "MMU\t\t: Hash\n");
55190f88 BH	195	}
55190f88 BH	196
2196c6f1 VH	197	static void pnv_prepare_going_down(void)
	198	{
	199	/*
	200	* Disable all notifiers from OPAL, we can't
	201	* service interrupts anymore anyway
	202	*/
81f2f7ce	203	opal_event_shutdown();
2196c6f1 VH	204
	205	/* Soft disable interrupts */
	206	local_irq_disable();
	207
	208	/*
	209	* Return secondary CPUs to firwmare if a flash update
	210	* is pending otherwise we will get all sort of error
	211	* messages about CPU being stuck etc.. This will also
	212	* have the side effect of hard disabling interrupts so
	213	* past this point, the kernel is effectively dead.
	214	*/
	215	opal_flash_term_callback();
	216	}
	217
ec27329f	218	static void __noreturn pnv_restart(char *cmd)
55190f88	219	{
ec27329f BH	220	long rc = OPAL_BUSY;
ec27329f BH	221
2196c6f1	222	pnv_prepare_going_down();
e8e71fa4	223
ec27329f BH	224	while (rc == OPAL_BUSY \|\| rc == OPAL_BUSY_EVENT) {
	225	rc = opal_cec_reboot();
	226	if (rc == OPAL_BUSY_EVENT)
	227	opal_poll_events(NULL);
	228	else
	229	mdelay(10);
	230	}
	231	for (;;)
	232	opal_poll_events(NULL);
55190f88 BH	233	}
55190f88 BH	234
ec27329f	235	static void __noreturn pnv_power_off(void)
55190f88	236	{
ec27329f BH	237	long rc = OPAL_BUSY;
ec27329f BH	238
2196c6f1	239	pnv_prepare_going_down();
e8e71fa4	240
ec27329f BH	241	while (rc == OPAL_BUSY \|\| rc == OPAL_BUSY_EVENT) {
	242	rc = opal_cec_power_down(0);
	243	if (rc == OPAL_BUSY_EVENT)
	244	opal_poll_events(NULL);
	245	else
	246	mdelay(10);
	247	}
	248	for (;;)
	249	opal_poll_events(NULL);
55190f88 BH	250	}
55190f88 BH	251
ec27329f	252	static void __noreturn pnv_halt(void)
55190f88	253	{
ec27329f	254	pnv_power_off();
55190f88 BH	255	}
55190f88 BH	256
628daa8d	257	static void pnv_progress(char *s, unsigned short hex)
55190f88 BH	258	{
	259	}
	260
73ed148a BH	261	static void pnv_shutdown(void)
	262	{
	263	/* Let the PCI code clear up IODA tables */
	264	pnv_pci_shutdown();
	265
f7d98d18 VH	266	/*
	267	* Stop OPAL activity: Unregister all OPAL interrupts so they
	268	* don't fire up while we kexec and make sure all potentially
	269	* DMA'ing ops are complete (such as dump retrieval).
73ed148a BH	270	*/
	271	opal_shutdown();
	272	}
	273
da665885	274	#ifdef CONFIG_KEXEC_CORE
298b34d7 BH	275	static void pnv_kexec_wait_secondaries_down(void)
	276	{
	277	int my_cpu, i, notified = -1;
	278
	279	my_cpu = get_cpu();
	280
	281	for_each_online_cpu(i) {
	282	uint8_t status;
1b70386c	283	int64_t rc, timeout = 1000;
298b34d7 BH	284
	285	if (i == my_cpu)
	286	continue;
	287
	288	for (;;) {
	289	rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
	290	&status);
	291	if (rc != OPAL_SUCCESS \|\| status != OPAL_THREAD_STARTED)
	292	break;
	293	barrier();
	294	if (i != notified) {
	295	printk(KERN_INFO "kexec: waiting for cpu %d "
	296	"(physical %d) to enter OPAL\n",
	297	i, paca[i].hw_cpu_id);
	298	notified = i;
	299	}
1b70386c SMJ	300
	301	/*
	302	* On crash secondaries might be unreachable or hung,
	303	* so timeout if we've waited too long
	304	* */
	305	mdelay(1);
	306	if (timeout-- == 0) {
	307	printk(KERN_ERR "kexec: timed out waiting for "
	308	"cpu %d (physical %d) to enter OPAL\n",
	309	i, paca[i].hw_cpu_id);
	310	break;
	311	}
298b34d7 BH	312	}
	313	}
	314	}
	315
628daa8d	316	static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
55190f88	317	{
1c0eaf0f BH	318	u64 reinit_flags;
1c0eaf0f BH	319
243e2511 BH	320	if (xive_enabled())
	321	xive_kexec_teardown_cpu(secondary);
	322	else
	323	xics_kexec_teardown_cpu(secondary);
13906db6	324
e4d54f71	325	/* On OPAL, we return all CPUs to firmware */
e4d54f71	326	if (!firmware_has_feature(FW_FEATURE_OPAL))
298b34d7 BH	327	return;
	328
	329	if (secondary) {
	330	/* Return secondary CPUs to firmware on OPAL v3 */
13906db6 BH	331	mb();
	332	get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
	333	mb();
	334
	335	/* Return the CPU to OPAL */
	336	opal_return_cpu();
298b34d7 BH	337	} else {
	338	/* Primary waits for the secondaries to have reached OPAL */
	339	pnv_kexec_wait_secondaries_down();
e72bb8a5	340
243e2511 BH	341	/* Switch XIVE back to emulation mode */
	342	if (xive_enabled())
	343	xive_shutdown();
	344
e72bb8a5 SMJ	345	/*
	346	* We might be running as little-endian - now that interrupts
	347	* are disabled, reset the HILE bit to big-endian so we don't
	348	* take interrupts in the wrong endian later
1c0eaf0f BH	349	*
	350	* We reinit to enable both radix and hash on P9 to ensure
	351	* the mode used by the next kernel is always supported.
e72bb8a5	352	*/
1c0eaf0f BH	353	reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
	354	if (cpu_has_feature(CPU_FTR_ARCH_300))
	355	reinit_flags \|= OPAL_REINIT_CPUS_MMU_RADIX \|
	356	OPAL_REINIT_CPUS_MMU_HASH;
	357	opal_reinit_cpus(reinit_flags);
13906db6	358	}
55190f88	359	}
da665885	360	#endif /* CONFIG_KEXEC_CORE */
55190f88	361
6d97d7a2 AB	362	#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
	363	static unsigned long pnv_memory_block_size(void)
	364	{
2d9218e9	365	return 256UL * 1024 * 1024;
6d97d7a2 AB	366	}
	367	#endif
	368
628daa8d	369	static void __init pnv_setup_machdep_opal(void)
55190f88	370	{
628daa8d	371	ppc_md.get_boot_time = opal_get_boot_time;
628daa8d	372	ppc_md.restart = pnv_restart;
9178ba29	373	pm_power_off = pnv_power_off;
628daa8d	374	ppc_md.halt = pnv_halt;
e36d0a2e	375	/* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
ed79ba9e	376	ppc_md.machine_check_exception = opal_machine_check;
55672ecf	377	ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
0869b6fd MS	378	ppc_md.hmi_exception_early = opal_hmi_exception_early;
0869b6fd MS	379	ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
55190f88 BH	380	}
55190f88 BH	381
55190f88 BH	382	static int __init pnv_probe(void)
55190f88 BH	383	{
406b0b6a	384	if (!of_machine_is_compatible("ibm,powernv"))
55190f88 BH	385	return 0;
55190f88 BH	386
628daa8d BH	387	if (firmware_has_feature(FW_FEATURE_OPAL))
628daa8d BH	388	pnv_setup_machdep_opal();
628daa8d	389
55190f88 BH	390	pr_debug("PowerNV detected !\n");
55190f88 BH	391
f2d57694 BH	392	pnv_init();
f2d57694 BH	393
55190f88 BH	394	return 1;
	395	}
	396
54820530 ME	397	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	398	void __init pnv_tm_init(void)
	399	{
	400	if (!firmware_has_feature(FW_FEATURE_OPAL) \|\|
	401	!pvr_version_is(PVR_POWER9) \|\|
	402	early_cpu_has_feature(CPU_FTR_TM))
	403	return;
	404
	405	if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
	406	return;
	407
	408	pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
	409	cur_cpu_spec->cpu_features \|= CPU_FTR_TM;
	410	/* Make sure "normal" HTM is off (it should be) */
	411	cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
	412	/* Turn on no suspend mode, and HTM no SC */
	413	cur_cpu_spec->cpu_user_features2 \|= PPC_FEATURE2_HTM_NO_SUSPEND \| \
	414	PPC_FEATURE2_HTM_NOSC;
	415	tm_suspend_disabled = true;
	416	}
	417	#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
	418
fb5153d0 GS	419	/*
	420	* Returns the cpu frequency for 'cpu' in Hz. This is used by
	421	* /proc/cpuinfo
	422	*/
e51df2c1	423	static unsigned long pnv_get_proc_freq(unsigned int cpu)
fb5153d0 GS	424	{
	425	unsigned long ret_freq;
	426
cd77b5ce	427	ret_freq = cpufreq_get(cpu) * 1000ul;
fb5153d0 GS	428
	429	/*
	430	* If the backend cpufreq driver does not exist,
	431	* then fallback to old way of reporting the clockrate.
	432	*/
	433	if (!ret_freq)
	434	ret_freq = ppc_proc_freq;
	435	return ret_freq;
	436	}
	437
55190f88 BH	438	define_machine(powernv) {
	439	.name = "PowerNV",
	440	.probe = pnv_probe,
628daa8d	441	.setup_arch = pnv_setup_arch,
55190f88 BH	442	.init_IRQ = pnv_init_IRQ,
55190f88 BH	443	.show_cpuinfo = pnv_show_cpuinfo,
fb5153d0	444	.get_proc_freq = pnv_get_proc_freq,
55190f88	445	.progress = pnv_progress,
73ed148a	446	.machine_shutdown = pnv_shutdown,
5593e303	447	.power_save = NULL,
55190f88	448	.calibrate_decr = generic_calibrate_decr,
da665885	449	#ifdef CONFIG_KEXEC_CORE
55190f88 BH	450	.kexec_cpu_down = pnv_kexec_cpu_down,
55190f88 BH	451	#endif
6d97d7a2 AB	452	#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
	453	.memory_block_size = pnv_memory_block_size,
	454	#endif
55190f88	455	};