]>
Commit | Line | Data |
---|---|---|
5d5a0936 | 1 | /* |
5d5a0936 LV |
2 | * PCI address cache; allows the lookup of PCI devices based on I/O address |
3 | * | |
3c8c90ab LV |
4 | * Copyright IBM Corporation 2004 |
5 | * Copyright Linas Vepstas <linas@austin.ibm.com> 2004 | |
5d5a0936 LV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <linux/list.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/rbtree.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
5d5a0936 | 26 | #include <linux/spinlock.h> |
60063497 | 27 | #include <linux/atomic.h> |
5d5a0936 LV |
28 | #include <asm/pci-bridge.h> |
29 | #include <asm/ppc-pci.h> | |
5d5a0936 | 30 | |
5d5a0936 LV |
31 | |
32 | /** | |
33 | * The pci address cache subsystem. This subsystem places | |
34 | * PCI device address resources into a red-black tree, sorted | |
35 | * according to the address range, so that given only an i/o | |
36 | * address, the corresponding PCI device can be **quickly** | |
37 | * found. It is safe to perform an address lookup in an interrupt | |
38 | * context; this ability is an important feature. | |
39 | * | |
40 | * Currently, the only customer of this code is the EEH subsystem; | |
41 | * thus, this code has been somewhat tailored to suit EEH better. | |
42 | * In particular, the cache does *not* hold the addresses of devices | |
43 | * for which EEH is not enabled. | |
44 | * | |
45 | * (Implementation Note: The RB tree seems to be better/faster | |
46 | * than any hash algo I could think of for this problem, even | |
47 | * with the penalty of slow pointer chases for d-cache misses). | |
48 | */ | |
29f8bf1b | 49 | struct pci_io_addr_range { |
5d5a0936 LV |
50 | struct rb_node rb_node; |
51 | unsigned long addr_lo; | |
52 | unsigned long addr_hi; | |
53 | struct pci_dev *pcidev; | |
54 | unsigned int flags; | |
55 | }; | |
56 | ||
29f8bf1b | 57 | static struct pci_io_addr_cache { |
5d5a0936 LV |
58 | struct rb_root rb_root; |
59 | spinlock_t piar_lock; | |
60 | } pci_io_addr_cache_root; | |
61 | ||
def9d83d | 62 | static inline struct pci_dev *__pci_addr_cache_get_device(unsigned long addr) |
5d5a0936 LV |
63 | { |
64 | struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; | |
65 | ||
66 | while (n) { | |
67 | struct pci_io_addr_range *piar; | |
68 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
69 | ||
70 | if (addr < piar->addr_lo) { | |
71 | n = n->rb_left; | |
72 | } else { | |
73 | if (addr > piar->addr_hi) { | |
74 | n = n->rb_right; | |
75 | } else { | |
76 | pci_dev_get(piar->pcidev); | |
77 | return piar->pcidev; | |
78 | } | |
79 | } | |
80 | } | |
81 | ||
82 | return NULL; | |
83 | } | |
84 | ||
85 | /** | |
def9d83d | 86 | * pci_addr_cache_get_device - Get device, given only address |
5d5a0936 LV |
87 | * @addr: mmio (PIO) phys address or i/o port number |
88 | * | |
89 | * Given an mmio phys address, or a port number, find a pci device | |
90 | * that implements this address. Be sure to pci_dev_put the device | |
91 | * when finished. I/O port numbers are assumed to be offset | |
92 | * from zero (that is, they do *not* have pci_io_addr added in). | |
93 | * It is safe to call this function within an interrupt. | |
94 | */ | |
def9d83d | 95 | struct pci_dev *pci_addr_cache_get_device(unsigned long addr) |
5d5a0936 LV |
96 | { |
97 | struct pci_dev *dev; | |
98 | unsigned long flags; | |
99 | ||
100 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
def9d83d | 101 | dev = __pci_addr_cache_get_device(addr); |
5d5a0936 LV |
102 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
103 | return dev; | |
104 | } | |
105 | ||
106 | #ifdef DEBUG | |
107 | /* | |
108 | * Handy-dandy debug print routine, does nothing more | |
109 | * than print out the contents of our addr cache. | |
110 | */ | |
111 | static void pci_addr_cache_print(struct pci_io_addr_cache *cache) | |
112 | { | |
113 | struct rb_node *n; | |
114 | int cnt = 0; | |
115 | ||
116 | n = rb_first(&cache->rb_root); | |
117 | while (n) { | |
118 | struct pci_io_addr_range *piar; | |
119 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
120 | printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n", | |
121 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, | |
122 | piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev)); | |
123 | cnt++; | |
124 | n = rb_next(n); | |
125 | } | |
126 | } | |
127 | #endif | |
128 | ||
129 | /* Insert address range into the rb tree. */ | |
130 | static struct pci_io_addr_range * | |
131 | pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo, | |
132 | unsigned long ahi, unsigned int flags) | |
133 | { | |
134 | struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; | |
135 | struct rb_node *parent = NULL; | |
136 | struct pci_io_addr_range *piar; | |
137 | ||
138 | /* Walk tree, find a place to insert into tree */ | |
139 | while (*p) { | |
140 | parent = *p; | |
141 | piar = rb_entry(parent, struct pci_io_addr_range, rb_node); | |
142 | if (ahi < piar->addr_lo) { | |
143 | p = &parent->rb_left; | |
144 | } else if (alo > piar->addr_hi) { | |
145 | p = &parent->rb_right; | |
146 | } else { | |
147 | if (dev != piar->pcidev || | |
148 | alo != piar->addr_lo || ahi != piar->addr_hi) { | |
149 | printk(KERN_WARNING "PIAR: overlapping address range\n"); | |
150 | } | |
151 | return piar; | |
152 | } | |
153 | } | |
7e4bbaf0 | 154 | piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); |
5d5a0936 LV |
155 | if (!piar) |
156 | return NULL; | |
157 | ||
af525592 | 158 | pci_dev_get(dev); |
5d5a0936 LV |
159 | piar->addr_lo = alo; |
160 | piar->addr_hi = ahi; | |
161 | piar->pcidev = dev; | |
162 | piar->flags = flags; | |
163 | ||
164 | #ifdef DEBUG | |
165 | printk(KERN_DEBUG "PIAR: insert range=[%lx:%lx] dev=%s\n", | |
29f8bf1b | 166 | alo, ahi, pci_name(dev)); |
5d5a0936 LV |
167 | #endif |
168 | ||
169 | rb_link_node(&piar->rb_node, parent, p); | |
170 | rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); | |
171 | ||
172 | return piar; | |
173 | } | |
174 | ||
175 | static void __pci_addr_cache_insert_device(struct pci_dev *dev) | |
176 | { | |
177 | struct device_node *dn; | |
d50a7d4c | 178 | struct eeh_dev *edev; |
5d5a0936 | 179 | int i; |
5d5a0936 LV |
180 | |
181 | dn = pci_device_to_OF_node(dev); | |
182 | if (!dn) { | |
183 | printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n", pci_name(dev)); | |
184 | return; | |
185 | } | |
186 | ||
d50a7d4c GS |
187 | edev = of_node_to_eeh_dev(dn); |
188 | if (!edev) { | |
189 | pr_warning("PCI: no EEH dev found for dn=%s\n", | |
190 | dn->full_name); | |
191 | return; | |
192 | } | |
193 | ||
5d5a0936 | 194 | /* Skip any devices for which EEH is not enabled. */ |
dbbceee1 | 195 | if (!edev->pe) { |
5d5a0936 | 196 | #ifdef DEBUG |
d50a7d4c GS |
197 | pr_info("PCI: skip building address cache for=%s - %s\n", |
198 | pci_name(dev), dn->full_name); | |
5d5a0936 LV |
199 | #endif |
200 | return; | |
201 | } | |
202 | ||
5d5a0936 LV |
203 | /* Walk resources on this device, poke them into the tree */ |
204 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
205 | unsigned long start = pci_resource_start(dev,i); | |
206 | unsigned long end = pci_resource_end(dev,i); | |
207 | unsigned int flags = pci_resource_flags(dev,i); | |
208 | ||
209 | /* We are interested only bus addresses, not dma or other stuff */ | |
210 | if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
211 | continue; | |
212 | if (start == 0 || ~start == 0 || end == 0 || ~end == 0) | |
213 | continue; | |
214 | pci_addr_cache_insert(dev, start, end, flags); | |
5d5a0936 | 215 | } |
5d5a0936 LV |
216 | } |
217 | ||
218 | /** | |
219 | * pci_addr_cache_insert_device - Add a device to the address cache | |
220 | * @dev: PCI device whose I/O addresses we are interested in. | |
221 | * | |
222 | * In order to support the fast lookup of devices based on addresses, | |
223 | * we maintain a cache of devices that can be quickly searched. | |
224 | * This routine adds a device to that cache. | |
225 | */ | |
226 | void pci_addr_cache_insert_device(struct pci_dev *dev) | |
227 | { | |
228 | unsigned long flags; | |
229 | ||
093eda3c LV |
230 | /* Ignore PCI bridges */ |
231 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) | |
232 | return; | |
233 | ||
5d5a0936 LV |
234 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); |
235 | __pci_addr_cache_insert_device(dev); | |
236 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
237 | } | |
238 | ||
239 | static inline void __pci_addr_cache_remove_device(struct pci_dev *dev) | |
240 | { | |
241 | struct rb_node *n; | |
5d5a0936 LV |
242 | |
243 | restart: | |
244 | n = rb_first(&pci_io_addr_cache_root.rb_root); | |
245 | while (n) { | |
246 | struct pci_io_addr_range *piar; | |
247 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
248 | ||
249 | if (piar->pcidev == dev) { | |
250 | rb_erase(n, &pci_io_addr_cache_root.rb_root); | |
af525592 | 251 | pci_dev_put(piar->pcidev); |
5d5a0936 LV |
252 | kfree(piar); |
253 | goto restart; | |
254 | } | |
255 | n = rb_next(n); | |
256 | } | |
5d5a0936 LV |
257 | } |
258 | ||
259 | /** | |
260 | * pci_addr_cache_remove_device - remove pci device from addr cache | |
261 | * @dev: device to remove | |
262 | * | |
263 | * Remove a device from the addr-cache tree. | |
264 | * This is potentially expensive, since it will walk | |
265 | * the tree multiple times (once per resource). | |
266 | * But so what; device removal doesn't need to be that fast. | |
267 | */ | |
268 | void pci_addr_cache_remove_device(struct pci_dev *dev) | |
269 | { | |
270 | unsigned long flags; | |
271 | ||
272 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
273 | __pci_addr_cache_remove_device(dev); | |
274 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
275 | } | |
276 | ||
277 | /** | |
278 | * pci_addr_cache_build - Build a cache of I/O addresses | |
279 | * | |
280 | * Build a cache of pci i/o addresses. This cache will be used to | |
281 | * find the pci device that corresponds to a given address. | |
282 | * This routine scans all pci busses to build the cache. | |
283 | * Must be run late in boot process, after the pci controllers | |
d6e05edc | 284 | * have been scanned for devices (after all device resources are known). |
5d5a0936 LV |
285 | */ |
286 | void __init pci_addr_cache_build(void) | |
287 | { | |
288 | struct device_node *dn; | |
d50a7d4c | 289 | struct eeh_dev *edev; |
5d5a0936 LV |
290 | struct pci_dev *dev = NULL; |
291 | ||
292 | spin_lock_init(&pci_io_addr_cache_root.piar_lock); | |
293 | ||
6901c6cc | 294 | for_each_pci_dev(dev) { |
5d5a0936 LV |
295 | pci_addr_cache_insert_device(dev); |
296 | ||
5d5a0936 | 297 | dn = pci_device_to_OF_node(dev); |
ccba051c NL |
298 | if (!dn) |
299 | continue; | |
d50a7d4c GS |
300 | |
301 | edev = of_node_to_eeh_dev(dn); | |
302 | if (!edev) | |
303 | continue; | |
304 | ||
093eda3c | 305 | pci_dev_get(dev); /* matching put is in eeh_remove_device() */ |
d50a7d4c GS |
306 | dev->dev.archdata.edev = edev; |
307 | edev->pdev = dev; | |
e1d04c97 LV |
308 | |
309 | eeh_sysfs_add_device(dev); | |
5d5a0936 LV |
310 | } |
311 | ||
312 | #ifdef DEBUG | |
313 | /* Verify tree built up above, echo back the list of addrs. */ | |
314 | pci_addr_cache_print(&pci_io_addr_cache_root); | |
315 | #endif | |
316 | } | |
317 |