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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <linux/config.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/prom.h> | |
38 | #include <asm/rtas.h> | |
1da177e4 LT |
39 | #include <asm/iommu.h> |
40 | #include <asm/pci-bridge.h> | |
41 | #include <asm/machdep.h> | |
42 | #include <asm/abs_addr.h> | |
1da177e4 | 43 | #include <asm/pSeries_reconfig.h> |
1ababe11 | 44 | #include <asm/firmware.h> |
c707ffcf | 45 | #include <asm/tce.h> |
d387899f | 46 | #include <asm/ppc-pci.h> |
2249ca9d | 47 | #include <asm/udbg.h> |
1da177e4 | 48 | |
a1218720 ME |
49 | #include "plpar_wrappers.h" |
50 | ||
1da177e4 LT |
51 | #define DBG(fmt...) |
52 | ||
bc97ce95 OJ |
53 | static void tce_build_pSeries(struct iommu_table *tbl, long index, |
54 | long npages, unsigned long uaddr, | |
1da177e4 LT |
55 | enum dma_data_direction direction) |
56 | { | |
bc97ce95 OJ |
57 | u64 proto_tce; |
58 | u64 *tcep; | |
59 | u64 rpn; | |
1da177e4 | 60 | |
d0035c62 OJ |
61 | index <<= TCE_PAGE_FACTOR; |
62 | npages <<= TCE_PAGE_FACTOR; | |
63 | ||
bc97ce95 | 64 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
65 | |
66 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 67 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 68 | |
bc97ce95 | 69 | tcep = ((u64 *)tbl->it_base) + index; |
1da177e4 LT |
70 | |
71 | while (npages--) { | |
72 | /* can't move this out since we might cross LMB boundary */ | |
bc97ce95 OJ |
73 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
74 | *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; | |
1da177e4 | 75 | |
d0035c62 | 76 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 77 | tcep++; |
1da177e4 LT |
78 | } |
79 | } | |
80 | ||
81 | ||
82 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
83 | { | |
bc97ce95 | 84 | u64 *tcep; |
1da177e4 | 85 | |
d0035c62 OJ |
86 | npages <<= TCE_PAGE_FACTOR; |
87 | index <<= TCE_PAGE_FACTOR; | |
88 | ||
bc97ce95 OJ |
89 | tcep = ((u64 *)tbl->it_base) + index; |
90 | ||
91 | while (npages--) | |
92 | *(tcep++) = 0; | |
1da177e4 LT |
93 | } |
94 | ||
95 | ||
96 | static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
97 | long npages, unsigned long uaddr, | |
98 | enum dma_data_direction direction) | |
99 | { | |
100 | u64 rc; | |
bc97ce95 OJ |
101 | u64 proto_tce, tce; |
102 | u64 rpn; | |
1da177e4 | 103 | |
cc8b5c96 MO |
104 | tcenum <<= TCE_PAGE_FACTOR; |
105 | npages <<= TCE_PAGE_FACTOR; | |
106 | ||
bc97ce95 OJ |
107 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
108 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 109 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 110 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
111 | |
112 | while (npages--) { | |
bc97ce95 OJ |
113 | tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
114 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); | |
115 | ||
1da177e4 LT |
116 | if (rc && printk_ratelimit()) { |
117 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
118 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
119 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
bc97ce95 | 120 | printk("\ttce val = 0x%lx\n", tce ); |
1da177e4 LT |
121 | show_stack(current, (unsigned long *)__get_SP()); |
122 | } | |
bc97ce95 | 123 | |
1da177e4 | 124 | tcenum++; |
bc97ce95 | 125 | rpn++; |
1da177e4 LT |
126 | } |
127 | } | |
128 | ||
bc97ce95 | 129 | static DEFINE_PER_CPU(u64 *, tce_page) = NULL; |
1da177e4 LT |
130 | |
131 | static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
132 | long npages, unsigned long uaddr, | |
133 | enum dma_data_direction direction) | |
134 | { | |
135 | u64 rc; | |
bc97ce95 OJ |
136 | u64 proto_tce; |
137 | u64 *tcep; | |
138 | u64 rpn; | |
1da177e4 LT |
139 | long l, limit; |
140 | ||
6fbb618f | 141 | if (TCE_PAGE_FACTOR == 0 && npages == 1) |
1da177e4 LT |
142 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
143 | direction); | |
144 | ||
145 | tcep = __get_cpu_var(tce_page); | |
146 | ||
147 | /* This is safe to do since interrupts are off when we're called | |
148 | * from iommu_alloc{,_sg}() | |
149 | */ | |
150 | if (!tcep) { | |
bc97ce95 | 151 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 LT |
152 | /* If allocation fails, fall back to the loop implementation */ |
153 | if (!tcep) | |
154 | return tce_build_pSeriesLP(tbl, tcenum, npages, | |
155 | uaddr, direction); | |
156 | __get_cpu_var(tce_page) = tcep; | |
157 | } | |
158 | ||
cc8b5c96 MO |
159 | tcenum <<= TCE_PAGE_FACTOR; |
160 | npages <<= TCE_PAGE_FACTOR; | |
161 | ||
bc97ce95 OJ |
162 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
163 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 164 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 165 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
166 | |
167 | /* We can map max one pageful of TCEs at a time */ | |
168 | do { | |
169 | /* | |
170 | * Set up the page with TCE data, looping through and setting | |
171 | * the values. | |
172 | */ | |
bc97ce95 | 173 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
174 | |
175 | for (l = 0; l < limit; l++) { | |
bc97ce95 OJ |
176 | tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
177 | rpn++; | |
1da177e4 LT |
178 | } |
179 | ||
180 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
181 | (u64)tcenum << 12, | |
182 | (u64)virt_to_abs(tcep), | |
183 | limit); | |
184 | ||
185 | npages -= limit; | |
186 | tcenum += limit; | |
187 | } while (npages > 0 && !rc); | |
188 | ||
189 | if (rc && printk_ratelimit()) { | |
190 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
191 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
192 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
bc97ce95 | 193 | printk("\ttce[0] val = 0x%lx\n", tcep[0]); |
1da177e4 LT |
194 | show_stack(current, (unsigned long *)__get_SP()); |
195 | } | |
196 | } | |
197 | ||
198 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
199 | { | |
200 | u64 rc; | |
1da177e4 | 201 | |
d0035c62 OJ |
202 | tcenum <<= TCE_PAGE_FACTOR; |
203 | npages <<= TCE_PAGE_FACTOR; | |
204 | ||
1da177e4 | 205 | while (npages--) { |
bc97ce95 | 206 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); |
1da177e4 LT |
207 | |
208 | if (rc && printk_ratelimit()) { | |
209 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
210 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
211 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
1da177e4 LT |
212 | show_stack(current, (unsigned long *)__get_SP()); |
213 | } | |
214 | ||
215 | tcenum++; | |
216 | } | |
217 | } | |
218 | ||
219 | ||
220 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
221 | { | |
222 | u64 rc; | |
1da177e4 | 223 | |
d0035c62 OJ |
224 | tcenum <<= TCE_PAGE_FACTOR; |
225 | npages <<= TCE_PAGE_FACTOR; | |
226 | ||
bc97ce95 | 227 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
228 | |
229 | if (rc && printk_ratelimit()) { | |
230 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
231 | printk("\trc = %ld\n", rc); | |
232 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
233 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
1da177e4 LT |
234 | show_stack(current, (unsigned long *)__get_SP()); |
235 | } | |
236 | } | |
237 | ||
238 | static void iommu_table_setparms(struct pci_controller *phb, | |
239 | struct device_node *dn, | |
bc97ce95 | 240 | struct iommu_table *tbl) |
1da177e4 LT |
241 | { |
242 | struct device_node *node; | |
243 | unsigned long *basep; | |
244 | unsigned int *sizep; | |
245 | ||
246 | node = (struct device_node *)phb->arch_data; | |
247 | ||
248 | basep = (unsigned long *)get_property(node, "linux,tce-base", NULL); | |
249 | sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL); | |
250 | if (basep == NULL || sizep == NULL) { | |
251 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
252 | "missing tce entries !\n", dn->full_name); | |
253 | return; | |
254 | } | |
255 | ||
256 | tbl->it_base = (unsigned long)__va(*basep); | |
257 | memset((void *)tbl->it_base, 0, *sizep); | |
258 | ||
259 | tbl->it_busno = phb->bus->number; | |
bc97ce95 | 260 | |
1da177e4 LT |
261 | /* Units of tce entries */ |
262 | tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT; | |
bc97ce95 | 263 | |
1da177e4 | 264 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
265 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
266 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 267 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 268 | } |
bc97ce95 | 269 | |
1da177e4 LT |
270 | phb->dma_window_base_cur += phb->dma_window_size; |
271 | ||
272 | /* Set the tce table size - measured in entries */ | |
273 | tbl->it_size = phb->dma_window_size >> PAGE_SHIFT; | |
274 | ||
275 | tbl->it_index = 0; | |
276 | tbl->it_blocksize = 16; | |
277 | tbl->it_type = TCE_PCI; | |
278 | } | |
279 | ||
280 | /* | |
281 | * iommu_table_setparms_lpar | |
282 | * | |
283 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
284 | */ |
285 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
286 | struct device_node *dn, | |
287 | struct iommu_table *tbl, | |
4c76e0bc | 288 | unsigned char *dma_window) |
1da177e4 | 289 | { |
4c76e0bc JK |
290 | unsigned long offset, size; |
291 | ||
1635317f | 292 | tbl->it_busno = PCI_DN(dn)->bussubno; |
4c76e0bc | 293 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 294 | |
1da177e4 | 295 | tbl->it_base = 0; |
1da177e4 LT |
296 | tbl->it_blocksize = 16; |
297 | tbl->it_type = TCE_PCI; | |
4c76e0bc JK |
298 | tbl->it_offset = offset >> PAGE_SHIFT; |
299 | tbl->it_size = size >> PAGE_SHIFT; | |
1da177e4 LT |
300 | } |
301 | ||
302 | static void iommu_bus_setup_pSeries(struct pci_bus *bus) | |
303 | { | |
3c2822cc | 304 | struct device_node *dn; |
1da177e4 | 305 | struct iommu_table *tbl; |
3c2822cc OJ |
306 | struct device_node *isa_dn, *isa_dn_orig; |
307 | struct device_node *tmp; | |
308 | struct pci_dn *pci; | |
309 | int children; | |
1da177e4 LT |
310 | |
311 | DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self); | |
312 | ||
3c2822cc OJ |
313 | dn = pci_bus_to_OF_node(bus); |
314 | pci = PCI_DN(dn); | |
315 | ||
316 | if (bus->self) { | |
317 | /* This is not a root bus, any setup will be done for the | |
318 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
319 | */ | |
320 | return; | |
321 | } | |
322 | ||
323 | /* Check if the ISA bus on the system is under | |
324 | * this PHB. | |
1da177e4 | 325 | */ |
3c2822cc | 326 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 327 | |
3c2822cc OJ |
328 | while (isa_dn && isa_dn != dn) |
329 | isa_dn = isa_dn->parent; | |
330 | ||
331 | if (isa_dn_orig) | |
332 | of_node_put(isa_dn_orig); | |
1da177e4 | 333 | |
3c2822cc OJ |
334 | /* Count number of direct PCI children of the PHB. |
335 | * All PCI device nodes have class-code property, so it's | |
336 | * an easy way to find them. | |
337 | */ | |
338 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) | |
339 | if (get_property(tmp, "class-code", NULL)) | |
340 | children++; | |
1da177e4 | 341 | |
3c2822cc | 342 | DBG("Children: %d\n", children); |
1da177e4 | 343 | |
3c2822cc OJ |
344 | /* Calculate amount of DMA window per slot. Each window must be |
345 | * a power of two (due to pci_alloc_consistent requirements). | |
346 | * | |
347 | * Keep 256MB aside for PHBs with ISA. | |
348 | */ | |
1da177e4 | 349 | |
3c2822cc OJ |
350 | if (!isa_dn) { |
351 | /* No ISA/IDE - just set window size and return */ | |
352 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
353 | ||
354 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
355 | pci->phb->dma_window_size >>= 1; | |
f951da37 AB |
356 | DBG("No ISA/IDE, window size is 0x%lx\n", |
357 | pci->phb->dma_window_size); | |
3c2822cc OJ |
358 | pci->phb->dma_window_base_cur = 0; |
359 | ||
360 | return; | |
1da177e4 | 361 | } |
3c2822cc OJ |
362 | |
363 | /* If we have ISA, then we probably have an IDE | |
364 | * controller too. Allocate a 128MB table but | |
365 | * skip the first 128MB to avoid stepping on ISA | |
366 | * space. | |
367 | */ | |
368 | pci->phb->dma_window_size = 0x8000000ul; | |
369 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
370 | ||
371 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
372 | ||
373 | iommu_table_setparms(pci->phb, dn, tbl); | |
374 | pci->iommu_table = iommu_init_table(tbl); | |
375 | ||
376 | /* Divide the rest (1.75GB) among the children */ | |
377 | pci->phb->dma_window_size = 0x80000000ul; | |
378 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
379 | pci->phb->dma_window_size >>= 1; | |
380 | ||
f951da37 | 381 | DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); |
3c2822cc | 382 | |
1da177e4 LT |
383 | } |
384 | ||
385 | ||
386 | static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus) | |
387 | { | |
388 | struct iommu_table *tbl; | |
389 | struct device_node *dn, *pdn; | |
1635317f | 390 | struct pci_dn *ppci; |
4c76e0bc | 391 | unsigned char *dma_window = NULL; |
1da177e4 LT |
392 | |
393 | DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self); | |
394 | ||
395 | dn = pci_bus_to_OF_node(bus); | |
396 | ||
397 | /* Find nearest ibm,dma-window, walking up the device tree */ | |
398 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
4c76e0bc | 399 | dma_window = get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
400 | if (dma_window != NULL) |
401 | break; | |
402 | } | |
403 | ||
404 | if (dma_window == NULL) { | |
405 | DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name); | |
406 | return; | |
407 | } | |
408 | ||
e07102db | 409 | ppci = PCI_DN(pdn); |
1635317f | 410 | if (!ppci->iommu_table) { |
1da177e4 LT |
411 | /* Bussubno hasn't been copied yet. |
412 | * Do it now because iommu_table_setparms_lpar needs it. | |
413 | */ | |
1635317f PM |
414 | |
415 | ppci->bussubno = bus->number; | |
1da177e4 LT |
416 | |
417 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
418 | GFP_KERNEL); | |
bc97ce95 | 419 | |
1635317f | 420 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); |
1da177e4 | 421 | |
1635317f | 422 | ppci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
423 | } |
424 | ||
425 | if (pdn != dn) | |
1635317f | 426 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
427 | } |
428 | ||
429 | ||
430 | static void iommu_dev_setup_pSeries(struct pci_dev *dev) | |
431 | { | |
432 | struct device_node *dn, *mydn; | |
3c2822cc | 433 | struct iommu_table *tbl; |
1da177e4 | 434 | |
f951da37 | 435 | DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, pci_name(dev)); |
1da177e4 | 436 | |
1da177e4 LT |
437 | mydn = dn = pci_device_to_OF_node(dev); |
438 | ||
3c2822cc OJ |
439 | /* If we're the direct child of a root bus, then we need to allocate |
440 | * an iommu table ourselves. The bus setup code should have setup | |
441 | * the window sizes already. | |
442 | */ | |
443 | if (!dev->bus->self) { | |
444 | DBG(" --> first child, no bridge. Allocating iommu table.\n"); | |
445 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
446 | iommu_table_setparms(PCI_DN(dn)->phb, dn, tbl); | |
447 | PCI_DN(mydn)->iommu_table = iommu_init_table(tbl); | |
448 | ||
449 | return; | |
450 | } | |
451 | ||
452 | /* If this device is further down the bus tree, search upwards until | |
453 | * an already allocated iommu table is found and use that. | |
454 | */ | |
455 | ||
e07102db | 456 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
457 | dn = dn->parent; |
458 | ||
e07102db | 459 | if (dn && PCI_DN(dn)) { |
1635317f | 460 | PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table; |
1da177e4 | 461 | } else { |
f951da37 | 462 | DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, pci_name(dev)); |
1da177e4 LT |
463 | } |
464 | } | |
465 | ||
466 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
467 | { | |
468 | int err = NOTIFY_OK; | |
469 | struct device_node *np = node; | |
e07102db | 470 | struct pci_dn *pci = PCI_DN(np); |
1da177e4 LT |
471 | |
472 | switch (action) { | |
473 | case PSERIES_RECONFIG_REMOVE: | |
8902e87f | 474 | if (pci && pci->iommu_table && |
1da177e4 LT |
475 | get_property(np, "ibm,dma-window", NULL)) |
476 | iommu_free_table(np); | |
477 | break; | |
478 | default: | |
479 | err = NOTIFY_DONE; | |
480 | break; | |
481 | } | |
482 | return err; | |
483 | } | |
484 | ||
485 | static struct notifier_block iommu_reconfig_nb = { | |
486 | .notifier_call = iommu_reconfig_notifier, | |
487 | }; | |
488 | ||
489 | static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev) | |
490 | { | |
491 | struct device_node *pdn, *dn; | |
492 | struct iommu_table *tbl; | |
4c76e0bc | 493 | unsigned char *dma_window = NULL; |
1635317f | 494 | struct pci_dn *pci; |
1da177e4 | 495 | |
f951da37 | 496 | DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, pci_name(dev)); |
1da177e4 LT |
497 | |
498 | /* dev setup for LPAR is a little tricky, since the device tree might | |
499 | * contain the dma-window properties per-device and not neccesarily | |
500 | * for the bus. So we need to search upwards in the tree until we | |
501 | * either hit a dma-window property, OR find a parent with a table | |
502 | * already allocated. | |
503 | */ | |
504 | dn = pci_device_to_OF_node(dev); | |
505 | ||
e07102db | 506 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f | 507 | pdn = pdn->parent) { |
4c76e0bc | 508 | dma_window = get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
509 | if (dma_window) |
510 | break; | |
511 | } | |
512 | ||
513 | /* Check for parent == NULL so we don't try to setup the empty EADS | |
514 | * slots on POWER4 machines. | |
515 | */ | |
516 | if (dma_window == NULL || pdn->parent == NULL) { | |
586a90eb AB |
517 | DBG("No dma window for device, linking to parent\n"); |
518 | PCI_DN(dn)->iommu_table = PCI_DN(pdn)->iommu_table; | |
1da177e4 LT |
519 | return; |
520 | } else { | |
521 | DBG("Found DMA window, allocating table\n"); | |
522 | } | |
523 | ||
e07102db | 524 | pci = PCI_DN(pdn); |
1635317f | 525 | if (!pci->iommu_table) { |
1da177e4 | 526 | /* iommu_table_setparms_lpar needs bussubno. */ |
1635317f | 527 | pci->bussubno = pci->phb->bus->number; |
1da177e4 LT |
528 | |
529 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
530 | GFP_KERNEL); | |
531 | ||
1635317f | 532 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); |
1da177e4 | 533 | |
1635317f | 534 | pci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
535 | } |
536 | ||
537 | if (pdn != dn) | |
1635317f | 538 | PCI_DN(dn)->iommu_table = pci->iommu_table; |
1da177e4 LT |
539 | } |
540 | ||
541 | static void iommu_bus_setup_null(struct pci_bus *b) { } | |
542 | static void iommu_dev_setup_null(struct pci_dev *d) { } | |
543 | ||
544 | /* These are called very early. */ | |
545 | void iommu_init_early_pSeries(void) | |
546 | { | |
547 | if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) { | |
548 | /* Direct I/O, IOMMU off */ | |
549 | ppc_md.iommu_dev_setup = iommu_dev_setup_null; | |
550 | ppc_md.iommu_bus_setup = iommu_bus_setup_null; | |
551 | pci_direct_iommu_init(); | |
552 | ||
553 | return; | |
554 | } | |
555 | ||
57cfb814 | 556 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 557 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
558 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
559 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
560 | } else { | |
561 | ppc_md.tce_build = tce_build_pSeriesLP; | |
562 | ppc_md.tce_free = tce_free_pSeriesLP; | |
563 | } | |
564 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP; | |
565 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP; | |
566 | } else { | |
567 | ppc_md.tce_build = tce_build_pSeries; | |
568 | ppc_md.tce_free = tce_free_pSeries; | |
569 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries; | |
570 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries; | |
571 | } | |
572 | ||
573 | ||
574 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
575 | ||
576 | pci_iommu_init(); | |
577 | } | |
578 |