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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <asm/io.h> | |
36 | #include <asm/prom.h> | |
37 | #include <asm/rtas.h> | |
1da177e4 LT |
38 | #include <asm/iommu.h> |
39 | #include <asm/pci-bridge.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/abs_addr.h> | |
1da177e4 | 42 | #include <asm/pSeries_reconfig.h> |
1ababe11 | 43 | #include <asm/firmware.h> |
c707ffcf | 44 | #include <asm/tce.h> |
d387899f | 45 | #include <asm/ppc-pci.h> |
2249ca9d | 46 | #include <asm/udbg.h> |
1da177e4 | 47 | |
a1218720 ME |
48 | #include "plpar_wrappers.h" |
49 | ||
1da177e4 | 50 | |
bc97ce95 OJ |
51 | static void tce_build_pSeries(struct iommu_table *tbl, long index, |
52 | long npages, unsigned long uaddr, | |
1da177e4 LT |
53 | enum dma_data_direction direction) |
54 | { | |
bc97ce95 OJ |
55 | u64 proto_tce; |
56 | u64 *tcep; | |
57 | u64 rpn; | |
1da177e4 | 58 | |
bc97ce95 | 59 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
60 | |
61 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 62 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 63 | |
bc97ce95 | 64 | tcep = ((u64 *)tbl->it_base) + index; |
1da177e4 LT |
65 | |
66 | while (npages--) { | |
67 | /* can't move this out since we might cross LMB boundary */ | |
bc97ce95 OJ |
68 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
69 | *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; | |
1da177e4 | 70 | |
d0035c62 | 71 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 72 | tcep++; |
1da177e4 LT |
73 | } |
74 | } | |
75 | ||
76 | ||
77 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
78 | { | |
bc97ce95 | 79 | u64 *tcep; |
1da177e4 | 80 | |
bc97ce95 OJ |
81 | tcep = ((u64 *)tbl->it_base) + index; |
82 | ||
83 | while (npages--) | |
84 | *(tcep++) = 0; | |
1da177e4 LT |
85 | } |
86 | ||
5f50867b HM |
87 | static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) |
88 | { | |
89 | u64 *tcep; | |
90 | ||
5f50867b HM |
91 | tcep = ((u64 *)tbl->it_base) + index; |
92 | ||
93 | return *tcep; | |
94 | } | |
1da177e4 LT |
95 | |
96 | static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
97 | long npages, unsigned long uaddr, | |
98 | enum dma_data_direction direction) | |
99 | { | |
100 | u64 rc; | |
bc97ce95 OJ |
101 | u64 proto_tce, tce; |
102 | u64 rpn; | |
1da177e4 | 103 | |
bc97ce95 OJ |
104 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
105 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 106 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 107 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
108 | |
109 | while (npages--) { | |
bc97ce95 OJ |
110 | tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
111 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); | |
112 | ||
1da177e4 LT |
113 | if (rc && printk_ratelimit()) { |
114 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
115 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
116 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
bc97ce95 | 117 | printk("\ttce val = 0x%lx\n", tce ); |
1da177e4 LT |
118 | show_stack(current, (unsigned long *)__get_SP()); |
119 | } | |
bc97ce95 | 120 | |
1da177e4 | 121 | tcenum++; |
bc97ce95 | 122 | rpn++; |
1da177e4 LT |
123 | } |
124 | } | |
125 | ||
bc97ce95 | 126 | static DEFINE_PER_CPU(u64 *, tce_page) = NULL; |
1da177e4 LT |
127 | |
128 | static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
129 | long npages, unsigned long uaddr, | |
130 | enum dma_data_direction direction) | |
131 | { | |
132 | u64 rc; | |
bc97ce95 OJ |
133 | u64 proto_tce; |
134 | u64 *tcep; | |
135 | u64 rpn; | |
1da177e4 LT |
136 | long l, limit; |
137 | ||
5d2efba6 | 138 | if (npages == 1) |
1da177e4 LT |
139 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
140 | direction); | |
141 | ||
142 | tcep = __get_cpu_var(tce_page); | |
143 | ||
144 | /* This is safe to do since interrupts are off when we're called | |
145 | * from iommu_alloc{,_sg}() | |
146 | */ | |
147 | if (!tcep) { | |
bc97ce95 | 148 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 LT |
149 | /* If allocation fails, fall back to the loop implementation */ |
150 | if (!tcep) | |
151 | return tce_build_pSeriesLP(tbl, tcenum, npages, | |
152 | uaddr, direction); | |
153 | __get_cpu_var(tce_page) = tcep; | |
154 | } | |
155 | ||
bc97ce95 OJ |
156 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
157 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 158 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 159 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
160 | |
161 | /* We can map max one pageful of TCEs at a time */ | |
162 | do { | |
163 | /* | |
164 | * Set up the page with TCE data, looping through and setting | |
165 | * the values. | |
166 | */ | |
bc97ce95 | 167 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
168 | |
169 | for (l = 0; l < limit; l++) { | |
bc97ce95 OJ |
170 | tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
171 | rpn++; | |
1da177e4 LT |
172 | } |
173 | ||
174 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
175 | (u64)tcenum << 12, | |
176 | (u64)virt_to_abs(tcep), | |
177 | limit); | |
178 | ||
179 | npages -= limit; | |
180 | tcenum += limit; | |
181 | } while (npages > 0 && !rc); | |
182 | ||
183 | if (rc && printk_ratelimit()) { | |
184 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
185 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
186 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
bc97ce95 | 187 | printk("\ttce[0] val = 0x%lx\n", tcep[0]); |
1da177e4 LT |
188 | show_stack(current, (unsigned long *)__get_SP()); |
189 | } | |
190 | } | |
191 | ||
192 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
193 | { | |
194 | u64 rc; | |
1da177e4 | 195 | |
1da177e4 | 196 | while (npages--) { |
bc97ce95 | 197 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); |
1da177e4 LT |
198 | |
199 | if (rc && printk_ratelimit()) { | |
200 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
201 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
202 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
1da177e4 LT |
203 | show_stack(current, (unsigned long *)__get_SP()); |
204 | } | |
205 | ||
206 | tcenum++; | |
207 | } | |
208 | } | |
209 | ||
210 | ||
211 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
212 | { | |
213 | u64 rc; | |
1da177e4 | 214 | |
bc97ce95 | 215 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
216 | |
217 | if (rc && printk_ratelimit()) { | |
218 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
219 | printk("\trc = %ld\n", rc); | |
220 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
221 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
1da177e4 LT |
222 | show_stack(current, (unsigned long *)__get_SP()); |
223 | } | |
224 | } | |
225 | ||
5f50867b HM |
226 | static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) |
227 | { | |
228 | u64 rc; | |
229 | unsigned long tce_ret; | |
230 | ||
5f50867b HM |
231 | rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); |
232 | ||
233 | if (rc && printk_ratelimit()) { | |
234 | printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n", | |
235 | rc); | |
236 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
237 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
238 | show_stack(current, (unsigned long *)__get_SP()); | |
239 | } | |
240 | ||
241 | return tce_ret; | |
242 | } | |
243 | ||
bed59275 | 244 | #ifdef CONFIG_PCI |
1da177e4 LT |
245 | static void iommu_table_setparms(struct pci_controller *phb, |
246 | struct device_node *dn, | |
bc97ce95 | 247 | struct iommu_table *tbl) |
1da177e4 LT |
248 | { |
249 | struct device_node *node; | |
9938c474 NL |
250 | const unsigned long *basep; |
251 | const u32 *sizep; | |
1da177e4 | 252 | |
44ef3390 | 253 | node = phb->dn; |
1da177e4 | 254 | |
e2eb6392 SR |
255 | basep = of_get_property(node, "linux,tce-base", NULL); |
256 | sizep = of_get_property(node, "linux,tce-size", NULL); | |
1da177e4 LT |
257 | if (basep == NULL || sizep == NULL) { |
258 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
259 | "missing tce entries !\n", dn->full_name); | |
260 | return; | |
261 | } | |
262 | ||
263 | tbl->it_base = (unsigned long)__va(*basep); | |
5f50867b HM |
264 | |
265 | #ifndef CONFIG_CRASH_DUMP | |
1da177e4 | 266 | memset((void *)tbl->it_base, 0, *sizep); |
5f50867b | 267 | #endif |
1da177e4 LT |
268 | |
269 | tbl->it_busno = phb->bus->number; | |
bc97ce95 | 270 | |
1da177e4 | 271 | /* Units of tce entries */ |
5d2efba6 | 272 | tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; |
bc97ce95 | 273 | |
1da177e4 | 274 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
275 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
276 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 277 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 278 | } |
bc97ce95 | 279 | |
1da177e4 LT |
280 | phb->dma_window_base_cur += phb->dma_window_size; |
281 | ||
282 | /* Set the tce table size - measured in entries */ | |
5d2efba6 | 283 | tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; |
1da177e4 LT |
284 | |
285 | tbl->it_index = 0; | |
286 | tbl->it_blocksize = 16; | |
287 | tbl->it_type = TCE_PCI; | |
288 | } | |
289 | ||
290 | /* | |
291 | * iommu_table_setparms_lpar | |
292 | * | |
293 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
294 | */ |
295 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
296 | struct device_node *dn, | |
297 | struct iommu_table *tbl, | |
96188ce5 SR |
298 | const void *dma_window, |
299 | int bussubno) | |
1da177e4 | 300 | { |
4c76e0bc JK |
301 | unsigned long offset, size; |
302 | ||
96188ce5 | 303 | tbl->it_busno = bussubno; |
4c76e0bc | 304 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 305 | |
1da177e4 | 306 | tbl->it_base = 0; |
1da177e4 LT |
307 | tbl->it_blocksize = 16; |
308 | tbl->it_type = TCE_PCI; | |
5d2efba6 LV |
309 | tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; |
310 | tbl->it_size = size >> IOMMU_PAGE_SHIFT; | |
1da177e4 LT |
311 | } |
312 | ||
12d04eef | 313 | static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) |
1da177e4 | 314 | { |
3c2822cc | 315 | struct device_node *dn; |
1da177e4 | 316 | struct iommu_table *tbl; |
3c2822cc OJ |
317 | struct device_node *isa_dn, *isa_dn_orig; |
318 | struct device_node *tmp; | |
319 | struct pci_dn *pci; | |
320 | int children; | |
1da177e4 | 321 | |
3c2822cc | 322 | dn = pci_bus_to_OF_node(bus); |
12d04eef | 323 | |
f7ebf352 | 324 | pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); |
3c2822cc OJ |
325 | |
326 | if (bus->self) { | |
327 | /* This is not a root bus, any setup will be done for the | |
328 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
329 | */ | |
330 | return; | |
331 | } | |
12d04eef | 332 | pci = PCI_DN(dn); |
3c2822cc OJ |
333 | |
334 | /* Check if the ISA bus on the system is under | |
335 | * this PHB. | |
1da177e4 | 336 | */ |
3c2822cc | 337 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 338 | |
3c2822cc OJ |
339 | while (isa_dn && isa_dn != dn) |
340 | isa_dn = isa_dn->parent; | |
341 | ||
342 | if (isa_dn_orig) | |
343 | of_node_put(isa_dn_orig); | |
1da177e4 | 344 | |
d3c58fb1 | 345 | /* Count number of direct PCI children of the PHB. */ |
3c2822cc | 346 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) |
d3c58fb1 | 347 | children++; |
1da177e4 | 348 | |
f7ebf352 | 349 | pr_debug("Children: %d\n", children); |
1da177e4 | 350 | |
3c2822cc OJ |
351 | /* Calculate amount of DMA window per slot. Each window must be |
352 | * a power of two (due to pci_alloc_consistent requirements). | |
353 | * | |
354 | * Keep 256MB aside for PHBs with ISA. | |
355 | */ | |
1da177e4 | 356 | |
3c2822cc OJ |
357 | if (!isa_dn) { |
358 | /* No ISA/IDE - just set window size and return */ | |
359 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
360 | ||
361 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
362 | pci->phb->dma_window_size >>= 1; | |
f7ebf352 ME |
363 | pr_debug("No ISA/IDE, window size is 0x%lx\n", |
364 | pci->phb->dma_window_size); | |
3c2822cc OJ |
365 | pci->phb->dma_window_base_cur = 0; |
366 | ||
367 | return; | |
1da177e4 | 368 | } |
3c2822cc OJ |
369 | |
370 | /* If we have ISA, then we probably have an IDE | |
371 | * controller too. Allocate a 128MB table but | |
372 | * skip the first 128MB to avoid stepping on ISA | |
373 | * space. | |
374 | */ | |
375 | pci->phb->dma_window_size = 0x8000000ul; | |
376 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
377 | ||
ca1588e7 AB |
378 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
379 | pci->phb->node); | |
3c2822cc OJ |
380 | |
381 | iommu_table_setparms(pci->phb, dn, tbl); | |
ca1588e7 | 382 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
3c2822cc OJ |
383 | |
384 | /* Divide the rest (1.75GB) among the children */ | |
385 | pci->phb->dma_window_size = 0x80000000ul; | |
386 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
387 | pci->phb->dma_window_size >>= 1; | |
388 | ||
f7ebf352 | 389 | pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); |
1da177e4 LT |
390 | } |
391 | ||
392 | ||
12d04eef | 393 | static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) |
1da177e4 LT |
394 | { |
395 | struct iommu_table *tbl; | |
396 | struct device_node *dn, *pdn; | |
1635317f | 397 | struct pci_dn *ppci; |
954a46e2 | 398 | const void *dma_window = NULL; |
1da177e4 | 399 | |
1da177e4 LT |
400 | dn = pci_bus_to_OF_node(bus); |
401 | ||
f7ebf352 ME |
402 | pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", |
403 | dn->full_name); | |
12d04eef | 404 | |
1da177e4 LT |
405 | /* Find nearest ibm,dma-window, walking up the device tree */ |
406 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
e2eb6392 | 407 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
408 | if (dma_window != NULL) |
409 | break; | |
410 | } | |
411 | ||
412 | if (dma_window == NULL) { | |
f7ebf352 | 413 | pr_debug(" no ibm,dma-window property !\n"); |
1da177e4 LT |
414 | return; |
415 | } | |
416 | ||
e07102db | 417 | ppci = PCI_DN(pdn); |
12d04eef | 418 | |
f7ebf352 ME |
419 | pr_debug(" parent is %s, iommu_table: 0x%p\n", |
420 | pdn->full_name, ppci->iommu_table); | |
12d04eef | 421 | |
1635317f | 422 | if (!ppci->iommu_table) { |
ca1588e7 AB |
423 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
424 | ppci->phb->node); | |
96188ce5 SR |
425 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, |
426 | bus->number); | |
ca1588e7 | 427 | ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); |
f7ebf352 | 428 | pr_debug(" created table: %p\n", ppci->iommu_table); |
1da177e4 LT |
429 | } |
430 | ||
431 | if (pdn != dn) | |
1635317f | 432 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
433 | } |
434 | ||
435 | ||
12d04eef | 436 | static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) |
1da177e4 | 437 | { |
12d04eef | 438 | struct device_node *dn; |
3c2822cc | 439 | struct iommu_table *tbl; |
1da177e4 | 440 | |
f7ebf352 | 441 | pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); |
1da177e4 | 442 | |
12d04eef | 443 | dn = dev->dev.archdata.of_node; |
1da177e4 | 444 | |
3c2822cc OJ |
445 | /* If we're the direct child of a root bus, then we need to allocate |
446 | * an iommu table ourselves. The bus setup code should have setup | |
447 | * the window sizes already. | |
448 | */ | |
449 | if (!dev->bus->self) { | |
12d04eef BH |
450 | struct pci_controller *phb = PCI_DN(dn)->phb; |
451 | ||
f7ebf352 | 452 | pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); |
ca1588e7 | 453 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
12d04eef BH |
454 | phb->node); |
455 | iommu_table_setparms(phb, dn, tbl); | |
77319254 LV |
456 | PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); |
457 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
3c2822cc OJ |
458 | return; |
459 | } | |
460 | ||
461 | /* If this device is further down the bus tree, search upwards until | |
462 | * an already allocated iommu table is found and use that. | |
463 | */ | |
464 | ||
e07102db | 465 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
466 | dn = dn->parent; |
467 | ||
12d04eef BH |
468 | if (dn && PCI_DN(dn)) |
469 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
470 | else | |
471 | printk(KERN_WARNING "iommu: Device %s has no iommu table\n", | |
472 | pci_name(dev)); | |
1da177e4 LT |
473 | } |
474 | ||
12d04eef | 475 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
1da177e4 LT |
476 | { |
477 | struct device_node *pdn, *dn; | |
478 | struct iommu_table *tbl; | |
954a46e2 | 479 | const void *dma_window = NULL; |
1635317f | 480 | struct pci_dn *pci; |
1da177e4 | 481 | |
f7ebf352 | 482 | pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); |
12d04eef | 483 | |
1da177e4 LT |
484 | /* dev setup for LPAR is a little tricky, since the device tree might |
485 | * contain the dma-window properties per-device and not neccesarily | |
486 | * for the bus. So we need to search upwards in the tree until we | |
487 | * either hit a dma-window property, OR find a parent with a table | |
488 | * already allocated. | |
489 | */ | |
490 | dn = pci_device_to_OF_node(dev); | |
f7ebf352 | 491 | pr_debug(" node is %s\n", dn->full_name); |
5d2efba6 | 492 | |
e07102db | 493 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f | 494 | pdn = pdn->parent) { |
e2eb6392 | 495 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
496 | if (dma_window) |
497 | break; | |
498 | } | |
499 | ||
650f7b3b LV |
500 | if (!pdn || !PCI_DN(pdn)) { |
501 | printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " | |
502 | "no DMA window found for pci dev=%s dn=%s\n", | |
503 | pci_name(dev), dn? dn->full_name : "<null>"); | |
504 | return; | |
505 | } | |
f7ebf352 | 506 | pr_debug(" parent is %s\n", pdn->full_name); |
12d04eef | 507 | |
1da177e4 LT |
508 | /* Check for parent == NULL so we don't try to setup the empty EADS |
509 | * slots on POWER4 machines. | |
510 | */ | |
511 | if (dma_window == NULL || pdn->parent == NULL) { | |
f7ebf352 | 512 | pr_debug(" no dma window for device, linking to parent\n"); |
12d04eef | 513 | dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; |
1da177e4 | 514 | return; |
1da177e4 LT |
515 | } |
516 | ||
e07102db | 517 | pci = PCI_DN(pdn); |
1635317f | 518 | if (!pci->iommu_table) { |
ca1588e7 AB |
519 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
520 | pci->phb->node); | |
96188ce5 SR |
521 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, |
522 | pci->phb->bus->number); | |
ca1588e7 | 523 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
f7ebf352 | 524 | pr_debug(" created table: %p\n", pci->iommu_table); |
de113217 | 525 | } else { |
f7ebf352 | 526 | pr_debug(" found DMA window, table: %p\n", pci->iommu_table); |
1da177e4 LT |
527 | } |
528 | ||
12d04eef | 529 | dev->dev.archdata.dma_data = pci->iommu_table; |
1da177e4 | 530 | } |
bed59275 SR |
531 | #else /* CONFIG_PCI */ |
532 | #define pci_dma_bus_setup_pSeries NULL | |
533 | #define pci_dma_dev_setup_pSeries NULL | |
534 | #define pci_dma_bus_setup_pSeriesLP NULL | |
535 | #define pci_dma_dev_setup_pSeriesLP NULL | |
536 | #endif /* !CONFIG_PCI */ | |
537 | ||
538 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
539 | { | |
540 | int err = NOTIFY_OK; | |
541 | struct device_node *np = node; | |
542 | struct pci_dn *pci = PCI_DN(np); | |
543 | ||
544 | switch (action) { | |
545 | case PSERIES_RECONFIG_REMOVE: | |
546 | if (pci && pci->iommu_table && | |
e2eb6392 | 547 | of_get_property(np, "ibm,dma-window", NULL)) |
68d315f5 | 548 | iommu_free_table(pci->iommu_table, np->full_name); |
bed59275 SR |
549 | break; |
550 | default: | |
551 | err = NOTIFY_DONE; | |
552 | break; | |
553 | } | |
554 | return err; | |
555 | } | |
556 | ||
557 | static struct notifier_block iommu_reconfig_nb = { | |
558 | .notifier_call = iommu_reconfig_notifier, | |
559 | }; | |
1da177e4 | 560 | |
1da177e4 LT |
561 | /* These are called very early. */ |
562 | void iommu_init_early_pSeries(void) | |
563 | { | |
e2eb6392 | 564 | if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { |
1da177e4 | 565 | /* Direct I/O, IOMMU off */ |
12d04eef BH |
566 | ppc_md.pci_dma_dev_setup = NULL; |
567 | ppc_md.pci_dma_bus_setup = NULL; | |
98747770 | 568 | set_pci_dma_ops(&dma_direct_ops); |
1da177e4 LT |
569 | return; |
570 | } | |
571 | ||
57cfb814 | 572 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 573 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
574 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
575 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
576 | } else { | |
577 | ppc_md.tce_build = tce_build_pSeriesLP; | |
578 | ppc_md.tce_free = tce_free_pSeriesLP; | |
579 | } | |
5f50867b | 580 | ppc_md.tce_get = tce_get_pSeriesLP; |
12d04eef BH |
581 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
582 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | |
1da177e4 LT |
583 | } else { |
584 | ppc_md.tce_build = tce_build_pSeries; | |
585 | ppc_md.tce_free = tce_free_pSeries; | |
5f50867b | 586 | ppc_md.tce_get = tce_get_pseries; |
12d04eef BH |
587 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; |
588 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; | |
1da177e4 LT |
589 | } |
590 | ||
591 | ||
592 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
593 | ||
98747770 | 594 | set_pci_dma_ops(&dma_iommu_ops); |
1da177e4 LT |
595 | } |
596 |