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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <asm/io.h> | |
36 | #include <asm/prom.h> | |
37 | #include <asm/rtas.h> | |
1da177e4 LT |
38 | #include <asm/iommu.h> |
39 | #include <asm/pci-bridge.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/abs_addr.h> | |
1da177e4 | 42 | #include <asm/pSeries_reconfig.h> |
1ababe11 | 43 | #include <asm/firmware.h> |
c707ffcf | 44 | #include <asm/tce.h> |
d387899f | 45 | #include <asm/ppc-pci.h> |
2249ca9d | 46 | #include <asm/udbg.h> |
1da177e4 | 47 | |
a1218720 ME |
48 | #include "plpar_wrappers.h" |
49 | ||
1da177e4 | 50 | |
6490c490 | 51 | static int tce_build_pSeries(struct iommu_table *tbl, long index, |
bc97ce95 | 52 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
53 | enum dma_data_direction direction, |
54 | struct dma_attrs *attrs) | |
1da177e4 | 55 | { |
bc97ce95 OJ |
56 | u64 proto_tce; |
57 | u64 *tcep; | |
58 | u64 rpn; | |
1da177e4 | 59 | |
bc97ce95 | 60 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
61 | |
62 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 63 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 64 | |
bc97ce95 | 65 | tcep = ((u64 *)tbl->it_base) + index; |
1da177e4 LT |
66 | |
67 | while (npages--) { | |
68 | /* can't move this out since we might cross LMB boundary */ | |
bc97ce95 OJ |
69 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
70 | *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; | |
1da177e4 | 71 | |
d0035c62 | 72 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 73 | tcep++; |
1da177e4 | 74 | } |
6490c490 | 75 | return 0; |
1da177e4 LT |
76 | } |
77 | ||
78 | ||
79 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
80 | { | |
bc97ce95 | 81 | u64 *tcep; |
1da177e4 | 82 | |
bc97ce95 OJ |
83 | tcep = ((u64 *)tbl->it_base) + index; |
84 | ||
85 | while (npages--) | |
86 | *(tcep++) = 0; | |
1da177e4 LT |
87 | } |
88 | ||
5f50867b HM |
89 | static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) |
90 | { | |
91 | u64 *tcep; | |
92 | ||
5f50867b HM |
93 | tcep = ((u64 *)tbl->it_base) + index; |
94 | ||
95 | return *tcep; | |
96 | } | |
1da177e4 | 97 | |
6490c490 RJ |
98 | static void tce_free_pSeriesLP(struct iommu_table*, long, long); |
99 | static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); | |
100 | ||
101 | static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
1da177e4 | 102 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
103 | enum dma_data_direction direction, |
104 | struct dma_attrs *attrs) | |
1da177e4 | 105 | { |
6490c490 | 106 | u64 rc = 0; |
bc97ce95 OJ |
107 | u64 proto_tce, tce; |
108 | u64 rpn; | |
6490c490 RJ |
109 | int ret = 0; |
110 | long tcenum_start = tcenum, npages_start = npages; | |
1da177e4 | 111 | |
bc97ce95 OJ |
112 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
113 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 114 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 115 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
116 | |
117 | while (npages--) { | |
bc97ce95 OJ |
118 | tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
119 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); | |
120 | ||
6490c490 RJ |
121 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
122 | ret = (int)rc; | |
123 | tce_free_pSeriesLP(tbl, tcenum_start, | |
124 | (npages_start - (npages + 1))); | |
125 | break; | |
126 | } | |
127 | ||
1da177e4 LT |
128 | if (rc && printk_ratelimit()) { |
129 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
130 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
131 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
bc97ce95 | 132 | printk("\ttce val = 0x%lx\n", tce ); |
1da177e4 LT |
133 | show_stack(current, (unsigned long *)__get_SP()); |
134 | } | |
bc97ce95 | 135 | |
1da177e4 | 136 | tcenum++; |
bc97ce95 | 137 | rpn++; |
1da177e4 | 138 | } |
6490c490 | 139 | return ret; |
1da177e4 LT |
140 | } |
141 | ||
bc97ce95 | 142 | static DEFINE_PER_CPU(u64 *, tce_page) = NULL; |
1da177e4 | 143 | |
6490c490 | 144 | static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, |
1da177e4 | 145 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
146 | enum dma_data_direction direction, |
147 | struct dma_attrs *attrs) | |
1da177e4 | 148 | { |
6490c490 | 149 | u64 rc = 0; |
bc97ce95 OJ |
150 | u64 proto_tce; |
151 | u64 *tcep; | |
152 | u64 rpn; | |
1da177e4 | 153 | long l, limit; |
6490c490 RJ |
154 | long tcenum_start = tcenum, npages_start = npages; |
155 | int ret = 0; | |
1da177e4 | 156 | |
541b2755 | 157 | if (npages == 1) { |
6490c490 RJ |
158 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
159 | direction, attrs); | |
541b2755 | 160 | } |
1da177e4 LT |
161 | |
162 | tcep = __get_cpu_var(tce_page); | |
163 | ||
164 | /* This is safe to do since interrupts are off when we're called | |
165 | * from iommu_alloc{,_sg}() | |
166 | */ | |
167 | if (!tcep) { | |
bc97ce95 | 168 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 | 169 | /* If allocation fails, fall back to the loop implementation */ |
541b2755 | 170 | if (!tcep) { |
6490c490 | 171 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
4f3dd8a0 | 172 | direction, attrs); |
541b2755 | 173 | } |
1da177e4 LT |
174 | __get_cpu_var(tce_page) = tcep; |
175 | } | |
176 | ||
bc97ce95 OJ |
177 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
178 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 179 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 180 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
181 | |
182 | /* We can map max one pageful of TCEs at a time */ | |
183 | do { | |
184 | /* | |
185 | * Set up the page with TCE data, looping through and setting | |
186 | * the values. | |
187 | */ | |
bc97ce95 | 188 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
189 | |
190 | for (l = 0; l < limit; l++) { | |
bc97ce95 OJ |
191 | tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
192 | rpn++; | |
1da177e4 LT |
193 | } |
194 | ||
195 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
196 | (u64)tcenum << 12, | |
197 | (u64)virt_to_abs(tcep), | |
198 | limit); | |
199 | ||
200 | npages -= limit; | |
201 | tcenum += limit; | |
202 | } while (npages > 0 && !rc); | |
203 | ||
6490c490 RJ |
204 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
205 | ret = (int)rc; | |
206 | tce_freemulti_pSeriesLP(tbl, tcenum_start, | |
207 | (npages_start - (npages + limit))); | |
208 | return ret; | |
209 | } | |
210 | ||
1da177e4 LT |
211 | if (rc && printk_ratelimit()) { |
212 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
213 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
214 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
bc97ce95 | 215 | printk("\ttce[0] val = 0x%lx\n", tcep[0]); |
1da177e4 LT |
216 | show_stack(current, (unsigned long *)__get_SP()); |
217 | } | |
6490c490 | 218 | return ret; |
1da177e4 LT |
219 | } |
220 | ||
221 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
222 | { | |
223 | u64 rc; | |
1da177e4 | 224 | |
1da177e4 | 225 | while (npages--) { |
bc97ce95 | 226 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); |
1da177e4 LT |
227 | |
228 | if (rc && printk_ratelimit()) { | |
229 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
230 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
231 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
1da177e4 LT |
232 | show_stack(current, (unsigned long *)__get_SP()); |
233 | } | |
234 | ||
235 | tcenum++; | |
236 | } | |
237 | } | |
238 | ||
239 | ||
240 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
241 | { | |
242 | u64 rc; | |
1da177e4 | 243 | |
bc97ce95 | 244 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
245 | |
246 | if (rc && printk_ratelimit()) { | |
247 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
248 | printk("\trc = %ld\n", rc); | |
249 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
250 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
1da177e4 LT |
251 | show_stack(current, (unsigned long *)__get_SP()); |
252 | } | |
253 | } | |
254 | ||
5f50867b HM |
255 | static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) |
256 | { | |
257 | u64 rc; | |
258 | unsigned long tce_ret; | |
259 | ||
5f50867b HM |
260 | rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); |
261 | ||
262 | if (rc && printk_ratelimit()) { | |
263 | printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n", | |
264 | rc); | |
265 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
266 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
267 | show_stack(current, (unsigned long *)__get_SP()); | |
268 | } | |
269 | ||
270 | return tce_ret; | |
271 | } | |
272 | ||
bed59275 | 273 | #ifdef CONFIG_PCI |
1da177e4 LT |
274 | static void iommu_table_setparms(struct pci_controller *phb, |
275 | struct device_node *dn, | |
bc97ce95 | 276 | struct iommu_table *tbl) |
1da177e4 LT |
277 | { |
278 | struct device_node *node; | |
9938c474 NL |
279 | const unsigned long *basep; |
280 | const u32 *sizep; | |
1da177e4 | 281 | |
44ef3390 | 282 | node = phb->dn; |
1da177e4 | 283 | |
e2eb6392 SR |
284 | basep = of_get_property(node, "linux,tce-base", NULL); |
285 | sizep = of_get_property(node, "linux,tce-size", NULL); | |
1da177e4 LT |
286 | if (basep == NULL || sizep == NULL) { |
287 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
288 | "missing tce entries !\n", dn->full_name); | |
289 | return; | |
290 | } | |
291 | ||
292 | tbl->it_base = (unsigned long)__va(*basep); | |
5f50867b HM |
293 | |
294 | #ifndef CONFIG_CRASH_DUMP | |
1da177e4 | 295 | memset((void *)tbl->it_base, 0, *sizep); |
5f50867b | 296 | #endif |
1da177e4 LT |
297 | |
298 | tbl->it_busno = phb->bus->number; | |
bc97ce95 | 299 | |
1da177e4 | 300 | /* Units of tce entries */ |
5d2efba6 | 301 | tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; |
bc97ce95 | 302 | |
1da177e4 | 303 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
304 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
305 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 306 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 307 | } |
bc97ce95 | 308 | |
1da177e4 LT |
309 | phb->dma_window_base_cur += phb->dma_window_size; |
310 | ||
311 | /* Set the tce table size - measured in entries */ | |
5d2efba6 | 312 | tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; |
1da177e4 LT |
313 | |
314 | tbl->it_index = 0; | |
315 | tbl->it_blocksize = 16; | |
316 | tbl->it_type = TCE_PCI; | |
317 | } | |
318 | ||
319 | /* | |
320 | * iommu_table_setparms_lpar | |
321 | * | |
322 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
323 | */ |
324 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
325 | struct device_node *dn, | |
326 | struct iommu_table *tbl, | |
96188ce5 SR |
327 | const void *dma_window, |
328 | int bussubno) | |
1da177e4 | 329 | { |
4c76e0bc JK |
330 | unsigned long offset, size; |
331 | ||
96188ce5 | 332 | tbl->it_busno = bussubno; |
4c76e0bc | 333 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 334 | |
1da177e4 | 335 | tbl->it_base = 0; |
1da177e4 LT |
336 | tbl->it_blocksize = 16; |
337 | tbl->it_type = TCE_PCI; | |
5d2efba6 LV |
338 | tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; |
339 | tbl->it_size = size >> IOMMU_PAGE_SHIFT; | |
1da177e4 LT |
340 | } |
341 | ||
12d04eef | 342 | static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) |
1da177e4 | 343 | { |
3c2822cc | 344 | struct device_node *dn; |
1da177e4 | 345 | struct iommu_table *tbl; |
3c2822cc OJ |
346 | struct device_node *isa_dn, *isa_dn_orig; |
347 | struct device_node *tmp; | |
348 | struct pci_dn *pci; | |
349 | int children; | |
1da177e4 | 350 | |
3c2822cc | 351 | dn = pci_bus_to_OF_node(bus); |
12d04eef | 352 | |
f7ebf352 | 353 | pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); |
3c2822cc OJ |
354 | |
355 | if (bus->self) { | |
356 | /* This is not a root bus, any setup will be done for the | |
357 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
358 | */ | |
359 | return; | |
360 | } | |
12d04eef | 361 | pci = PCI_DN(dn); |
3c2822cc OJ |
362 | |
363 | /* Check if the ISA bus on the system is under | |
364 | * this PHB. | |
1da177e4 | 365 | */ |
3c2822cc | 366 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 367 | |
3c2822cc OJ |
368 | while (isa_dn && isa_dn != dn) |
369 | isa_dn = isa_dn->parent; | |
370 | ||
371 | if (isa_dn_orig) | |
372 | of_node_put(isa_dn_orig); | |
1da177e4 | 373 | |
d3c58fb1 | 374 | /* Count number of direct PCI children of the PHB. */ |
3c2822cc | 375 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) |
d3c58fb1 | 376 | children++; |
1da177e4 | 377 | |
f7ebf352 | 378 | pr_debug("Children: %d\n", children); |
1da177e4 | 379 | |
3c2822cc OJ |
380 | /* Calculate amount of DMA window per slot. Each window must be |
381 | * a power of two (due to pci_alloc_consistent requirements). | |
382 | * | |
383 | * Keep 256MB aside for PHBs with ISA. | |
384 | */ | |
1da177e4 | 385 | |
3c2822cc OJ |
386 | if (!isa_dn) { |
387 | /* No ISA/IDE - just set window size and return */ | |
388 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
389 | ||
390 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
391 | pci->phb->dma_window_size >>= 1; | |
f7ebf352 ME |
392 | pr_debug("No ISA/IDE, window size is 0x%lx\n", |
393 | pci->phb->dma_window_size); | |
3c2822cc OJ |
394 | pci->phb->dma_window_base_cur = 0; |
395 | ||
396 | return; | |
1da177e4 | 397 | } |
3c2822cc OJ |
398 | |
399 | /* If we have ISA, then we probably have an IDE | |
400 | * controller too. Allocate a 128MB table but | |
401 | * skip the first 128MB to avoid stepping on ISA | |
402 | * space. | |
403 | */ | |
404 | pci->phb->dma_window_size = 0x8000000ul; | |
405 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
406 | ||
ca1588e7 AB |
407 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
408 | pci->phb->node); | |
3c2822cc OJ |
409 | |
410 | iommu_table_setparms(pci->phb, dn, tbl); | |
ca1588e7 | 411 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
3c2822cc OJ |
412 | |
413 | /* Divide the rest (1.75GB) among the children */ | |
414 | pci->phb->dma_window_size = 0x80000000ul; | |
415 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
416 | pci->phb->dma_window_size >>= 1; | |
417 | ||
f7ebf352 | 418 | pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); |
1da177e4 LT |
419 | } |
420 | ||
421 | ||
12d04eef | 422 | static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) |
1da177e4 LT |
423 | { |
424 | struct iommu_table *tbl; | |
425 | struct device_node *dn, *pdn; | |
1635317f | 426 | struct pci_dn *ppci; |
954a46e2 | 427 | const void *dma_window = NULL; |
1da177e4 | 428 | |
1da177e4 LT |
429 | dn = pci_bus_to_OF_node(bus); |
430 | ||
f7ebf352 ME |
431 | pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", |
432 | dn->full_name); | |
12d04eef | 433 | |
1da177e4 LT |
434 | /* Find nearest ibm,dma-window, walking up the device tree */ |
435 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
e2eb6392 | 436 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
437 | if (dma_window != NULL) |
438 | break; | |
439 | } | |
440 | ||
441 | if (dma_window == NULL) { | |
f7ebf352 | 442 | pr_debug(" no ibm,dma-window property !\n"); |
1da177e4 LT |
443 | return; |
444 | } | |
445 | ||
e07102db | 446 | ppci = PCI_DN(pdn); |
12d04eef | 447 | |
f7ebf352 ME |
448 | pr_debug(" parent is %s, iommu_table: 0x%p\n", |
449 | pdn->full_name, ppci->iommu_table); | |
12d04eef | 450 | |
1635317f | 451 | if (!ppci->iommu_table) { |
ca1588e7 AB |
452 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
453 | ppci->phb->node); | |
96188ce5 SR |
454 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, |
455 | bus->number); | |
ca1588e7 | 456 | ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); |
f7ebf352 | 457 | pr_debug(" created table: %p\n", ppci->iommu_table); |
1da177e4 LT |
458 | } |
459 | ||
460 | if (pdn != dn) | |
1635317f | 461 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
462 | } |
463 | ||
464 | ||
12d04eef | 465 | static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) |
1da177e4 | 466 | { |
12d04eef | 467 | struct device_node *dn; |
3c2822cc | 468 | struct iommu_table *tbl; |
1da177e4 | 469 | |
f7ebf352 | 470 | pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); |
1da177e4 | 471 | |
12d04eef | 472 | dn = dev->dev.archdata.of_node; |
1da177e4 | 473 | |
3c2822cc OJ |
474 | /* If we're the direct child of a root bus, then we need to allocate |
475 | * an iommu table ourselves. The bus setup code should have setup | |
476 | * the window sizes already. | |
477 | */ | |
478 | if (!dev->bus->self) { | |
12d04eef BH |
479 | struct pci_controller *phb = PCI_DN(dn)->phb; |
480 | ||
f7ebf352 | 481 | pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); |
ca1588e7 | 482 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
12d04eef BH |
483 | phb->node); |
484 | iommu_table_setparms(phb, dn, tbl); | |
77319254 LV |
485 | PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); |
486 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
3c2822cc OJ |
487 | return; |
488 | } | |
489 | ||
490 | /* If this device is further down the bus tree, search upwards until | |
491 | * an already allocated iommu table is found and use that. | |
492 | */ | |
493 | ||
e07102db | 494 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
495 | dn = dn->parent; |
496 | ||
12d04eef BH |
497 | if (dn && PCI_DN(dn)) |
498 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
499 | else | |
500 | printk(KERN_WARNING "iommu: Device %s has no iommu table\n", | |
501 | pci_name(dev)); | |
1da177e4 LT |
502 | } |
503 | ||
12d04eef | 504 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
1da177e4 LT |
505 | { |
506 | struct device_node *pdn, *dn; | |
507 | struct iommu_table *tbl; | |
954a46e2 | 508 | const void *dma_window = NULL; |
1635317f | 509 | struct pci_dn *pci; |
1da177e4 | 510 | |
f7ebf352 | 511 | pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); |
12d04eef | 512 | |
1da177e4 LT |
513 | /* dev setup for LPAR is a little tricky, since the device tree might |
514 | * contain the dma-window properties per-device and not neccesarily | |
515 | * for the bus. So we need to search upwards in the tree until we | |
516 | * either hit a dma-window property, OR find a parent with a table | |
517 | * already allocated. | |
518 | */ | |
519 | dn = pci_device_to_OF_node(dev); | |
f7ebf352 | 520 | pr_debug(" node is %s\n", dn->full_name); |
5d2efba6 | 521 | |
e07102db | 522 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f | 523 | pdn = pdn->parent) { |
e2eb6392 | 524 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
525 | if (dma_window) |
526 | break; | |
527 | } | |
528 | ||
650f7b3b LV |
529 | if (!pdn || !PCI_DN(pdn)) { |
530 | printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " | |
531 | "no DMA window found for pci dev=%s dn=%s\n", | |
532 | pci_name(dev), dn? dn->full_name : "<null>"); | |
533 | return; | |
534 | } | |
f7ebf352 | 535 | pr_debug(" parent is %s\n", pdn->full_name); |
12d04eef | 536 | |
1da177e4 LT |
537 | /* Check for parent == NULL so we don't try to setup the empty EADS |
538 | * slots on POWER4 machines. | |
539 | */ | |
540 | if (dma_window == NULL || pdn->parent == NULL) { | |
f7ebf352 | 541 | pr_debug(" no dma window for device, linking to parent\n"); |
12d04eef | 542 | dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; |
1da177e4 | 543 | return; |
1da177e4 LT |
544 | } |
545 | ||
e07102db | 546 | pci = PCI_DN(pdn); |
1635317f | 547 | if (!pci->iommu_table) { |
ca1588e7 AB |
548 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
549 | pci->phb->node); | |
96188ce5 SR |
550 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, |
551 | pci->phb->bus->number); | |
ca1588e7 | 552 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
f7ebf352 | 553 | pr_debug(" created table: %p\n", pci->iommu_table); |
de113217 | 554 | } else { |
f7ebf352 | 555 | pr_debug(" found DMA window, table: %p\n", pci->iommu_table); |
1da177e4 LT |
556 | } |
557 | ||
12d04eef | 558 | dev->dev.archdata.dma_data = pci->iommu_table; |
1da177e4 | 559 | } |
bed59275 SR |
560 | #else /* CONFIG_PCI */ |
561 | #define pci_dma_bus_setup_pSeries NULL | |
562 | #define pci_dma_dev_setup_pSeries NULL | |
563 | #define pci_dma_bus_setup_pSeriesLP NULL | |
564 | #define pci_dma_dev_setup_pSeriesLP NULL | |
565 | #endif /* !CONFIG_PCI */ | |
566 | ||
567 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
568 | { | |
569 | int err = NOTIFY_OK; | |
570 | struct device_node *np = node; | |
571 | struct pci_dn *pci = PCI_DN(np); | |
572 | ||
573 | switch (action) { | |
574 | case PSERIES_RECONFIG_REMOVE: | |
575 | if (pci && pci->iommu_table && | |
e2eb6392 | 576 | of_get_property(np, "ibm,dma-window", NULL)) |
68d315f5 | 577 | iommu_free_table(pci->iommu_table, np->full_name); |
bed59275 SR |
578 | break; |
579 | default: | |
580 | err = NOTIFY_DONE; | |
581 | break; | |
582 | } | |
583 | return err; | |
584 | } | |
585 | ||
586 | static struct notifier_block iommu_reconfig_nb = { | |
587 | .notifier_call = iommu_reconfig_notifier, | |
588 | }; | |
1da177e4 | 589 | |
1da177e4 LT |
590 | /* These are called very early. */ |
591 | void iommu_init_early_pSeries(void) | |
592 | { | |
e2eb6392 | 593 | if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { |
1da177e4 | 594 | /* Direct I/O, IOMMU off */ |
12d04eef BH |
595 | ppc_md.pci_dma_dev_setup = NULL; |
596 | ppc_md.pci_dma_bus_setup = NULL; | |
98747770 | 597 | set_pci_dma_ops(&dma_direct_ops); |
1da177e4 LT |
598 | return; |
599 | } | |
600 | ||
57cfb814 | 601 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 602 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
603 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
604 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
605 | } else { | |
606 | ppc_md.tce_build = tce_build_pSeriesLP; | |
607 | ppc_md.tce_free = tce_free_pSeriesLP; | |
608 | } | |
5f50867b | 609 | ppc_md.tce_get = tce_get_pSeriesLP; |
12d04eef BH |
610 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
611 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | |
1da177e4 LT |
612 | } else { |
613 | ppc_md.tce_build = tce_build_pSeries; | |
614 | ppc_md.tce_free = tce_free_pSeries; | |
5f50867b | 615 | ppc_md.tce_get = tce_get_pseries; |
12d04eef BH |
616 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; |
617 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; | |
1da177e4 LT |
618 | } |
619 | ||
620 | ||
621 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
622 | ||
98747770 | 623 | set_pci_dma_ops(&dma_iommu_ops); |
1da177e4 LT |
624 | } |
625 |