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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
beacc6da | 31 | #include <linux/memblock.h> |
1da177e4 LT |
32 | #include <linux/spinlock.h> |
33 | #include <linux/string.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
62a8bd6c | 36 | #include <linux/crash_dump.h> |
4e8b0cf4 | 37 | #include <linux/memory.h> |
1cf3d8b3 | 38 | #include <linux/of.h> |
ac9a5889 | 39 | #include <linux/iommu.h> |
0eaf4def | 40 | #include <linux/rculist.h> |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/prom.h> | |
43 | #include <asm/rtas.h> | |
1da177e4 LT |
44 | #include <asm/iommu.h> |
45 | #include <asm/pci-bridge.h> | |
46 | #include <asm/machdep.h> | |
1ababe11 | 47 | #include <asm/firmware.h> |
c707ffcf | 48 | #include <asm/tce.h> |
d387899f | 49 | #include <asm/ppc-pci.h> |
2249ca9d | 50 | #include <asm/udbg.h> |
4e8b0cf4 | 51 | #include <asm/mmzone.h> |
212bebb4 | 52 | #include <asm/plpar_wrappers.h> |
a1218720 | 53 | |
38ae9ec4 | 54 | #include "pseries.h" |
1da177e4 | 55 | |
b348aa65 AK |
56 | static struct iommu_table_group *iommu_pseries_alloc_group(int node) |
57 | { | |
4dd9eab3 ME |
58 | struct iommu_table_group *table_group; |
59 | struct iommu_table *tbl; | |
60 | struct iommu_table_group_link *tgl; | |
b348aa65 AK |
61 | |
62 | table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL, | |
63 | node); | |
64 | if (!table_group) | |
4dd9eab3 | 65 | return NULL; |
b348aa65 AK |
66 | |
67 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node); | |
68 | if (!tbl) | |
4dd9eab3 | 69 | goto free_group; |
b348aa65 | 70 | |
0eaf4def AK |
71 | tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, |
72 | node); | |
73 | if (!tgl) | |
4dd9eab3 | 74 | goto free_table; |
0eaf4def AK |
75 | |
76 | INIT_LIST_HEAD_RCU(&tbl->it_group_list); | |
e5afdf9d | 77 | kref_init(&tbl->it_kref); |
0eaf4def AK |
78 | tgl->table_group = table_group; |
79 | list_add_rcu(&tgl->next, &tbl->it_group_list); | |
80 | ||
b348aa65 AK |
81 | table_group->tables[0] = tbl; |
82 | ||
83 | return table_group; | |
84 | ||
4dd9eab3 | 85 | free_table: |
b348aa65 | 86 | kfree(tbl); |
4dd9eab3 ME |
87 | free_group: |
88 | kfree(table_group); | |
b348aa65 AK |
89 | return NULL; |
90 | } | |
91 | ||
92 | static void iommu_pseries_free_group(struct iommu_table_group *table_group, | |
ac9a5889 AK |
93 | const char *node_name) |
94 | { | |
b348aa65 | 95 | struct iommu_table *tbl; |
0eaf4def AK |
96 | #ifdef CONFIG_IOMMU_API |
97 | struct iommu_table_group_link *tgl; | |
98 | #endif | |
b348aa65 AK |
99 | |
100 | if (!table_group) | |
101 | return; | |
102 | ||
0eaf4def | 103 | tbl = table_group->tables[0]; |
ac9a5889 | 104 | #ifdef CONFIG_IOMMU_API |
0eaf4def AK |
105 | tgl = list_first_entry_or_null(&tbl->it_group_list, |
106 | struct iommu_table_group_link, next); | |
107 | ||
108 | WARN_ON_ONCE(!tgl); | |
109 | if (tgl) { | |
110 | list_del_rcu(&tgl->next); | |
111 | kfree(tgl); | |
112 | } | |
b348aa65 AK |
113 | if (table_group->group) { |
114 | iommu_group_put(table_group->group); | |
115 | BUG_ON(table_group->group); | |
ac9a5889 AK |
116 | } |
117 | #endif | |
e5afdf9d | 118 | iommu_tce_table_put(tbl); |
b348aa65 AK |
119 | |
120 | kfree(table_group); | |
ac9a5889 AK |
121 | } |
122 | ||
6490c490 | 123 | static int tce_build_pSeries(struct iommu_table *tbl, long index, |
bc97ce95 | 124 | long npages, unsigned long uaddr, |
4f3dd8a0 | 125 | enum dma_data_direction direction, |
00085f1e | 126 | unsigned long attrs) |
1da177e4 | 127 | { |
bc97ce95 | 128 | u64 proto_tce; |
df015604 | 129 | __be64 *tcep, *tces; |
bc97ce95 | 130 | u64 rpn; |
1da177e4 | 131 | |
bc97ce95 | 132 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
133 | |
134 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 135 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 136 | |
df015604 | 137 | tces = tcep = ((__be64 *)tbl->it_base) + index; |
1da177e4 LT |
138 | |
139 | while (npages--) { | |
95f72d1e | 140 | /* can't move this out since we might cross MEMBLOCK boundary */ |
474e3d56 | 141 | rpn = __pa(uaddr) >> TCE_SHIFT; |
df015604 | 142 | *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT); |
1da177e4 | 143 | |
d0035c62 | 144 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 145 | tcep++; |
1da177e4 | 146 | } |
6490c490 | 147 | return 0; |
1da177e4 LT |
148 | } |
149 | ||
150 | ||
151 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
152 | { | |
df015604 | 153 | __be64 *tcep, *tces; |
1da177e4 | 154 | |
df015604 | 155 | tces = tcep = ((__be64 *)tbl->it_base) + index; |
bc97ce95 OJ |
156 | |
157 | while (npages--) | |
158 | *(tcep++) = 0; | |
1da177e4 LT |
159 | } |
160 | ||
5f50867b HM |
161 | static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) |
162 | { | |
df015604 | 163 | __be64 *tcep; |
5f50867b | 164 | |
df015604 | 165 | tcep = ((__be64 *)tbl->it_base) + index; |
5f50867b | 166 | |
df015604 | 167 | return be64_to_cpu(*tcep); |
5f50867b | 168 | } |
1da177e4 | 169 | |
b0788c64 | 170 | static void tce_free_pSeriesLP(unsigned long liobn, long, long); |
6490c490 RJ |
171 | static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); |
172 | ||
b0788c64 | 173 | static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift, |
1da177e4 | 174 | long npages, unsigned long uaddr, |
4f3dd8a0 | 175 | enum dma_data_direction direction, |
00085f1e | 176 | unsigned long attrs) |
1da177e4 | 177 | { |
6490c490 | 178 | u64 rc = 0; |
bc97ce95 OJ |
179 | u64 proto_tce, tce; |
180 | u64 rpn; | |
6490c490 RJ |
181 | int ret = 0; |
182 | long tcenum_start = tcenum, npages_start = npages; | |
1da177e4 | 183 | |
b0788c64 | 184 | rpn = __pa(uaddr) >> tceshift; |
bc97ce95 | 185 | proto_tce = TCE_PCI_READ; |
1da177e4 | 186 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 187 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
188 | |
189 | while (npages--) { | |
b0788c64 AK |
190 | tce = proto_tce | (rpn & TCE_RPN_MASK) << tceshift; |
191 | rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce); | |
bc97ce95 | 192 | |
6490c490 RJ |
193 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
194 | ret = (int)rc; | |
b0788c64 | 195 | tce_free_pSeriesLP(liobn, tcenum_start, |
6490c490 RJ |
196 | (npages_start - (npages + 1))); |
197 | break; | |
198 | } | |
199 | ||
1da177e4 | 200 | if (rc && printk_ratelimit()) { |
fe333321 | 201 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
b0788c64 | 202 | printk("\tindex = 0x%llx\n", (u64)liobn); |
fe333321 IM |
203 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); |
204 | printk("\ttce val = 0x%llx\n", tce ); | |
4ff52b4d | 205 | dump_stack(); |
1da177e4 | 206 | } |
bc97ce95 | 207 | |
1da177e4 | 208 | tcenum++; |
bc97ce95 | 209 | rpn++; |
1da177e4 | 210 | } |
6490c490 | 211 | return ret; |
1da177e4 LT |
212 | } |
213 | ||
df015604 | 214 | static DEFINE_PER_CPU(__be64 *, tce_page); |
1da177e4 | 215 | |
6490c490 | 216 | static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, |
1da177e4 | 217 | long npages, unsigned long uaddr, |
4f3dd8a0 | 218 | enum dma_data_direction direction, |
00085f1e | 219 | unsigned long attrs) |
1da177e4 | 220 | { |
6490c490 | 221 | u64 rc = 0; |
bc97ce95 | 222 | u64 proto_tce; |
df015604 | 223 | __be64 *tcep; |
bc97ce95 | 224 | u64 rpn; |
1da177e4 | 225 | long l, limit; |
6490c490 RJ |
226 | long tcenum_start = tcenum, npages_start = npages; |
227 | int ret = 0; | |
c1703e85 | 228 | unsigned long flags; |
1da177e4 | 229 | |
da004c36 | 230 | if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) { |
b0788c64 AK |
231 | return tce_build_pSeriesLP(tbl->it_index, tcenum, |
232 | tbl->it_page_shift, npages, uaddr, | |
6490c490 | 233 | direction, attrs); |
541b2755 | 234 | } |
1da177e4 | 235 | |
c1703e85 AB |
236 | local_irq_save(flags); /* to protect tcep and the page behind it */ |
237 | ||
69111bac | 238 | tcep = __this_cpu_read(tce_page); |
1da177e4 LT |
239 | |
240 | /* This is safe to do since interrupts are off when we're called | |
241 | * from iommu_alloc{,_sg}() | |
242 | */ | |
243 | if (!tcep) { | |
df015604 | 244 | tcep = (__be64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 | 245 | /* If allocation fails, fall back to the loop implementation */ |
541b2755 | 246 | if (!tcep) { |
c1703e85 | 247 | local_irq_restore(flags); |
b0788c64 AK |
248 | return tce_build_pSeriesLP(tbl->it_index, tcenum, |
249 | tbl->it_page_shift, | |
250 | npages, uaddr, direction, attrs); | |
541b2755 | 251 | } |
69111bac | 252 | __this_cpu_write(tce_page, tcep); |
1da177e4 LT |
253 | } |
254 | ||
474e3d56 | 255 | rpn = __pa(uaddr) >> TCE_SHIFT; |
bc97ce95 | 256 | proto_tce = TCE_PCI_READ; |
1da177e4 | 257 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 258 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
259 | |
260 | /* We can map max one pageful of TCEs at a time */ | |
261 | do { | |
262 | /* | |
263 | * Set up the page with TCE data, looping through and setting | |
264 | * the values. | |
265 | */ | |
bc97ce95 | 266 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
267 | |
268 | for (l = 0; l < limit; l++) { | |
df015604 | 269 | tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT); |
bc97ce95 | 270 | rpn++; |
1da177e4 LT |
271 | } |
272 | ||
273 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
274 | (u64)tcenum << 12, | |
474e3d56 | 275 | (u64)__pa(tcep), |
1da177e4 LT |
276 | limit); |
277 | ||
278 | npages -= limit; | |
279 | tcenum += limit; | |
280 | } while (npages > 0 && !rc); | |
281 | ||
c1703e85 AB |
282 | local_irq_restore(flags); |
283 | ||
6490c490 RJ |
284 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
285 | ret = (int)rc; | |
286 | tce_freemulti_pSeriesLP(tbl, tcenum_start, | |
287 | (npages_start - (npages + limit))); | |
288 | return ret; | |
289 | } | |
290 | ||
1da177e4 | 291 | if (rc && printk_ratelimit()) { |
fe333321 IM |
292 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
293 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
294 | printk("\tnpages = 0x%llx\n", (u64)npages); | |
295 | printk("\ttce[0] val = 0x%llx\n", tcep[0]); | |
4ff52b4d | 296 | dump_stack(); |
1da177e4 | 297 | } |
6490c490 | 298 | return ret; |
1da177e4 LT |
299 | } |
300 | ||
b0788c64 | 301 | static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long npages) |
1da177e4 LT |
302 | { |
303 | u64 rc; | |
1da177e4 | 304 | |
1da177e4 | 305 | while (npages--) { |
b0788c64 | 306 | rc = plpar_tce_put((u64)liobn, (u64)tcenum << 12, 0); |
1da177e4 LT |
307 | |
308 | if (rc && printk_ratelimit()) { | |
fe333321 | 309 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
b0788c64 | 310 | printk("\tindex = 0x%llx\n", (u64)liobn); |
fe333321 | 311 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); |
4ff52b4d | 312 | dump_stack(); |
1da177e4 LT |
313 | } |
314 | ||
315 | tcenum++; | |
316 | } | |
317 | } | |
318 | ||
319 | ||
320 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
321 | { | |
322 | u64 rc; | |
1da177e4 | 323 | |
da004c36 | 324 | if (!firmware_has_feature(FW_FEATURE_MULTITCE)) |
b0788c64 | 325 | return tce_free_pSeriesLP(tbl->it_index, tcenum, npages); |
da004c36 | 326 | |
bc97ce95 | 327 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
328 | |
329 | if (rc && printk_ratelimit()) { | |
330 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
fe333321 IM |
331 | printk("\trc = %lld\n", rc); |
332 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
333 | printk("\tnpages = 0x%llx\n", (u64)npages); | |
4ff52b4d | 334 | dump_stack(); |
1da177e4 LT |
335 | } |
336 | } | |
337 | ||
5f50867b HM |
338 | static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) |
339 | { | |
340 | u64 rc; | |
341 | unsigned long tce_ret; | |
342 | ||
5f50867b HM |
343 | rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); |
344 | ||
345 | if (rc && printk_ratelimit()) { | |
fe333321 IM |
346 | printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc); |
347 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
348 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
4ff52b4d | 349 | dump_stack(); |
5f50867b HM |
350 | } |
351 | ||
352 | return tce_ret; | |
353 | } | |
354 | ||
25985edc | 355 | /* this is compatible with cells for the device tree property */ |
4e8b0cf4 NA |
356 | struct dynamic_dma_window_prop { |
357 | __be32 liobn; /* tce table number */ | |
358 | __be64 dma_base; /* address hi,lo */ | |
359 | __be32 tce_shift; /* ilog2(tce_page_size) */ | |
360 | __be32 window_shift; /* ilog2(tce_window_size) */ | |
361 | }; | |
362 | ||
363 | struct direct_window { | |
364 | struct device_node *device; | |
365 | const struct dynamic_dma_window_prop *prop; | |
366 | struct list_head list; | |
367 | }; | |
368 | ||
369 | /* Dynamic DMA Window support */ | |
370 | struct ddw_query_response { | |
9410e018 AK |
371 | u32 windows_available; |
372 | u32 largest_available_block; | |
373 | u32 page_size; | |
374 | u32 migration_capable; | |
4e8b0cf4 NA |
375 | }; |
376 | ||
377 | struct ddw_create_response { | |
9410e018 AK |
378 | u32 liobn; |
379 | u32 addr_hi; | |
380 | u32 addr_lo; | |
4e8b0cf4 NA |
381 | }; |
382 | ||
383 | static LIST_HEAD(direct_window_list); | |
384 | /* prevents races between memory on/offline and window creation */ | |
385 | static DEFINE_SPINLOCK(direct_window_list_lock); | |
386 | /* protects initializing window twice for same device */ | |
387 | static DEFINE_MUTEX(direct_window_init_mutex); | |
388 | #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info" | |
389 | ||
390 | static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn, | |
391 | unsigned long num_pfn, const void *arg) | |
392 | { | |
393 | const struct dynamic_dma_window_prop *maprange = arg; | |
394 | int rc; | |
395 | u64 tce_size, num_tce, dma_offset, next; | |
396 | u32 tce_shift; | |
397 | long limit; | |
398 | ||
399 | tce_shift = be32_to_cpu(maprange->tce_shift); | |
400 | tce_size = 1ULL << tce_shift; | |
401 | next = start_pfn << PAGE_SHIFT; | |
402 | num_tce = num_pfn << PAGE_SHIFT; | |
403 | ||
404 | /* round back to the beginning of the tce page size */ | |
405 | num_tce += next & (tce_size - 1); | |
406 | next &= ~(tce_size - 1); | |
407 | ||
408 | /* covert to number of tces */ | |
409 | num_tce |= tce_size - 1; | |
410 | num_tce >>= tce_shift; | |
411 | ||
412 | do { | |
413 | /* | |
414 | * Set up the page with TCE data, looping through and setting | |
415 | * the values. | |
416 | */ | |
417 | limit = min_t(long, num_tce, 512); | |
418 | dma_offset = next + be64_to_cpu(maprange->dma_base); | |
419 | ||
420 | rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn), | |
421 | dma_offset, | |
422 | 0, limit); | |
22b38298 | 423 | next += limit * tce_size; |
4e8b0cf4 NA |
424 | num_tce -= limit; |
425 | } while (num_tce > 0 && !rc); | |
426 | ||
427 | return rc; | |
428 | } | |
429 | ||
430 | static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn, | |
431 | unsigned long num_pfn, const void *arg) | |
432 | { | |
433 | const struct dynamic_dma_window_prop *maprange = arg; | |
df015604 AB |
434 | u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn; |
435 | __be64 *tcep; | |
4e8b0cf4 NA |
436 | u32 tce_shift; |
437 | u64 rc = 0; | |
438 | long l, limit; | |
439 | ||
b0788c64 AK |
440 | if (!firmware_has_feature(FW_FEATURE_MULTITCE)) { |
441 | unsigned long tceshift = be32_to_cpu(maprange->tce_shift); | |
442 | unsigned long dmastart = (start_pfn << PAGE_SHIFT) + | |
443 | be64_to_cpu(maprange->dma_base); | |
444 | unsigned long tcenum = dmastart >> tceshift; | |
445 | unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift; | |
446 | void *uaddr = __va(start_pfn << PAGE_SHIFT); | |
447 | ||
448 | return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn), | |
449 | tcenum, tceshift, npages, (unsigned long) uaddr, | |
450 | DMA_BIDIRECTIONAL, 0); | |
451 | } | |
452 | ||
4e8b0cf4 | 453 | local_irq_disable(); /* to protect tcep and the page behind it */ |
69111bac | 454 | tcep = __this_cpu_read(tce_page); |
4e8b0cf4 NA |
455 | |
456 | if (!tcep) { | |
df015604 | 457 | tcep = (__be64 *)__get_free_page(GFP_ATOMIC); |
4e8b0cf4 NA |
458 | if (!tcep) { |
459 | local_irq_enable(); | |
460 | return -ENOMEM; | |
461 | } | |
69111bac | 462 | __this_cpu_write(tce_page, tcep); |
4e8b0cf4 NA |
463 | } |
464 | ||
465 | proto_tce = TCE_PCI_READ | TCE_PCI_WRITE; | |
466 | ||
467 | liobn = (u64)be32_to_cpu(maprange->liobn); | |
468 | tce_shift = be32_to_cpu(maprange->tce_shift); | |
469 | tce_size = 1ULL << tce_shift; | |
470 | next = start_pfn << PAGE_SHIFT; | |
471 | num_tce = num_pfn << PAGE_SHIFT; | |
472 | ||
473 | /* round back to the beginning of the tce page size */ | |
474 | num_tce += next & (tce_size - 1); | |
475 | next &= ~(tce_size - 1); | |
476 | ||
477 | /* covert to number of tces */ | |
478 | num_tce |= tce_size - 1; | |
479 | num_tce >>= tce_shift; | |
480 | ||
481 | /* We can map max one pageful of TCEs at a time */ | |
482 | do { | |
483 | /* | |
484 | * Set up the page with TCE data, looping through and setting | |
485 | * the values. | |
486 | */ | |
487 | limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE); | |
488 | dma_offset = next + be64_to_cpu(maprange->dma_base); | |
489 | ||
490 | for (l = 0; l < limit; l++) { | |
df015604 | 491 | tcep[l] = cpu_to_be64(proto_tce | next); |
4e8b0cf4 NA |
492 | next += tce_size; |
493 | } | |
494 | ||
495 | rc = plpar_tce_put_indirect(liobn, | |
496 | dma_offset, | |
474e3d56 | 497 | (u64)__pa(tcep), |
4e8b0cf4 NA |
498 | limit); |
499 | ||
500 | num_tce -= limit; | |
501 | } while (num_tce > 0 && !rc); | |
502 | ||
503 | /* error cleanup: caller will clear whole range */ | |
504 | ||
505 | local_irq_enable(); | |
506 | return rc; | |
507 | } | |
508 | ||
509 | static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn, | |
510 | unsigned long num_pfn, void *arg) | |
511 | { | |
512 | return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg); | |
513 | } | |
514 | ||
1da177e4 LT |
515 | static void iommu_table_setparms(struct pci_controller *phb, |
516 | struct device_node *dn, | |
bc97ce95 | 517 | struct iommu_table *tbl) |
1da177e4 LT |
518 | { |
519 | struct device_node *node; | |
b7d6bf4f | 520 | const unsigned long *basep; |
9938c474 | 521 | const u32 *sizep; |
1da177e4 | 522 | |
44ef3390 | 523 | node = phb->dn; |
1da177e4 | 524 | |
e2eb6392 SR |
525 | basep = of_get_property(node, "linux,tce-base", NULL); |
526 | sizep = of_get_property(node, "linux,tce-size", NULL); | |
1da177e4 | 527 | if (basep == NULL || sizep == NULL) { |
b7c670d6 RH |
528 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %pOF has " |
529 | "missing tce entries !\n", dn); | |
1da177e4 LT |
530 | return; |
531 | } | |
532 | ||
533 | tbl->it_base = (unsigned long)__va(*basep); | |
5f50867b | 534 | |
62a8bd6c | 535 | if (!is_kdump_kernel()) |
54622f10 | 536 | memset((void *)tbl->it_base, 0, *sizep); |
1da177e4 LT |
537 | |
538 | tbl->it_busno = phb->bus->number; | |
3a553170 | 539 | tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; |
bc97ce95 | 540 | |
1da177e4 | 541 | /* Units of tce entries */ |
3a553170 | 542 | tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift; |
bc97ce95 | 543 | |
1da177e4 | 544 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
545 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
546 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 547 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 548 | } |
bc97ce95 | 549 | |
1da177e4 LT |
550 | phb->dma_window_base_cur += phb->dma_window_size; |
551 | ||
552 | /* Set the tce table size - measured in entries */ | |
3a553170 | 553 | tbl->it_size = phb->dma_window_size >> tbl->it_page_shift; |
1da177e4 LT |
554 | |
555 | tbl->it_index = 0; | |
556 | tbl->it_blocksize = 16; | |
557 | tbl->it_type = TCE_PCI; | |
558 | } | |
559 | ||
560 | /* | |
561 | * iommu_table_setparms_lpar | |
562 | * | |
563 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
564 | */ |
565 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
566 | struct device_node *dn, | |
567 | struct iommu_table *tbl, | |
b6e1f6ad | 568 | struct iommu_table_group *table_group, |
2083f681 | 569 | const __be32 *dma_window) |
1da177e4 | 570 | { |
4c76e0bc JK |
571 | unsigned long offset, size; |
572 | ||
4c76e0bc | 573 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 574 | |
b8c49def | 575 | tbl->it_busno = phb->bus->number; |
3a553170 | 576 | tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; |
1da177e4 | 577 | tbl->it_base = 0; |
1da177e4 LT |
578 | tbl->it_blocksize = 16; |
579 | tbl->it_type = TCE_PCI; | |
3a553170 AP |
580 | tbl->it_offset = offset >> tbl->it_page_shift; |
581 | tbl->it_size = size >> tbl->it_page_shift; | |
b6e1f6ad AK |
582 | |
583 | table_group->tce32_start = offset; | |
584 | table_group->tce32_size = size; | |
1da177e4 LT |
585 | } |
586 | ||
da004c36 AK |
587 | struct iommu_table_ops iommu_table_pseries_ops = { |
588 | .set = tce_build_pSeries, | |
589 | .clear = tce_free_pSeries, | |
590 | .get = tce_get_pseries | |
591 | }; | |
592 | ||
12d04eef | 593 | static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) |
1da177e4 | 594 | { |
3c2822cc | 595 | struct device_node *dn; |
1da177e4 | 596 | struct iommu_table *tbl; |
3c2822cc OJ |
597 | struct device_node *isa_dn, *isa_dn_orig; |
598 | struct device_node *tmp; | |
599 | struct pci_dn *pci; | |
600 | int children; | |
1da177e4 | 601 | |
3c2822cc | 602 | dn = pci_bus_to_OF_node(bus); |
12d04eef | 603 | |
b7c670d6 | 604 | pr_debug("pci_dma_bus_setup_pSeries: setting up bus %pOF\n", dn); |
3c2822cc OJ |
605 | |
606 | if (bus->self) { | |
607 | /* This is not a root bus, any setup will be done for the | |
608 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
609 | */ | |
610 | return; | |
611 | } | |
12d04eef | 612 | pci = PCI_DN(dn); |
3c2822cc OJ |
613 | |
614 | /* Check if the ISA bus on the system is under | |
615 | * this PHB. | |
1da177e4 | 616 | */ |
3c2822cc | 617 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 618 | |
3c2822cc OJ |
619 | while (isa_dn && isa_dn != dn) |
620 | isa_dn = isa_dn->parent; | |
621 | ||
498b6514 | 622 | of_node_put(isa_dn_orig); |
1da177e4 | 623 | |
d3c58fb1 | 624 | /* Count number of direct PCI children of the PHB. */ |
3c2822cc | 625 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) |
d3c58fb1 | 626 | children++; |
1da177e4 | 627 | |
f7ebf352 | 628 | pr_debug("Children: %d\n", children); |
1da177e4 | 629 | |
3c2822cc OJ |
630 | /* Calculate amount of DMA window per slot. Each window must be |
631 | * a power of two (due to pci_alloc_consistent requirements). | |
632 | * | |
633 | * Keep 256MB aside for PHBs with ISA. | |
634 | */ | |
1da177e4 | 635 | |
3c2822cc OJ |
636 | if (!isa_dn) { |
637 | /* No ISA/IDE - just set window size and return */ | |
638 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
639 | ||
640 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
641 | pci->phb->dma_window_size >>= 1; | |
41febbc8 | 642 | pr_debug("No ISA/IDE, window size is 0x%llx\n", |
f7ebf352 | 643 | pci->phb->dma_window_size); |
3c2822cc OJ |
644 | pci->phb->dma_window_base_cur = 0; |
645 | ||
646 | return; | |
1da177e4 | 647 | } |
3c2822cc OJ |
648 | |
649 | /* If we have ISA, then we probably have an IDE | |
650 | * controller too. Allocate a 128MB table but | |
651 | * skip the first 128MB to avoid stepping on ISA | |
652 | * space. | |
653 | */ | |
654 | pci->phb->dma_window_size = 0x8000000ul; | |
655 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
656 | ||
b348aa65 AK |
657 | pci->table_group = iommu_pseries_alloc_group(pci->phb->node); |
658 | tbl = pci->table_group->tables[0]; | |
3c2822cc OJ |
659 | |
660 | iommu_table_setparms(pci->phb, dn, tbl); | |
da004c36 | 661 | tbl->it_ops = &iommu_table_pseries_ops; |
b348aa65 | 662 | iommu_init_table(tbl, pci->phb->node); |
3c2822cc OJ |
663 | |
664 | /* Divide the rest (1.75GB) among the children */ | |
665 | pci->phb->dma_window_size = 0x80000000ul; | |
666 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
667 | pci->phb->dma_window_size >>= 1; | |
668 | ||
41febbc8 | 669 | pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); |
1da177e4 LT |
670 | } |
671 | ||
b6e1f6ad AK |
672 | #ifdef CONFIG_IOMMU_API |
673 | static int tce_exchange_pseries(struct iommu_table *tbl, long index, unsigned | |
674 | long *tce, enum dma_data_direction *direction) | |
675 | { | |
676 | long rc; | |
677 | unsigned long ioba = (unsigned long) index << tbl->it_page_shift; | |
678 | unsigned long flags, oldtce = 0; | |
679 | u64 proto_tce = iommu_direction_to_tce_perm(*direction); | |
680 | unsigned long newtce = *tce | proto_tce; | |
681 | ||
682 | spin_lock_irqsave(&tbl->large_pool.lock, flags); | |
683 | ||
684 | rc = plpar_tce_get((u64)tbl->it_index, ioba, &oldtce); | |
685 | if (!rc) | |
686 | rc = plpar_tce_put((u64)tbl->it_index, ioba, newtce); | |
687 | ||
688 | if (!rc) { | |
689 | *direction = iommu_tce_direction(oldtce); | |
690 | *tce = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE); | |
691 | } | |
692 | ||
693 | spin_unlock_irqrestore(&tbl->large_pool.lock, flags); | |
694 | ||
695 | return rc; | |
696 | } | |
697 | #endif | |
698 | ||
da004c36 AK |
699 | struct iommu_table_ops iommu_table_lpar_multi_ops = { |
700 | .set = tce_buildmulti_pSeriesLP, | |
b6e1f6ad AK |
701 | #ifdef CONFIG_IOMMU_API |
702 | .exchange = tce_exchange_pseries, | |
703 | #endif | |
da004c36 AK |
704 | .clear = tce_freemulti_pSeriesLP, |
705 | .get = tce_get_pSeriesLP | |
706 | }; | |
1da177e4 | 707 | |
12d04eef | 708 | static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) |
1da177e4 LT |
709 | { |
710 | struct iommu_table *tbl; | |
711 | struct device_node *dn, *pdn; | |
1635317f | 712 | struct pci_dn *ppci; |
2083f681 | 713 | const __be32 *dma_window = NULL; |
1da177e4 | 714 | |
1da177e4 LT |
715 | dn = pci_bus_to_OF_node(bus); |
716 | ||
b7c670d6 RH |
717 | pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %pOF\n", |
718 | dn); | |
12d04eef | 719 | |
1da177e4 LT |
720 | /* Find nearest ibm,dma-window, walking up the device tree */ |
721 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
e2eb6392 | 722 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
723 | if (dma_window != NULL) |
724 | break; | |
725 | } | |
726 | ||
727 | if (dma_window == NULL) { | |
f7ebf352 | 728 | pr_debug(" no ibm,dma-window property !\n"); |
1da177e4 LT |
729 | return; |
730 | } | |
731 | ||
e07102db | 732 | ppci = PCI_DN(pdn); |
12d04eef | 733 | |
b7c670d6 RH |
734 | pr_debug(" parent is %pOF, iommu_table: 0x%p\n", |
735 | pdn, ppci->table_group); | |
12d04eef | 736 | |
b348aa65 AK |
737 | if (!ppci->table_group) { |
738 | ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node); | |
739 | tbl = ppci->table_group->tables[0]; | |
b6e1f6ad AK |
740 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, |
741 | ppci->table_group, dma_window); | |
da004c36 | 742 | tbl->it_ops = &iommu_table_lpar_multi_ops; |
b348aa65 AK |
743 | iommu_init_table(tbl, ppci->phb->node); |
744 | iommu_register_group(ppci->table_group, | |
745 | pci_domain_nr(bus), 0); | |
746 | pr_debug(" created table: %p\n", ppci->table_group); | |
1da177e4 | 747 | } |
1da177e4 LT |
748 | } |
749 | ||
750 | ||
12d04eef | 751 | static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) |
1da177e4 | 752 | { |
12d04eef | 753 | struct device_node *dn; |
3c2822cc | 754 | struct iommu_table *tbl; |
1da177e4 | 755 | |
f7ebf352 | 756 | pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); |
1da177e4 | 757 | |
58f9b0b0 | 758 | dn = dev->dev.of_node; |
1da177e4 | 759 | |
3c2822cc OJ |
760 | /* If we're the direct child of a root bus, then we need to allocate |
761 | * an iommu table ourselves. The bus setup code should have setup | |
762 | * the window sizes already. | |
763 | */ | |
764 | if (!dev->bus->self) { | |
12d04eef BH |
765 | struct pci_controller *phb = PCI_DN(dn)->phb; |
766 | ||
f7ebf352 | 767 | pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); |
b348aa65 AK |
768 | PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node); |
769 | tbl = PCI_DN(dn)->table_group->tables[0]; | |
12d04eef | 770 | iommu_table_setparms(phb, dn, tbl); |
da004c36 | 771 | tbl->it_ops = &iommu_table_pseries_ops; |
b348aa65 | 772 | iommu_init_table(tbl, phb->node); |
4617082e | 773 | set_iommu_table_base(&dev->dev, tbl); |
3c2822cc OJ |
774 | return; |
775 | } | |
776 | ||
777 | /* If this device is further down the bus tree, search upwards until | |
778 | * an already allocated iommu table is found and use that. | |
779 | */ | |
780 | ||
b348aa65 | 781 | while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL) |
1da177e4 LT |
782 | dn = dn->parent; |
783 | ||
6d350297 | 784 | if (dn && PCI_DN(dn)) |
b348aa65 AK |
785 | set_iommu_table_base(&dev->dev, |
786 | PCI_DN(dn)->table_group->tables[0]); | |
6d350297 | 787 | else |
12d04eef BH |
788 | printk(KERN_WARNING "iommu: Device %s has no iommu table\n", |
789 | pci_name(dev)); | |
1da177e4 LT |
790 | } |
791 | ||
4e8b0cf4 NA |
792 | static int __read_mostly disable_ddw; |
793 | ||
794 | static int __init disable_ddw_setup(char *str) | |
795 | { | |
796 | disable_ddw = 1; | |
797 | printk(KERN_INFO "ppc iommu: disabling ddw.\n"); | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | early_param("disable_ddw", disable_ddw_setup); | |
803 | ||
5efbabe0 | 804 | static void remove_ddw(struct device_node *np, bool remove_prop) |
4e8b0cf4 NA |
805 | { |
806 | struct dynamic_dma_window_prop *dwp; | |
807 | struct property *win64; | |
9410e018 | 808 | u32 ddw_avail[3]; |
4e8b0cf4 | 809 | u64 liobn; |
9410e018 AK |
810 | int ret = 0; |
811 | ||
812 | ret = of_property_read_u32_array(np, "ibm,ddw-applicable", | |
813 | &ddw_avail[0], 3); | |
4e8b0cf4 | 814 | |
4e8b0cf4 | 815 | win64 = of_find_property(np, DIRECT64_PROPNAME, NULL); |
2573f684 | 816 | if (!win64) |
4e8b0cf4 NA |
817 | return; |
818 | ||
9410e018 | 819 | if (ret || win64->length < sizeof(*dwp)) |
2573f684 MM |
820 | goto delprop; |
821 | ||
4e8b0cf4 NA |
822 | dwp = win64->value; |
823 | liobn = (u64)be32_to_cpu(dwp->liobn); | |
824 | ||
825 | /* clear the whole window, note the arg is in kernel pages */ | |
826 | ret = tce_clearrange_multi_pSeriesLP(0, | |
827 | 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp); | |
828 | if (ret) | |
b7c670d6 RH |
829 | pr_warning("%pOF failed to clear tces in window.\n", |
830 | np); | |
4e8b0cf4 | 831 | else |
b7c670d6 RH |
832 | pr_debug("%pOF successfully cleared tces in window.\n", |
833 | np); | |
4e8b0cf4 | 834 | |
ae69e1ed NA |
835 | ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn); |
836 | if (ret) | |
b7c670d6 | 837 | pr_warning("%pOF: failed to remove direct window: rtas returned " |
ae69e1ed | 838 | "%d to ibm,remove-pe-dma-window(%x) %llx\n", |
b7c670d6 | 839 | np, ret, ddw_avail[2], liobn); |
ae69e1ed | 840 | else |
b7c670d6 | 841 | pr_debug("%pOF: successfully removed direct window: rtas returned " |
ae69e1ed | 842 | "%d to ibm,remove-pe-dma-window(%x) %llx\n", |
b7c670d6 | 843 | np, ret, ddw_avail[2], liobn); |
4e8b0cf4 | 844 | |
2573f684 | 845 | delprop: |
5efbabe0 GS |
846 | if (remove_prop) |
847 | ret = of_remove_property(np, win64); | |
2573f684 | 848 | if (ret) |
b7c670d6 RH |
849 | pr_warning("%pOF: failed to remove direct window property: %d\n", |
850 | np, ret); | |
2573f684 | 851 | } |
4e8b0cf4 | 852 | |
b73a635f | 853 | static u64 find_existing_ddw(struct device_node *pdn) |
4e8b0cf4 | 854 | { |
4e8b0cf4 NA |
855 | struct direct_window *window; |
856 | const struct dynamic_dma_window_prop *direct64; | |
857 | u64 dma_addr = 0; | |
858 | ||
4e8b0cf4 NA |
859 | spin_lock(&direct_window_list_lock); |
860 | /* check if we already created a window and dupe that config if so */ | |
861 | list_for_each_entry(window, &direct_window_list, list) { | |
862 | if (window->device == pdn) { | |
863 | direct64 = window->prop; | |
df015604 | 864 | dma_addr = be64_to_cpu(direct64->dma_base); |
4e8b0cf4 NA |
865 | break; |
866 | } | |
867 | } | |
868 | spin_unlock(&direct_window_list_lock); | |
869 | ||
870 | return dma_addr; | |
871 | } | |
872 | ||
c8566780 | 873 | static int find_existing_ddw_windows(void) |
4e8b0cf4 | 874 | { |
97e7dc52 | 875 | int len; |
c8566780 | 876 | struct device_node *pdn; |
97e7dc52 | 877 | struct direct_window *window; |
4e8b0cf4 | 878 | const struct dynamic_dma_window_prop *direct64; |
4e8b0cf4 | 879 | |
c8566780 MM |
880 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
881 | return 0; | |
882 | ||
883 | for_each_node_with_property(pdn, DIRECT64_PROPNAME) { | |
97e7dc52 | 884 | direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len); |
c8566780 MM |
885 | if (!direct64) |
886 | continue; | |
887 | ||
97e7dc52 NA |
888 | window = kzalloc(sizeof(*window), GFP_KERNEL); |
889 | if (!window || len < sizeof(struct dynamic_dma_window_prop)) { | |
890 | kfree(window); | |
5efbabe0 | 891 | remove_ddw(pdn, true); |
97e7dc52 NA |
892 | continue; |
893 | } | |
c8566780 | 894 | |
97e7dc52 NA |
895 | window->device = pdn; |
896 | window->prop = direct64; | |
897 | spin_lock(&direct_window_list_lock); | |
898 | list_add(&window->list, &direct_window_list); | |
899 | spin_unlock(&direct_window_list_lock); | |
4e8b0cf4 NA |
900 | } |
901 | ||
c8566780 | 902 | return 0; |
4e8b0cf4 | 903 | } |
c8566780 | 904 | machine_arch_initcall(pseries, find_existing_ddw_windows); |
4e8b0cf4 | 905 | |
b73a635f | 906 | static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail, |
4e8b0cf4 NA |
907 | struct ddw_query_response *query) |
908 | { | |
8445a87f GP |
909 | struct device_node *dn; |
910 | struct pci_dn *pdn; | |
4e8b0cf4 NA |
911 | u32 cfg_addr; |
912 | u64 buid; | |
913 | int ret; | |
914 | ||
915 | /* | |
916 | * Get the config address and phb buid of the PE window. | |
917 | * Rely on eeh to retrieve this for us. | |
918 | * Retrieve them from the pci device, not the node with the | |
919 | * dma-window property | |
920 | */ | |
8445a87f GP |
921 | dn = pci_device_to_OF_node(dev); |
922 | pdn = PCI_DN(dn); | |
923 | buid = pdn->phb->buid; | |
8a934efe | 924 | cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8)); |
39baadbf | 925 | |
b73a635f | 926 | ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query, |
4e8b0cf4 NA |
927 | cfg_addr, BUID_HI(buid), BUID_LO(buid)); |
928 | dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x" | |
b73a635f | 929 | " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid), |
4e8b0cf4 NA |
930 | BUID_LO(buid), ret); |
931 | return ret; | |
932 | } | |
933 | ||
b73a635f | 934 | static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail, |
4e8b0cf4 NA |
935 | struct ddw_create_response *create, int page_shift, |
936 | int window_shift) | |
937 | { | |
8445a87f GP |
938 | struct device_node *dn; |
939 | struct pci_dn *pdn; | |
4e8b0cf4 NA |
940 | u32 cfg_addr; |
941 | u64 buid; | |
942 | int ret; | |
943 | ||
944 | /* | |
945 | * Get the config address and phb buid of the PE window. | |
946 | * Rely on eeh to retrieve this for us. | |
947 | * Retrieve them from the pci device, not the node with the | |
948 | * dma-window property | |
949 | */ | |
8445a87f GP |
950 | dn = pci_device_to_OF_node(dev); |
951 | pdn = PCI_DN(dn); | |
952 | buid = pdn->phb->buid; | |
8a934efe | 953 | cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8)); |
4e8b0cf4 NA |
954 | |
955 | do { | |
956 | /* extra outputs are LIOBN and dma-addr (hi, lo) */ | |
9410e018 AK |
957 | ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, |
958 | cfg_addr, BUID_HI(buid), BUID_LO(buid), | |
959 | page_shift, window_shift); | |
4e8b0cf4 NA |
960 | } while (rtas_busy_delay(ret)); |
961 | dev_info(&dev->dev, | |
962 | "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d " | |
b73a635f | 963 | "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1], |
4e8b0cf4 NA |
964 | cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift, |
965 | window_shift, ret, create->liobn, create->addr_hi, create->addr_lo); | |
966 | ||
967 | return ret; | |
968 | } | |
969 | ||
61435690 NA |
970 | struct failed_ddw_pdn { |
971 | struct device_node *pdn; | |
972 | struct list_head list; | |
973 | }; | |
974 | ||
975 | static LIST_HEAD(failed_ddw_pdn_list); | |
976 | ||
8f189f6b AK |
977 | static phys_addr_t ddw_memory_hotplug_max(void) |
978 | { | |
979 | phys_addr_t max_addr = memory_hotplug_max(); | |
980 | struct device_node *memory; | |
981 | ||
982 | for_each_node_by_type(memory, "memory") { | |
983 | unsigned long start, size; | |
984 | int ranges, n_mem_addr_cells, n_mem_size_cells, len; | |
985 | const __be32 *memcell_buf; | |
986 | ||
987 | memcell_buf = of_get_property(memory, "reg", &len); | |
988 | if (!memcell_buf || len <= 0) | |
989 | continue; | |
990 | ||
991 | n_mem_addr_cells = of_n_addr_cells(memory); | |
992 | n_mem_size_cells = of_n_size_cells(memory); | |
993 | ||
994 | /* ranges in cell */ | |
995 | ranges = (len >> 2) / (n_mem_addr_cells + n_mem_size_cells); | |
996 | ||
997 | start = of_read_number(memcell_buf, n_mem_addr_cells); | |
998 | memcell_buf += n_mem_addr_cells; | |
999 | size = of_read_number(memcell_buf, n_mem_size_cells); | |
1000 | memcell_buf += n_mem_size_cells; | |
1001 | ||
1002 | max_addr = max_t(phys_addr_t, max_addr, start + size); | |
1003 | } | |
1004 | ||
1005 | return max_addr; | |
1006 | } | |
1007 | ||
4e8b0cf4 NA |
1008 | /* |
1009 | * If the PE supports dynamic dma windows, and there is space for a table | |
1010 | * that can map all pages in a linear offset, then setup such a table, | |
1011 | * and record the dma-offset in the struct device. | |
1012 | * | |
1013 | * dev: the pci device we are checking | |
1014 | * pdn: the parent pe node with the ibm,dma_window property | |
1015 | * Future: also check if we can remap the base window for our base page size | |
1016 | * | |
1017 | * returns the dma offset for use by dma_set_mask | |
1018 | */ | |
1019 | static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn) | |
1020 | { | |
1021 | int len, ret; | |
1022 | struct ddw_query_response query; | |
1023 | struct ddw_create_response create; | |
1024 | int page_shift; | |
1025 | u64 dma_addr, max_addr; | |
1026 | struct device_node *dn; | |
9410e018 | 1027 | u32 ddw_avail[3]; |
4e8b0cf4 | 1028 | struct direct_window *window; |
76730334 | 1029 | struct property *win64; |
4e8b0cf4 | 1030 | struct dynamic_dma_window_prop *ddwprop; |
61435690 | 1031 | struct failed_ddw_pdn *fpdn; |
4e8b0cf4 NA |
1032 | |
1033 | mutex_lock(&direct_window_init_mutex); | |
1034 | ||
b73a635f | 1035 | dma_addr = find_existing_ddw(pdn); |
4e8b0cf4 NA |
1036 | if (dma_addr != 0) |
1037 | goto out_unlock; | |
1038 | ||
61435690 NA |
1039 | /* |
1040 | * If we already went through this for a previous function of | |
1041 | * the same device and failed, we don't want to muck with the | |
1042 | * DMA window again, as it will race with in-flight operations | |
1043 | * and can lead to EEHs. The above mutex protects access to the | |
1044 | * list. | |
1045 | */ | |
1046 | list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) { | |
b7c670d6 | 1047 | if (fpdn->pdn == pdn) |
61435690 NA |
1048 | goto out_unlock; |
1049 | } | |
1050 | ||
4e8b0cf4 NA |
1051 | /* |
1052 | * the ibm,ddw-applicable property holds the tokens for: | |
1053 | * ibm,query-pe-dma-window | |
1054 | * ibm,create-pe-dma-window | |
1055 | * ibm,remove-pe-dma-window | |
1056 | * for the given node in that order. | |
1057 | * the property is actually in the parent, not the PE | |
1058 | */ | |
9410e018 AK |
1059 | ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable", |
1060 | &ddw_avail[0], 3); | |
1061 | if (ret) | |
ae69e1ed | 1062 | goto out_failed; |
25ebc45b | 1063 | |
ae69e1ed | 1064 | /* |
4e8b0cf4 NA |
1065 | * Query if there is a second window of size to map the |
1066 | * whole partition. Query returns number of windows, largest | |
1067 | * block assigned to PE (partition endpoint), and two bitmasks | |
1068 | * of page sizes: supported and supported for migrate-dma. | |
1069 | */ | |
1070 | dn = pci_device_to_OF_node(dev); | |
b73a635f | 1071 | ret = query_ddw(dev, ddw_avail, &query); |
4e8b0cf4 | 1072 | if (ret != 0) |
ae69e1ed | 1073 | goto out_failed; |
4e8b0cf4 NA |
1074 | |
1075 | if (query.windows_available == 0) { | |
1076 | /* | |
1077 | * no additional windows are available for this device. | |
1078 | * We might be able to reallocate the existing window, | |
1079 | * trading in for a larger page size. | |
1080 | */ | |
1081 | dev_dbg(&dev->dev, "no free dynamic windows"); | |
ae69e1ed | 1082 | goto out_failed; |
4e8b0cf4 | 1083 | } |
9410e018 | 1084 | if (query.page_size & 4) { |
4e8b0cf4 | 1085 | page_shift = 24; /* 16MB */ |
9410e018 | 1086 | } else if (query.page_size & 2) { |
4e8b0cf4 | 1087 | page_shift = 16; /* 64kB */ |
9410e018 | 1088 | } else if (query.page_size & 1) { |
4e8b0cf4 NA |
1089 | page_shift = 12; /* 4kB */ |
1090 | } else { | |
1091 | dev_dbg(&dev->dev, "no supported direct page size in mask %x", | |
1092 | query.page_size); | |
ae69e1ed | 1093 | goto out_failed; |
4e8b0cf4 NA |
1094 | } |
1095 | /* verify the window * number of ptes will map the partition */ | |
1096 | /* check largest block * page size > max memory hotplug addr */ | |
8f189f6b | 1097 | max_addr = ddw_memory_hotplug_max(); |
9410e018 | 1098 | if (query.largest_available_block < (max_addr >> page_shift)) { |
8ab102d6 | 1099 | dev_dbg(&dev->dev, "can't map partition max 0x%llx with %u " |
4e8b0cf4 NA |
1100 | "%llu-sized pages\n", max_addr, query.largest_available_block, |
1101 | 1ULL << page_shift); | |
ae69e1ed | 1102 | goto out_failed; |
4e8b0cf4 NA |
1103 | } |
1104 | len = order_base_2(max_addr); | |
1105 | win64 = kzalloc(sizeof(struct property), GFP_KERNEL); | |
1106 | if (!win64) { | |
1107 | dev_info(&dev->dev, | |
1108 | "couldn't allocate property for 64bit dma window\n"); | |
ae69e1ed | 1109 | goto out_failed; |
4e8b0cf4 NA |
1110 | } |
1111 | win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL); | |
1112 | win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL); | |
76730334 | 1113 | win64->length = sizeof(*ddwprop); |
4e8b0cf4 NA |
1114 | if (!win64->name || !win64->value) { |
1115 | dev_info(&dev->dev, | |
1116 | "couldn't allocate property name and value\n"); | |
1117 | goto out_free_prop; | |
1118 | } | |
1119 | ||
b73a635f | 1120 | ret = create_ddw(dev, ddw_avail, &create, page_shift, len); |
4e8b0cf4 NA |
1121 | if (ret != 0) |
1122 | goto out_free_prop; | |
1123 | ||
9410e018 AK |
1124 | ddwprop->liobn = cpu_to_be32(create.liobn); |
1125 | ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) | | |
1126 | create.addr_lo); | |
4e8b0cf4 NA |
1127 | ddwprop->tce_shift = cpu_to_be32(page_shift); |
1128 | ddwprop->window_shift = cpu_to_be32(len); | |
1129 | ||
b7c670d6 RH |
1130 | dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %pOF\n", |
1131 | create.liobn, dn); | |
4e8b0cf4 NA |
1132 | |
1133 | window = kzalloc(sizeof(*window), GFP_KERNEL); | |
1134 | if (!window) | |
1135 | goto out_clear_window; | |
1136 | ||
1137 | ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT, | |
1138 | win64->value, tce_setrange_multi_pSeriesLP_walk); | |
1139 | if (ret) { | |
b7c670d6 RH |
1140 | dev_info(&dev->dev, "failed to map direct window for %pOF: %d\n", |
1141 | dn, ret); | |
7a19081f | 1142 | goto out_free_window; |
4e8b0cf4 NA |
1143 | } |
1144 | ||
79d1c712 | 1145 | ret = of_add_property(pdn, win64); |
4e8b0cf4 | 1146 | if (ret) { |
b7c670d6 RH |
1147 | dev_err(&dev->dev, "unable to add dma window property for %pOF: %d", |
1148 | pdn, ret); | |
7a19081f | 1149 | goto out_free_window; |
4e8b0cf4 NA |
1150 | } |
1151 | ||
1152 | window->device = pdn; | |
1153 | window->prop = ddwprop; | |
1154 | spin_lock(&direct_window_list_lock); | |
1155 | list_add(&window->list, &direct_window_list); | |
1156 | spin_unlock(&direct_window_list_lock); | |
1157 | ||
9410e018 | 1158 | dma_addr = be64_to_cpu(ddwprop->dma_base); |
4e8b0cf4 NA |
1159 | goto out_unlock; |
1160 | ||
7a19081f JL |
1161 | out_free_window: |
1162 | kfree(window); | |
1163 | ||
4e8b0cf4 | 1164 | out_clear_window: |
5efbabe0 | 1165 | remove_ddw(pdn, true); |
4e8b0cf4 NA |
1166 | |
1167 | out_free_prop: | |
1168 | kfree(win64->name); | |
1169 | kfree(win64->value); | |
1170 | kfree(win64); | |
1171 | ||
ae69e1ed | 1172 | out_failed: |
25ebc45b | 1173 | |
61435690 NA |
1174 | fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL); |
1175 | if (!fpdn) | |
1176 | goto out_unlock; | |
1177 | fpdn->pdn = pdn; | |
1178 | list_add(&fpdn->list, &failed_ddw_pdn_list); | |
1179 | ||
4e8b0cf4 NA |
1180 | out_unlock: |
1181 | mutex_unlock(&direct_window_init_mutex); | |
1182 | return dma_addr; | |
1183 | } | |
1184 | ||
12d04eef | 1185 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
1da177e4 LT |
1186 | { |
1187 | struct device_node *pdn, *dn; | |
1188 | struct iommu_table *tbl; | |
2083f681 | 1189 | const __be32 *dma_window = NULL; |
1635317f | 1190 | struct pci_dn *pci; |
1da177e4 | 1191 | |
f7ebf352 | 1192 | pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); |
12d04eef | 1193 | |
1da177e4 | 1194 | /* dev setup for LPAR is a little tricky, since the device tree might |
25985edc | 1195 | * contain the dma-window properties per-device and not necessarily |
1da177e4 LT |
1196 | * for the bus. So we need to search upwards in the tree until we |
1197 | * either hit a dma-window property, OR find a parent with a table | |
1198 | * already allocated. | |
1199 | */ | |
1200 | dn = pci_device_to_OF_node(dev); | |
b7c670d6 | 1201 | pr_debug(" node is %pOF\n", dn); |
5d2efba6 | 1202 | |
b348aa65 | 1203 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group; |
1635317f | 1204 | pdn = pdn->parent) { |
e2eb6392 | 1205 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
1206 | if (dma_window) |
1207 | break; | |
1208 | } | |
1209 | ||
650f7b3b LV |
1210 | if (!pdn || !PCI_DN(pdn)) { |
1211 | printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " | |
b7c670d6 RH |
1212 | "no DMA window found for pci dev=%s dn=%pOF\n", |
1213 | pci_name(dev), dn); | |
650f7b3b LV |
1214 | return; |
1215 | } | |
b7c670d6 | 1216 | pr_debug(" parent is %pOF\n", pdn); |
12d04eef | 1217 | |
e07102db | 1218 | pci = PCI_DN(pdn); |
b348aa65 AK |
1219 | if (!pci->table_group) { |
1220 | pci->table_group = iommu_pseries_alloc_group(pci->phb->node); | |
1221 | tbl = pci->table_group->tables[0]; | |
b6e1f6ad AK |
1222 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, |
1223 | pci->table_group, dma_window); | |
da004c36 | 1224 | tbl->it_ops = &iommu_table_lpar_multi_ops; |
b348aa65 AK |
1225 | iommu_init_table(tbl, pci->phb->node); |
1226 | iommu_register_group(pci->table_group, | |
1227 | pci_domain_nr(pci->phb->bus), 0); | |
1228 | pr_debug(" created table: %p\n", pci->table_group); | |
de113217 | 1229 | } else { |
b348aa65 | 1230 | pr_debug(" found DMA window, table: %p\n", pci->table_group); |
1da177e4 LT |
1231 | } |
1232 | ||
b348aa65 | 1233 | set_iommu_table_base(&dev->dev, pci->table_group->tables[0]); |
4617082e | 1234 | iommu_add_device(&dev->dev); |
1da177e4 | 1235 | } |
4e8b0cf4 NA |
1236 | |
1237 | static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask) | |
1238 | { | |
1239 | bool ddw_enabled = false; | |
1240 | struct device_node *pdn, *dn; | |
1241 | struct pci_dev *pdev; | |
2083f681 | 1242 | const __be32 *dma_window = NULL; |
4e8b0cf4 NA |
1243 | u64 dma_offset; |
1244 | ||
64ac822f | 1245 | if (!dev->dma_mask) |
4e8b0cf4 NA |
1246 | return -EIO; |
1247 | ||
64ac822f MM |
1248 | if (!dev_is_pci(dev)) |
1249 | goto check_mask; | |
1250 | ||
eb0dd411 NA |
1251 | pdev = to_pci_dev(dev); |
1252 | ||
4e8b0cf4 NA |
1253 | /* only attempt to use a new window if 64-bit DMA is requested */ |
1254 | if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) { | |
4e8b0cf4 | 1255 | dn = pci_device_to_OF_node(pdev); |
b7c670d6 | 1256 | dev_dbg(dev, "node is %pOF\n", dn); |
4e8b0cf4 NA |
1257 | |
1258 | /* | |
1259 | * the device tree might contain the dma-window properties | |
25985edc | 1260 | * per-device and not necessarily for the bus. So we need to |
4e8b0cf4 NA |
1261 | * search upwards in the tree until we either hit a dma-window |
1262 | * property, OR find a parent with a table already allocated. | |
1263 | */ | |
b348aa65 | 1264 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group; |
4e8b0cf4 NA |
1265 | pdn = pdn->parent) { |
1266 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); | |
1267 | if (dma_window) | |
1268 | break; | |
1269 | } | |
1270 | if (pdn && PCI_DN(pdn)) { | |
1271 | dma_offset = enable_ddw(pdev, pdn); | |
1272 | if (dma_offset != 0) { | |
1273 | dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset); | |
1274 | set_dma_offset(dev, dma_offset); | |
1275 | set_dma_ops(dev, &dma_direct_ops); | |
1276 | ddw_enabled = true; | |
1277 | } | |
1278 | } | |
1279 | } | |
1280 | ||
e91c2511 | 1281 | /* fall back on iommu ops */ |
64ac822f MM |
1282 | if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) { |
1283 | dev_info(dev, "Restoring 32-bit DMA via iommu\n"); | |
4e8b0cf4 NA |
1284 | set_dma_ops(dev, &dma_iommu_ops); |
1285 | } | |
1286 | ||
64ac822f MM |
1287 | check_mask: |
1288 | if (!dma_supported(dev, dma_mask)) | |
1289 | return -EIO; | |
1290 | ||
4e8b0cf4 NA |
1291 | *dev->dma_mask = dma_mask; |
1292 | return 0; | |
1293 | } | |
1294 | ||
6a5c7be5 MM |
1295 | static u64 dma_get_required_mask_pSeriesLP(struct device *dev) |
1296 | { | |
1297 | if (!dev->dma_mask) | |
1298 | return 0; | |
1299 | ||
1300 | if (!disable_ddw && dev_is_pci(dev)) { | |
1301 | struct pci_dev *pdev = to_pci_dev(dev); | |
1302 | struct device_node *dn; | |
1303 | ||
1304 | dn = pci_device_to_OF_node(pdev); | |
1305 | ||
1306 | /* search upwards for ibm,dma-window */ | |
b348aa65 | 1307 | for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group; |
6a5c7be5 MM |
1308 | dn = dn->parent) |
1309 | if (of_get_property(dn, "ibm,dma-window", NULL)) | |
1310 | break; | |
1311 | /* if there is a ibm,ddw-applicable property require 64 bits */ | |
1312 | if (dn && PCI_DN(dn) && | |
1313 | of_get_property(dn, "ibm,ddw-applicable", NULL)) | |
1314 | return DMA_BIT_MASK(64); | |
1315 | } | |
1316 | ||
d24f9c69 | 1317 | return dma_iommu_ops.get_required_mask(dev); |
6a5c7be5 MM |
1318 | } |
1319 | ||
4e8b0cf4 NA |
1320 | static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action, |
1321 | void *data) | |
1322 | { | |
1323 | struct direct_window *window; | |
1324 | struct memory_notify *arg = data; | |
1325 | int ret = 0; | |
1326 | ||
1327 | switch (action) { | |
1328 | case MEM_GOING_ONLINE: | |
1329 | spin_lock(&direct_window_list_lock); | |
1330 | list_for_each_entry(window, &direct_window_list, list) { | |
1331 | ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn, | |
1332 | arg->nr_pages, window->prop); | |
1333 | /* XXX log error */ | |
1334 | } | |
1335 | spin_unlock(&direct_window_list_lock); | |
1336 | break; | |
1337 | case MEM_CANCEL_ONLINE: | |
1338 | case MEM_OFFLINE: | |
1339 | spin_lock(&direct_window_list_lock); | |
1340 | list_for_each_entry(window, &direct_window_list, list) { | |
1341 | ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn, | |
1342 | arg->nr_pages, window->prop); | |
1343 | /* XXX log error */ | |
1344 | } | |
1345 | spin_unlock(&direct_window_list_lock); | |
1346 | break; | |
1347 | default: | |
1348 | break; | |
1349 | } | |
1350 | if (ret && action != MEM_CANCEL_ONLINE) | |
1351 | return NOTIFY_BAD; | |
1352 | ||
1353 | return NOTIFY_OK; | |
1354 | } | |
1355 | ||
1356 | static struct notifier_block iommu_mem_nb = { | |
1357 | .notifier_call = iommu_mem_notifier, | |
1358 | }; | |
1359 | ||
f5242e5a | 1360 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data) |
bed59275 SR |
1361 | { |
1362 | int err = NOTIFY_OK; | |
f5242e5a GL |
1363 | struct of_reconfig_data *rd = data; |
1364 | struct device_node *np = rd->dn; | |
bed59275 | 1365 | struct pci_dn *pci = PCI_DN(np); |
4e8b0cf4 | 1366 | struct direct_window *window; |
bed59275 SR |
1367 | |
1368 | switch (action) { | |
1cf3d8b3 | 1369 | case OF_RECONFIG_DETACH_NODE: |
5efbabe0 GS |
1370 | /* |
1371 | * Removing the property will invoke the reconfig | |
1372 | * notifier again, which causes dead-lock on the | |
1373 | * read-write semaphore of the notifier chain. So | |
1374 | * we have to remove the property when releasing | |
1375 | * the device node. | |
1376 | */ | |
1377 | remove_ddw(np, false); | |
b348aa65 AK |
1378 | if (pci && pci->table_group) |
1379 | iommu_pseries_free_group(pci->table_group, | |
ac9a5889 | 1380 | np->full_name); |
4e8b0cf4 NA |
1381 | |
1382 | spin_lock(&direct_window_list_lock); | |
1383 | list_for_each_entry(window, &direct_window_list, list) { | |
1384 | if (window->device == np) { | |
1385 | list_del(&window->list); | |
1386 | kfree(window); | |
1387 | break; | |
1388 | } | |
1389 | } | |
1390 | spin_unlock(&direct_window_list_lock); | |
bed59275 SR |
1391 | break; |
1392 | default: | |
1393 | err = NOTIFY_DONE; | |
1394 | break; | |
1395 | } | |
1396 | return err; | |
1397 | } | |
1398 | ||
1399 | static struct notifier_block iommu_reconfig_nb = { | |
1400 | .notifier_call = iommu_reconfig_notifier, | |
1401 | }; | |
1da177e4 | 1402 | |
1da177e4 LT |
1403 | /* These are called very early. */ |
1404 | void iommu_init_early_pSeries(void) | |
1405 | { | |
a8daac8a | 1406 | if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) |
1da177e4 | 1407 | return; |
1da177e4 | 1408 | |
57cfb814 | 1409 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
38ae9ec4 DA |
1410 | pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
1411 | pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | |
4e8b0cf4 | 1412 | ppc_md.dma_set_mask = dma_set_mask_pSeriesLP; |
6a5c7be5 | 1413 | ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP; |
1da177e4 | 1414 | } else { |
38ae9ec4 DA |
1415 | pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries; |
1416 | pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries; | |
1da177e4 LT |
1417 | } |
1418 | ||
1419 | ||
1cf3d8b3 | 1420 | of_reconfig_notifier_register(&iommu_reconfig_nb); |
4e8b0cf4 | 1421 | register_memory_notifier(&iommu_mem_nb); |
1da177e4 | 1422 | |
98747770 | 1423 | set_pci_dma_ops(&dma_iommu_ops); |
1da177e4 LT |
1424 | } |
1425 | ||
4e89a2d8 WS |
1426 | static int __init disable_multitce(char *str) |
1427 | { | |
1428 | if (strcmp(str, "off") == 0 && | |
1429 | firmware_has_feature(FW_FEATURE_LPAR) && | |
1430 | firmware_has_feature(FW_FEATURE_MULTITCE)) { | |
1431 | printk(KERN_INFO "Disabling MULTITCE firmware feature\n"); | |
4e89a2d8 WS |
1432 | powerpc_firmware_features &= ~FW_FEATURE_MULTITCE; |
1433 | } | |
1434 | return 1; | |
1435 | } | |
1436 | ||
1437 | __setup("multitce=", disable_multitce); | |
4ad04e59 NA |
1438 | |
1439 | machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init); |