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1da177e4 1/*
033ef338 2 * 64-bit pSeries and RS/6000 setup code.
1da177e4
LT
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified by PPC64 Team, IBM Corp
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15/*
16 * bootup setup stuff..
17 */
18
19#undef DEBUG
20
62d60e9f 21#include <linux/cpu.h>
1da177e4
LT
22#include <linux/errno.h>
23#include <linux/sched.h>
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/stddef.h>
27#include <linux/unistd.h>
28#include <linux/slab.h>
29#include <linux/user.h>
30#include <linux/a.out.h>
31#include <linux/tty.h>
32#include <linux/major.h>
33#include <linux/interrupt.h>
34#include <linux/reboot.h>
35#include <linux/init.h>
36#include <linux/ioport.h>
37#include <linux/console.h>
38#include <linux/pci.h>
cebb2b15 39#include <linux/utsname.h>
1da177e4
LT
40#include <linux/adb.h>
41#include <linux/module.h>
42#include <linux/delay.h>
43#include <linux/irq.h>
44#include <linux/seq_file.h>
45#include <linux/root_dev.h>
46
47#include <asm/mmu.h>
48#include <asm/processor.h>
49#include <asm/io.h>
50#include <asm/pgtable.h>
51#include <asm/prom.h>
52#include <asm/rtas.h>
53#include <asm/pci-bridge.h>
54#include <asm/iommu.h>
55#include <asm/dma.h>
56#include <asm/machdep.h>
57#include <asm/irq.h>
3d1229d6 58#include <asm/kexec.h>
1da177e4
LT
59#include <asm/time.h>
60#include <asm/nvram.h>
007e8f51 61#include "xics.h"
180a3362 62#include <asm/pmc.h>
bbeb3f4c 63#include <asm/mpic.h>
d387899f 64#include <asm/ppc-pci.h>
69a80d3f
PM
65#include <asm/i8259.h>
66#include <asm/udbg.h>
2249ca9d 67#include <asm/smp.h>
1da177e4 68
a1218720 69#include "plpar_wrappers.h"
c902be71 70#include "ras.h"
1965746b 71#include "firmware.h"
a1218720 72
1da177e4
LT
73#ifdef DEBUG
74#define DBG(fmt...) udbg_printf(fmt)
75#else
76#define DBG(fmt...)
77#endif
78
0ebfff14
BH
79/* move those away to a .h */
80extern void smp_init_pseries_mpic(void);
81extern void smp_init_pseries_xics(void);
1da177e4 82extern void find_udbg_vterm(void);
1da177e4
LT
83
84int fwnmi_active; /* TRUE if an FWNMI handler is present */
85
fbd7740f
PM
86static void pseries_shared_idle_sleep(void);
87static void pseries_dedicated_idle_sleep(void);
62d60e9f 88
0ebfff14 89static struct device_node *pSeries_mpic_node;
1da177e4 90
8446196a 91static void pSeries_show_cpuinfo(struct seq_file *m)
1da177e4
LT
92{
93 struct device_node *root;
94 const char *model = "";
95
96 root = of_find_node_by_path("/");
97 if (root)
98 model = get_property(root, "model", NULL);
99 seq_printf(m, "machine\t\t: CHRP %s\n", model);
100 of_node_put(root);
101}
102
103/* Initialize firmware assisted non-maskable interrupts if
104 * the firmware supports this feature.
1da177e4
LT
105 */
106static void __init fwnmi_init(void)
107{
8c4f1f29
ME
108 unsigned long system_reset_addr, machine_check_addr;
109
1da177e4
LT
110 int ibm_nmi_register = rtas_token("ibm,nmi-register");
111 if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE)
112 return;
8c4f1f29
ME
113
114 /* If the kernel's not linked at zero we point the firmware at low
115 * addresses anyway, and use a trampoline to get to the real code. */
116 system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START;
117 machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START;
118
119 if (0 == rtas_call(ibm_nmi_register, 2, 1, NULL, system_reset_addr,
120 machine_check_addr))
1da177e4
LT
121 fwnmi_active = 1;
122}
123
0ebfff14 124void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc,
b9e5b4e6
BH
125 struct pt_regs *regs)
126{
0ebfff14
BH
127 unsigned int cascade_irq = i8259_irq(regs);
128 if (cascade_irq != NO_IRQ)
b9e5b4e6 129 generic_handle_irq(cascade_irq, regs);
0ebfff14 130 desc->chip->eoi(irq);
b9e5b4e6
BH
131}
132
0ebfff14 133static void __init pseries_mpic_init_IRQ(void)
1da177e4 134{
0ebfff14 135 struct device_node *np, *old, *cascade = NULL;
954a46e2 136 const unsigned int *addrp;
f9bd170a 137 unsigned long intack = 0;
954a46e2 138 const unsigned int *opprop;
1da177e4 139 unsigned long openpic_addr = 0;
0ebfff14
BH
140 unsigned int cascade_irq;
141 int naddr, n, i, opplen;
142 struct mpic *mpic;
1da177e4 143
0ebfff14
BH
144 np = of_find_node_by_path("/");
145 naddr = prom_n_addr_cells(np);
954a46e2 146 opprop = get_property(np, "platform-open-pic", &opplen);
1da177e4 147 if (opprop != 0) {
0ebfff14 148 openpic_addr = of_read_number(opprop, naddr);
1da177e4
LT
149 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
150 }
0ebfff14 151 of_node_put(np);
1da177e4
LT
152
153 BUG_ON(openpic_addr == 0);
154
1da177e4 155 /* Setup the openpic driver */
0ebfff14
BH
156 mpic = mpic_alloc(pSeries_mpic_node, openpic_addr,
157 MPIC_PRIMARY,
158 16, 250, /* isu size, irq count */
159 " MPIC ");
160 BUG_ON(mpic == NULL);
161
162 /* Add ISUs */
163 opplen /= sizeof(u32);
164 for (n = 0, i = naddr; i < opplen; i += naddr, n++) {
165 unsigned long isuaddr = of_read_number(opprop + i, naddr);
166 mpic_assign_isu(mpic, n, isuaddr);
167 }
168
169 /* All ISUs are setup, complete initialization */
170 mpic_init(mpic);
171
172 /* Look for cascade */
173 for_each_node_by_type(np, "interrupt-controller")
174 if (device_is_compatible(np, "chrp,iic")) {
175 cascade = np;
176 break;
177 }
178 if (cascade == NULL)
179 return;
180
181 cascade_irq = irq_of_parse_and_map(cascade, 0);
182 if (cascade == NO_IRQ) {
183 printk(KERN_ERR "xics: failed to map cascade interrupt");
184 return;
185 }
186
187 /* Check ACK type */
188 for (old = of_node_get(cascade); old != NULL ; old = np) {
189 np = of_get_parent(old);
190 of_node_put(old);
191 if (np == NULL)
192 break;
193 if (strcmp(np->name, "pci") != 0)
194 continue;
954a46e2 195 addrp = get_property(np, "8259-interrupt-acknowledge",
0ebfff14
BH
196 NULL);
197 if (addrp == NULL)
198 continue;
199 naddr = prom_n_addr_cells(np);
200 intack = addrp[naddr-1];
201 if (naddr > 1)
202 intack |= ((unsigned long)addrp[naddr-2]) << 32;
203 }
204 if (intack)
205 printk(KERN_DEBUG "mpic: PCI 8259 intack at 0x%016lx\n",
206 intack);
207 i8259_init(cascade, intack);
208 of_node_put(cascade);
209 set_irq_chained_handler(cascade_irq, pseries_8259_cascade);
1da177e4
LT
210}
211
180a3362
ME
212static void pseries_lpar_enable_pmcs(void)
213{
214 unsigned long set, reset;
215
180a3362
ME
216 set = 1UL << 63;
217 reset = 0;
218 plpar_hcall_norets(H_PERFMON, set, reset);
219
220 /* instruct hypervisor to maintain PMCs */
221 if (firmware_has_feature(FW_FEATURE_SPLPAR))
3356bb9f 222 get_lppaca()->pmcregs_in_use = 1;
180a3362
ME
223}
224
0ebfff14 225#ifdef CONFIG_KEXEC
f50d4cfc 226static void pseries_kexec_cpu_down(int crash_shutdown, int secondary)
0ebfff14
BH
227{
228 /* Don't risk a hypervisor call if we're crashing */
229 if (firmware_has_feature(FW_FEATURE_SPLPAR) && !crash_shutdown) {
2f6093c8 230 unsigned long addr;
0ebfff14 231
2f6093c8
MN
232 addr = __pa(get_slb_shadow());
233 if (unregister_slb_shadow(hard_smp_processor_id(), addr))
234 printk("SLB shadow buffer deregistration of "
235 "cpu %u (hw_cpu_id %d) failed\n",
236 smp_processor_id(),
237 hard_smp_processor_id());
238
239 addr = __pa(get_lppaca());
240 if (unregister_vpa(hard_smp_processor_id(), addr)) {
0ebfff14
BH
241 printk("VPA deregistration of cpu %u (hw_cpu_id %d) "
242 "failed\n", smp_processor_id(),
243 hard_smp_processor_id());
244 }
245 }
f50d4cfc
ME
246}
247
248static void pseries_kexec_cpu_down_mpic(int crash_shutdown, int secondary)
249{
250 pseries_kexec_cpu_down(crash_shutdown, secondary);
251 mpic_teardown_this_cpu(secondary);
252}
253
254static void pseries_kexec_cpu_down_xics(int crash_shutdown, int secondary)
255{
256 pseries_kexec_cpu_down(crash_shutdown, secondary);
0ebfff14
BH
257 xics_teardown_cpu(secondary);
258}
259#endif /* CONFIG_KEXEC */
260
261static void __init pseries_discover_pic(void)
262{
263 struct device_node *np;
954a46e2 264 const char *typep;
0ebfff14
BH
265
266 for (np = NULL; (np = of_find_node_by_name(np,
267 "interrupt-controller"));) {
954a46e2 268 typep = get_property(np, "compatible", NULL);
0ebfff14
BH
269 if (strstr(typep, "open-pic")) {
270 pSeries_mpic_node = of_node_get(np);
271 ppc_md.init_IRQ = pseries_mpic_init_IRQ;
272 ppc_md.get_irq = mpic_get_irq;
273#ifdef CONFIG_KEXEC
274 ppc_md.kexec_cpu_down = pseries_kexec_cpu_down_mpic;
275#endif
1da177e4 276#ifdef CONFIG_SMP
0ebfff14 277 smp_init_pseries_mpic();
1da177e4 278#endif
0ebfff14
BH
279 return;
280 } else if (strstr(typep, "ppc-xicp")) {
281 ppc_md.init_IRQ = xics_init_IRQ;
282#ifdef CONFIG_KEXEC
283 ppc_md.kexec_cpu_down = pseries_kexec_cpu_down_xics;
284#endif
285#ifdef CONFIG_SMP
286 smp_init_pseries_xics();
287#endif
288 return;
289 }
290 }
291 printk(KERN_ERR "pSeries_discover_pic: failed to recognize"
292 " interrupt-controller\n");
293}
294
295static void __init pSeries_setup_arch(void)
296{
297 /* Discover PIC type and setup ppc_md accordingly */
298 pseries_discover_pic();
299
1da177e4
LT
300 /* openpic global configuration register (64-bit format). */
301 /* openpic Interrupt Source Unit pointer (64-bit format). */
302 /* python0 facility area (mmio) (64-bit format) REAL address. */
303
304 /* init to some ~sane value until calibrate_delay() runs */
305 loops_per_jiffy = 50000000;
306
307 if (ROOT_DEV == 0) {
308 printk("No ramdisk, default root is /dev/sda2\n");
309 ROOT_DEV = Root_SDA2;
310 }
311
312 fwnmi_init();
313
314 /* Find and initialize PCI host bridges */
315 init_pci_config_tokens();
1da177e4 316 find_and_init_phbs();
0160f53e 317 eeh_init();
1da177e4 318
1da177e4
LT
319 pSeries_nvram_init();
320
62d60e9f 321 /* Choose an idle loop */
1ababe11 322 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
8d15a3e5 323 vpa_init(boot_cpuid);
3356bb9f 324 if (get_lppaca()->shared_proc) {
4baaf0cf 325 printk(KERN_DEBUG "Using shared processor idle loop\n");
fbd7740f 326 ppc_md.power_save = pseries_shared_idle_sleep;
62d60e9f 327 } else {
4baaf0cf 328 printk(KERN_DEBUG "Using dedicated idle loop\n");
fbd7740f 329 ppc_md.power_save = pseries_dedicated_idle_sleep;
62d60e9f
ME
330 }
331 } else {
4baaf0cf 332 printk(KERN_DEBUG "Using default idle loop\n");
62d60e9f 333 }
180a3362 334
57cfb814 335 if (firmware_has_feature(FW_FEATURE_LPAR))
180a3362
ME
336 ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
337 else
338 ppc_md.enable_pmcs = power4_enable_pmcs;
1da177e4
LT
339}
340
341static int __init pSeries_init_panel(void)
342{
343 /* Manually leave the kernel version on the panel. */
344 ppc_md.progress("Linux ppc64\n", 0);
3de620e8 345 ppc_md.progress(system_utsname.release, 0);
1da177e4
LT
346
347 return 0;
348}
349arch_initcall(pSeries_init_panel);
350
1da177e4
LT
351static void pSeries_mach_cpu_die(void)
352{
353 local_irq_disable();
354 idle_task_exit();
b9e5b4e6 355 xics_teardown_cpu(0);
1da177e4
LT
356 rtas_stop_self();
357 /* Should never get here... */
358 BUG();
359 for(;;);
360}
361
cab0af98
ME
362static int pseries_set_dabr(unsigned long dabr)
363{
76032de8 364 return plpar_hcall_norets(H_SET_DABR, dabr);
cab0af98
ME
365}
366
76032de8
ME
367static int pseries_set_xdabr(unsigned long dabr)
368{
369 /* We want to catch accesses from kernel and userspace */
370 return plpar_hcall_norets(H_SET_XDABR, dabr,
371 H_DABRX_KERNEL | H_DABRX_USER);
372}
1da177e4
LT
373
374/*
375 * Early initialization. Relocation is on but do not reference unbolted pages
376 */
377static void __init pSeries_init_early(void)
378{
1da177e4
LT
379 DBG(" -> pSeries_init_early()\n");
380
381 fw_feature_init();
1da177e4 382
57cfb814 383 if (firmware_has_feature(FW_FEATURE_LPAR))
1da177e4 384 find_udbg_vterm();
1da177e4 385
76032de8 386 if (firmware_has_feature(FW_FEATURE_DABR))
cab0af98 387 ppc_md.set_dabr = pseries_set_dabr;
76032de8
ME
388 else if (firmware_has_feature(FW_FEATURE_XDABR))
389 ppc_md.set_dabr = pseries_set_xdabr;
1da177e4
LT
390
391 iommu_init_early_pSeries();
392
1da177e4
LT
393 DBG(" <- pSeries_init_early()\n");
394}
395
396
1da177e4
LT
397static int pSeries_check_legacy_ioport(unsigned int baseport)
398{
399 struct device_node *np;
400
401#define I8042_DATA_REG 0x60
402#define FDC_BASE 0x3f0
403
404
405 switch(baseport) {
406 case I8042_DATA_REG:
407 np = of_find_node_by_type(NULL, "8042");
408 if (np == NULL)
409 return -ENODEV;
410 of_node_put(np);
411 break;
412 case FDC_BASE:
413 np = of_find_node_by_type(NULL, "fdc");
414 if (np == NULL)
415 return -ENODEV;
416 of_node_put(np);
417 break;
30cbc222
OH
418 case PARALLEL_BASE:
419 np = of_find_node_by_type(NULL, "parallel");
420 if (np == NULL)
421 return -ENODEV;
422 of_node_put(np);
423 break;
1da177e4
LT
424 }
425 return 0;
426}
427
428/*
429 * Called very early, MMU is off, device-tree isn't unflattened
430 */
1da177e4 431
e8222502
BH
432static int __init pSeries_probe_hypertas(unsigned long node,
433 const char *uname, int depth,
434 void *data)
1da177e4 435{
e8222502
BH
436 if (depth != 1 ||
437 (strcmp(uname, "rtas") != 0 && strcmp(uname, "rtas@0") != 0))
438 return 0;
439
440 if (of_get_flat_dt_prop(node, "ibm,hypertas-functions", NULL) != NULL)
441 powerpc_firmware_features |= FW_FEATURE_LPAR;
442
7d0daae4
ME
443 if (firmware_has_feature(FW_FEATURE_LPAR))
444 hpte_init_lpar();
445 else
446 hpte_init_native();
447
e8222502
BH
448 return 1;
449}
450
451static int __init pSeries_probe(void)
452{
133dda1e 453 unsigned long root = of_get_flat_dt_root();
e8222502
BH
454 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
455 "device_type", NULL);
456 if (dtype == NULL)
457 return 0;
458 if (strcmp(dtype, "chrp"))
1da177e4
LT
459 return 0;
460
133dda1e
AB
461 /* Cell blades firmware claims to be chrp while it's not. Until this
462 * is fixed, we need to avoid those here.
463 */
464 if (of_flat_dt_is_compatible(root, "IBM,CPBW-1.0") ||
465 of_flat_dt_is_compatible(root, "IBM,CBEA"))
466 return 0;
467
e8222502 468 DBG("pSeries detected, looking for LPAR capability...\n");
1da177e4 469
e8222502
BH
470 /* Now try to figure out if we are running on LPAR */
471 of_scan_flat_dt(pSeries_probe_hypertas, NULL);
472
473 DBG("Machine is%s LPAR !\n",
474 (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not");
57cfb814 475
1da177e4
LT
476 return 1;
477}
478
e8222502 479
c66d5dd6
ME
480DECLARE_PER_CPU(unsigned long, smt_snooze_delay);
481
fbd7740f 482static void pseries_dedicated_idle_sleep(void)
143a1dec 483{
050a0938 484 unsigned int cpu = smp_processor_id();
c66d5dd6
ME
485 unsigned long start_snooze;
486 unsigned long *smt_snooze_delay = &__get_cpu_var(smt_snooze_delay);
c66d5dd6 487
fbd7740f
PM
488 /*
489 * Indicate to the HV that we are idle. Now would be
490 * a good time to find other work to dispatch.
491 */
492 get_lppaca()->idle = 1;
050a0938 493
fbd7740f
PM
494 /*
495 * We come in with interrupts disabled, and need_resched()
496 * has been checked recently. If we should poll for a little
497 * while, do so.
498 */
499 if (*smt_snooze_delay) {
500 start_snooze = get_tb() +
501 *smt_snooze_delay * tb_ticks_per_usec;
502 local_irq_enable();
503 set_thread_flag(TIF_POLLING_NRFLAG);
050a0938 504
fbd7740f
PM
505 while (get_tb() < start_snooze) {
506 if (need_resched() || cpu_is_offline(cpu))
507 goto out;
508 ppc64_runlatch_off();
509 HMT_low();
510 HMT_very_low();
511 }
512
513 HMT_medium();
514 clear_thread_flag(TIF_POLLING_NRFLAG);
515 smp_mb();
516 local_irq_disable();
517 if (need_resched() || cpu_is_offline(cpu))
518 goto out;
c66d5dd6 519 }
fbd7740f
PM
520
521 /*
9b9b72fe
JM
522 * If not SMT, cede processor. If CPU is running SMT
523 * cede if the other thread is not idle, so that it can
fbd7740f
PM
524 * go single-threaded. If the other thread is idle,
525 * we ask the hypervisor if it has pending work it
526 * wants to do and cede if it does. Otherwise we keep
527 * polling in order to reduce interrupt latency.
528 *
529 * Doing the cede when the other thread is active will
530 * result in this thread going dormant, meaning the other
531 * thread gets to run in single-threaded (ST) mode, which
532 * is slightly faster than SMT mode with this thread at
533 * very low priority. The cede enables interrupts, which
534 * doesn't matter here.
535 */
9b9b72fe
JM
536 if (!cpu_has_feature(CPU_FTR_SMT) || !lppaca[cpu ^ 1].idle
537 || poll_pending() == H_PENDING)
fbd7740f
PM
538 cede_processor();
539
540out:
541 HMT_medium();
542 get_lppaca()->idle = 0;
c66d5dd6
ME
543}
544
fbd7740f 545static void pseries_shared_idle_sleep(void)
c66d5dd6 546{
fbd7740f
PM
547 /*
548 * Indicate to the HV that we are idle. Now would be
549 * a good time to find other work to dispatch.
550 */
551 get_lppaca()->idle = 1;
050a0938 552
fbd7740f
PM
553 /*
554 * Yield the processor to the hypervisor. We return if
555 * an external interrupt occurs (which are driven prior
556 * to returning here) or if a prod occurs from another
557 * processor. When returning here, external interrupts
558 * are enabled.
559 */
560 cede_processor();
050a0938 561
fbd7740f 562 get_lppaca()->idle = 0;
c66d5dd6
ME
563}
564
4267292b
PM
565static int pSeries_pci_probe_mode(struct pci_bus *bus)
566{
57cfb814 567 if (firmware_has_feature(FW_FEATURE_LPAR))
4267292b
PM
568 return PCI_PROBE_DEVTREE;
569 return PCI_PROBE_NORMAL;
570}
571
e8222502
BH
572define_machine(pseries) {
573 .name = "pSeries",
1da177e4
LT
574 .probe = pSeries_probe,
575 .setup_arch = pSeries_setup_arch,
576 .init_early = pSeries_init_early,
0dd194d0 577 .show_cpuinfo = pSeries_show_cpuinfo,
1da177e4
LT
578 .log_error = pSeries_log_error,
579 .pcibios_fixup = pSeries_final_fixup,
4267292b 580 .pci_probe_mode = pSeries_pci_probe_mode,
dad32bbf 581 .irq_bus_setup = pSeries_irq_bus_setup,
f4fcbbe9
PM
582 .restart = rtas_restart,
583 .power_off = rtas_power_off,
584 .halt = rtas_halt,
1da177e4
LT
585 .panic = rtas_os_term,
586 .cpu_die = pSeries_mach_cpu_die,
773bf9c4
AB
587 .get_boot_time = rtas_get_boot_time,
588 .get_rtc_time = rtas_get_rtc_time,
589 .set_rtc_time = rtas_set_rtc_time,
10f7e7c1 590 .calibrate_decr = generic_calibrate_decr,
6566c6f1 591 .progress = rtas_progress,
1da177e4
LT
592 .check_legacy_ioport = pSeries_check_legacy_ioport,
593 .system_reset_exception = pSeries_system_reset_exception,
594 .machine_check_exception = pSeries_machine_check_exception,
c5e24354 595#ifdef CONFIG_KEXEC
3d1229d6
ME
596 .machine_kexec = default_machine_kexec,
597 .machine_kexec_prepare = default_machine_kexec_prepare,
cc532915 598 .machine_crash_shutdown = default_machine_crash_shutdown,
c5e24354 599#endif
1da177e4 600};