[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / sysdev / cpm_common.c

/*
 * Common CPM code
 *
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * Some parts derived from commproc.c/cpm2_common.c, which is:
 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/spinlock.h>
#include <linux/of.h>

#include <asm/udbg.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/rheap.h>
#include <asm/cpm.h>

#include <mm/mmu_decl.h>

#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
#include <linux/of_gpio.h>
#endif

#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc =
	(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;

static void udbg_putc_cpm(char c)
{
	u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);

	if (c == '\n')
		udbg_putc_cpm('\r');

	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
		;

	out_8(txbuf, c);
	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
}

void __init udbg_init_cpm(void)
{
	if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
		setbat(1, 0xf0000000, 0xf0000000, 1024*1024, _PAGE_IO);
#endif
		udbg_putc = udbg_putc_cpm;
	}
}
#endif

static spinlock_t cpm_muram_lock;
static rh_block_t cpm_boot_muram_rh_block[16];
static rh_info_t cpm_muram_info;
static u8 __iomem *muram_vbase;
static phys_addr_t muram_pbase;

/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS	4

int __init cpm_muram_init(void)
{
	struct device_node *np;
	struct resource r;
	u32 zero[OF_MAX_ADDR_CELLS] = {};
	resource_size_t max = 0;
	int i = 0;
	int ret = 0;

	spin_lock_init(&cpm_muram_lock);
	/* initialize the info header */
	rh_init(&cpm_muram_info, 1,
	        sizeof(cpm_boot_muram_rh_block) /
	        sizeof(cpm_boot_muram_rh_block[0]),
	        cpm_boot_muram_rh_block);

	np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
	if (!np) {
		/* try legacy bindings */
		np = of_find_node_by_name(NULL, "data-only");
		if (!np) {
			printk(KERN_ERR "Cannot find CPM muram data node");
			ret = -ENODEV;
			goto out;
		}
	}

	muram_pbase = of_translate_address(np, zero);
	if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
		printk(KERN_ERR "Cannot translate zero through CPM muram node");
		ret = -ENODEV;
		goto out;
	}

	while (of_address_to_resource(np, i++, &r) == 0) {
		if (r.end > max)
			max = r.end;

		rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
		                 r.end - r.start + 1);
	}

	muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
	if (!muram_vbase) {
		printk(KERN_ERR "Cannot map CPM muram");
		ret = -ENOMEM;
	}

out:
	of_node_put(np);
	return ret;
}

/**
 * cpm_muram_alloc - allocate the requested size worth of multi-user ram
 * @size: number of bytes to allocate
 * @align: requested alignment, in bytes
 *
 * This function returns an offset into the muram area.
 * Use cpm_dpram_addr() to get the virtual address of the area.
 * Use cpm_muram_free() to free the allocation.
 */
unsigned long cpm_muram_alloc(unsigned long size, unsigned long align)
{
	unsigned long start;
	unsigned long flags;

	spin_lock_irqsave(&cpm_muram_lock, flags);
	cpm_muram_info.alignment = align;
	start = rh_alloc(&cpm_muram_info, size, "commproc");
	spin_unlock_irqrestore(&cpm_muram_lock, flags);

	return start;
}
EXPORT_SYMBOL(cpm_muram_alloc);

/**
 * cpm_muram_free - free a chunk of multi-user ram
 * @offset: The beginning of the chunk as returned by cpm_muram_alloc().
 */
int cpm_muram_free(unsigned long offset)
{
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&cpm_muram_lock, flags);
	ret = rh_free(&cpm_muram_info, offset);
	spin_unlock_irqrestore(&cpm_muram_lock, flags);

	return ret;
}
EXPORT_SYMBOL(cpm_muram_free);

/**
 * cpm_muram_alloc_fixed - reserve a specific region of multi-user ram
 * @offset: the offset into the muram area to reserve
 * @size: the number of bytes to reserve
 *
 * This function returns "start" on success, -ENOMEM on failure.
 * Use cpm_dpram_addr() to get the virtual address of the area.
 * Use cpm_muram_free() to free the allocation.
 */
unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
{
	unsigned long start;
	unsigned long flags;

	spin_lock_irqsave(&cpm_muram_lock, flags);
	cpm_muram_info.alignment = 1;
	start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc");
	spin_unlock_irqrestore(&cpm_muram_lock, flags);

	return start;
}
EXPORT_SYMBOL(cpm_muram_alloc_fixed);

/**
 * cpm_muram_addr - turn a muram offset into a virtual address
 * @offset: muram offset to convert
 */
void __iomem *cpm_muram_addr(unsigned long offset)
{
	return muram_vbase + offset;
}
EXPORT_SYMBOL(cpm_muram_addr);

unsigned long cpm_muram_offset(void __iomem *addr)
{
	return addr - (void __iomem *)muram_vbase;
}
EXPORT_SYMBOL(cpm_muram_offset);

/**
 * cpm_muram_dma - turn a muram virtual address into a DMA address
 * @offset: virtual address from cpm_muram_addr() to convert
 */
dma_addr_t cpm_muram_dma(void __iomem *addr)
{
	return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
}
EXPORT_SYMBOL(cpm_muram_dma);

#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)

struct cpm2_ioports {
	u32 dir, par, sor, odr, dat;
	u32 res[3];
};

struct cpm2_gpio32_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;
};

static inline struct cpm2_gpio32_chip *
to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
{
	return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
}

static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;

	cpm2_gc->cpdata = in_be32(&iop->dat);
}

static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	u32 pin_mask;

	pin_mask = 1 << (31 - gpio);

	return !!(in_be32(&iop->dat) & pin_mask);
}

static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	if (value)
		cpm2_gc->cpdata |= pin_mask;
	else
		cpm2_gc->cpdata &= ~pin_mask;

	out_be32(&iop->dat, cpm2_gc->cpdata);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
}

static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	u32 pin_mask;

	pin_mask = 1 << (31 - gpio);

	setbits32(&iop->dir, pin_mask);

	cpm2_gpio32_set(gc, gpio, val);

	return 0;
}

static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	u32 pin_mask;

	pin_mask = 1 << (31 - gpio);

	clrbits32(&iop->dir, pin_mask);

	return 0;
}

int cpm2_gpiochip_add32(struct device_node *np)
{
	struct cpm2_gpio32_chip *cpm2_gc;
	struct of_mm_gpio_chip *mm_gc;
	struct of_gpio_chip *of_gc;
	struct gpio_chip *gc;

	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
	if (!cpm2_gc)
		return -ENOMEM;

	spin_lock_init(&cpm2_gc->lock);

	mm_gc = &cpm2_gc->mm_gc;
	of_gc = &mm_gc->of_gc;
	gc = &of_gc->gc;

	mm_gc->save_regs = cpm2_gpio32_save_regs;
	of_gc->gpio_cells = 2;
	gc->ngpio = 32;
	gc->direction_input = cpm2_gpio32_dir_in;
	gc->direction_output = cpm2_gpio32_dir_out;
	gc->get = cpm2_gpio32_get;
	gc->set = cpm2_gpio32_set;

	return of_mm_gpiochip_add(np, mm_gc);
}
#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
Commit	Line	Data
c374e00e SW	1	/*
	2	* Common CPM code
	3	*
	4	* Author: Scott Wood <scottwood@freescale.com>
	5	*
	6	* Copyright 2007 Freescale Semiconductor, Inc.
	7	*
15f8c604 SW	8	* Some parts derived from commproc.c/cpm2_common.c, which is:
	9	* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
	10	* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
	11	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	12	* 2006 (c) MontaVista Software, Inc.
	13	* Vitaly Bordug <vbordug@ru.mvista.com>
	14	*
c374e00e SW	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of version 2 of the GNU General Public License as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/init.h>
15f8c604	21	#include <linux/of_device.h>
e193325e LP	22	#include <linux/spinlock.h>
e193325e LP	23	#include <linux/of.h>
15f8c604	24
c374e00e SW	25	#include <asm/udbg.h>
	26	#include <asm/io.h>
	27	#include <asm/system.h>
15f8c604 SW	28	#include <asm/rheap.h>
	29	#include <asm/cpm.h>
	30
c374e00e SW	31	#include <mm/mmu_decl.h>
c374e00e SW	32
e193325e LP	33	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_8xx_GPIO)
	34	#include <linux/of_gpio.h>
	35	#endif
	36
c374e00e SW	37	#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
	38	static u32 __iomem *cpm_udbg_txdesc =
	39	(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
	40
	41	static void udbg_putc_cpm(char c)
	42	{
	43	u8 __iomem txbuf = (u8 __iomem __force )in_be32(&cpm_udbg_txdesc[1]);
	44
	45	if (c == '\n')
5e82eb33	46	udbg_putc_cpm('\r');
c374e00e SW	47
	48	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
	49	;
	50
	51	out_8(txbuf, c);
	52	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
	53	}
	54
	55	void __init udbg_init_cpm(void)
	56	{
	57	if (cpm_udbg_txdesc) {
	58	#ifdef CONFIG_CPM2
	59	setbat(1, 0xf0000000, 0xf0000000, 1024*1024, _PAGE_IO);
	60	#endif
	61	udbg_putc = udbg_putc_cpm;
	62	}
	63	}
	64	#endif
15f8c604	65
15f8c604 SW	66	static spinlock_t cpm_muram_lock;
	67	static rh_block_t cpm_boot_muram_rh_block[16];
	68	static rh_info_t cpm_muram_info;
	69	static u8 __iomem *muram_vbase;
	70	static phys_addr_t muram_pbase;
	71
	72	/* Max address size we deal with */
	73	#define OF_MAX_ADDR_CELLS 4
	74
	75	int __init cpm_muram_init(void)
	76	{
	77	struct device_node *np;
	78	struct resource r;
	79	u32 zero[OF_MAX_ADDR_CELLS] = {};
	80	resource_size_t max = 0;
	81	int i = 0;
	82	int ret = 0;
	83
15f8c604 SW	84	spin_lock_init(&cpm_muram_lock);
	85	/* initialize the info header */
	86	rh_init(&cpm_muram_info, 1,
	87	sizeof(cpm_boot_muram_rh_block) /
	88	sizeof(cpm_boot_muram_rh_block[0]),
	89	cpm_boot_muram_rh_block);
	90
	91	np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
	92	if (!np) {
5093bb96 AV	93	/* try legacy bindings */
	94	np = of_find_node_by_name(NULL, "data-only");
	95	if (!np) {
	96	printk(KERN_ERR "Cannot find CPM muram data node");
	97	ret = -ENODEV;
	98	goto out;
	99	}
15f8c604 SW	100	}
	101
	102	muram_pbase = of_translate_address(np, zero);
	103	if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
	104	printk(KERN_ERR "Cannot translate zero through CPM muram node");
	105	ret = -ENODEV;
	106	goto out;
	107	}
	108
	109	while (of_address_to_resource(np, i++, &r) == 0) {
	110	if (r.end > max)
	111	max = r.end;
	112
	113	rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
	114	r.end - r.start + 1);
	115	}
	116
	117	muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
	118	if (!muram_vbase) {
	119	printk(KERN_ERR "Cannot map CPM muram");
	120	ret = -ENOMEM;
	121	}
	122
	123	out:
	124	of_node_put(np);
	125	return ret;
	126	}
	127
	128	/**
	129	* cpm_muram_alloc - allocate the requested size worth of multi-user ram
	130	* @size: number of bytes to allocate
	131	* @align: requested alignment, in bytes
	132	*
	133	* This function returns an offset into the muram area.
	134	* Use cpm_dpram_addr() to get the virtual address of the area.
	135	* Use cpm_muram_free() to free the allocation.
	136	*/
	137	unsigned long cpm_muram_alloc(unsigned long size, unsigned long align)
	138	{
	139	unsigned long start;
	140	unsigned long flags;
	141
	142	spin_lock_irqsave(&cpm_muram_lock, flags);
	143	cpm_muram_info.alignment = align;
	144	start = rh_alloc(&cpm_muram_info, size, "commproc");
	145	spin_unlock_irqrestore(&cpm_muram_lock, flags);
	146
	147	return start;
	148	}
	149	EXPORT_SYMBOL(cpm_muram_alloc);
	150
	151	/**
	152	* cpm_muram_free - free a chunk of multi-user ram
	153	* @offset: The beginning of the chunk as returned by cpm_muram_alloc().
	154	*/
	155	int cpm_muram_free(unsigned long offset)
	156	{
	157	int ret;
	158	unsigned long flags;
	159
	160	spin_lock_irqsave(&cpm_muram_lock, flags);
	161	ret = rh_free(&cpm_muram_info, offset);
	162	spin_unlock_irqrestore(&cpm_muram_lock, flags);
	163
164	return ret;
165	}
166	EXPORT_SYMBOL(cpm_muram_free);
167
168	/**
169	* cpm_muram_alloc_fixed - reserve a specific region of multi-user ram
170	* @offset: the offset into the muram area to reserve
171	* @size: the number of bytes to reserve
172	*
173	* This function returns "start" on success, -ENOMEM on failure.
174	* Use cpm_dpram_addr() to get the virtual address of the area.
175	* Use cpm_muram_free() to free the allocation.
176	*/
177	unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
178	{
179	unsigned long start;
180	unsigned long flags;
181
182	spin_lock_irqsave(&cpm_muram_lock, flags);
183	cpm_muram_info.alignment = 1;
184	start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc");
185	spin_unlock_irqrestore(&cpm_muram_lock, flags);
186
187	return start;
188	}
189	EXPORT_SYMBOL(cpm_muram_alloc_fixed);
190
191	/**
192	* cpm_muram_addr - turn a muram offset into a virtual address
193	* @offset: muram offset to convert
194	*/
195	void __iomem *cpm_muram_addr(unsigned long offset)
196	{
197	return muram_vbase + offset;
198	}
199	EXPORT_SYMBOL(cpm_muram_addr);
200
5093bb96 AV	201	unsigned long cpm_muram_offset(void __iomem *addr)
	202	{
	203	return addr - (void __iomem *)muram_vbase;
	204	}
	205	EXPORT_SYMBOL(cpm_muram_offset);
	206
15f8c604	207	/**
4c011b1f	208	* cpm_muram_dma - turn a muram virtual address into a DMA address
15f8c604 SW	209	* @offset: virtual address from cpm_muram_addr() to convert
	210	*/
	211	dma_addr_t cpm_muram_dma(void __iomem *addr)
	212	{
	213	return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
	214	}
	215	EXPORT_SYMBOL(cpm_muram_dma);
e193325e LP	216
	217	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_8xx_GPIO)
	218
	219	struct cpm2_ioports {
	220	u32 dir, par, sor, odr, dat;
	221	u32 res[3];
	222	};
	223
	224	struct cpm2_gpio32_chip {
	225	struct of_mm_gpio_chip mm_gc;
	226	spinlock_t lock;
	227
	228	/* shadowed data register to clear/set bits safely */
	229	u32 cpdata;
	230	};
	231
	232	static inline struct cpm2_gpio32_chip *
	233	to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
	234	{
	235	return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
	236	}
	237
	238	static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
	239	{
	240	struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
	241	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	242
	243	cpm2_gc->cpdata = in_be32(&iop->dat);
	244	}
	245
	246	static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
	247	{
	248	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	249	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	250	u32 pin_mask;
	251
	252	pin_mask = 1 << (31 - gpio);
	253
	254	return !!(in_be32(&iop->dat) & pin_mask);
	255	}
	256
	257	static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
	258	{
	259	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	260	struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
	261	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	262	unsigned long flags;
	263	u32 pin_mask = 1 << (31 - gpio);
	264
	265	spin_lock_irqsave(&cpm2_gc->lock, flags);
	266
	267	if (value)
	268	cpm2_gc->cpdata \|= pin_mask;
	269	else
	270	cpm2_gc->cpdata &= ~pin_mask;
	271
	272	out_be32(&iop->dat, cpm2_gc->cpdata);
	273
	274	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
	275	}
	276
	277	static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	278	{
	279	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
280	struct cpm2_ioports __iomem *iop = mm_gc->regs;
281	u32 pin_mask;
282
283	pin_mask = 1 << (31 - gpio);
284
285	setbits32(&iop->dir, pin_mask);
286
287	cpm2_gpio32_set(gc, gpio, val);
288
289	return 0;
290	}
291
292	static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
293	{
294	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
295	struct cpm2_ioports __iomem *iop = mm_gc->regs;
296	u32 pin_mask;
297
298	pin_mask = 1 << (31 - gpio);
299
300	clrbits32(&iop->dir, pin_mask);
301
302	return 0;
303	}
304
305	int cpm2_gpiochip_add32(struct device_node *np)
306	{
307	struct cpm2_gpio32_chip *cpm2_gc;
308	struct of_mm_gpio_chip *mm_gc;
309	struct of_gpio_chip *of_gc;
310	struct gpio_chip *gc;
311
312	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
313	if (!cpm2_gc)
314	return -ENOMEM;
315
316	spin_lock_init(&cpm2_gc->lock);
317
318	mm_gc = &cpm2_gc->mm_gc;
319	of_gc = &mm_gc->of_gc;
320	gc = &of_gc->gc;
321
322	mm_gc->save_regs = cpm2_gpio32_save_regs;
323	of_gc->gpio_cells = 2;
324	gc->ngpio = 32;
325	gc->direction_input = cpm2_gpio32_dir_in;
326	gc->direction_output = cpm2_gpio32_dir_out;
327	gc->get = cpm2_gpio32_get;
328	gc->set = cpm2_gpio32_set;
329
330	return of_mm_gpiochip_add(np, mm_gc);
331	}
332	#endif /* CONFIG_CPM2 \|\| CONFIG_8xx_GPIO */