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34e36c15 JJ |
1 | /* |
2 | * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved. | |
3 | * | |
4 | * Author: Tony Li <tony.li@freescale.com> | |
5 | * Jason Jin <Jason.jin@freescale.com> | |
6 | * | |
7 | * The hwirq alloc and free code reuse from sysdev/mpic_msi.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | */ | |
15 | #include <linux/irq.h> | |
16 | #include <linux/bootmem.h> | |
34e36c15 JJ |
17 | #include <linux/msi.h> |
18 | #include <linux/pci.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
34e36c15 JJ |
20 | #include <linux/of_platform.h> |
21 | #include <sysdev/fsl_soc.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/hw_irq.h> | |
24 | #include <asm/ppc-pci.h> | |
25 | #include "fsl_msi.h" | |
26 | ||
27 | struct fsl_msi_feature { | |
28 | u32 fsl_pic_ip; | |
29 | u32 msiir_offset; | |
30 | }; | |
31 | ||
32 | static struct fsl_msi *fsl_msi; | |
33 | ||
34 | static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) | |
35 | { | |
36 | return in_be32(base + (reg >> 2)); | |
37 | } | |
38 | ||
34e36c15 JJ |
39 | /* |
40 | * We do not need this actually. The MSIR register has been read once | |
41 | * in the cascade interrupt. So, this MSI interrupt has been acked | |
42 | */ | |
43 | static void fsl_msi_end_irq(unsigned int virq) | |
44 | { | |
45 | } | |
46 | ||
47 | static struct irq_chip fsl_msi_chip = { | |
48 | .mask = mask_msi_irq, | |
49 | .unmask = unmask_msi_irq, | |
50 | .ack = fsl_msi_end_irq, | |
fc380c0c | 51 | .name = "FSL-MSI", |
34e36c15 JJ |
52 | }; |
53 | ||
54 | static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, | |
55 | irq_hw_number_t hw) | |
56 | { | |
57 | struct irq_chip *chip = &fsl_msi_chip; | |
58 | ||
6cff46f4 | 59 | irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; |
34e36c15 | 60 | |
692d1037 | 61 | set_irq_chip_and_handler(virq, chip, handle_edge_irq); |
34e36c15 JJ |
62 | |
63 | return 0; | |
64 | } | |
65 | ||
66 | static struct irq_host_ops fsl_msi_host_ops = { | |
67 | .map = fsl_msi_host_map, | |
68 | }; | |
69 | ||
34e36c15 JJ |
70 | static int fsl_msi_init_allocator(struct fsl_msi *msi_data) |
71 | { | |
692d1037 | 72 | int rc; |
34e36c15 | 73 | |
7e7ab367 ME |
74 | rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS, |
75 | msi_data->irqhost->of_node); | |
76 | if (rc) | |
77 | return rc; | |
34e36c15 | 78 | |
7e7ab367 ME |
79 | rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); |
80 | if (rc < 0) { | |
81 | msi_bitmap_free(&msi_data->bitmap); | |
82 | return rc; | |
34e36c15 JJ |
83 | } |
84 | ||
34e36c15 | 85 | return 0; |
34e36c15 JJ |
86 | } |
87 | ||
88 | static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type) | |
89 | { | |
90 | if (type == PCI_CAP_ID_MSIX) | |
91 | pr_debug("fslmsi: MSI-X untested, trying anyway.\n"); | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
96 | static void fsl_teardown_msi_irqs(struct pci_dev *pdev) | |
97 | { | |
98 | struct msi_desc *entry; | |
99 | struct fsl_msi *msi_data = fsl_msi; | |
100 | ||
101 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
102 | if (entry->irq == NO_IRQ) | |
103 | continue; | |
104 | set_irq_msi(entry->irq, NULL); | |
7e7ab367 ME |
105 | msi_bitmap_free_hwirqs(&msi_data->bitmap, |
106 | virq_to_hw(entry->irq), 1); | |
34e36c15 JJ |
107 | irq_dispose_mapping(entry->irq); |
108 | } | |
109 | ||
110 | return; | |
111 | } | |
112 | ||
113 | static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, | |
114 | struct msi_msg *msg) | |
115 | { | |
116 | struct fsl_msi *msi_data = fsl_msi; | |
3da34aae KG |
117 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
118 | u32 base = 0; | |
34e36c15 | 119 | |
3da34aae KG |
120 | pci_bus_read_config_dword(hose->bus, |
121 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); | |
122 | ||
123 | msg->address_lo = msi_data->msi_addr_lo + base; | |
34e36c15 JJ |
124 | msg->address_hi = msi_data->msi_addr_hi; |
125 | msg->data = hwirq; | |
126 | ||
127 | pr_debug("%s: allocated srs: %d, ibs: %d\n", | |
128 | __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG); | |
129 | } | |
130 | ||
131 | static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
132 | { | |
7e7ab367 | 133 | int rc, hwirq; |
34e36c15 JJ |
134 | unsigned int virq; |
135 | struct msi_desc *entry; | |
136 | struct msi_msg msg; | |
137 | struct fsl_msi *msi_data = fsl_msi; | |
138 | ||
139 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
7e7ab367 | 140 | hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); |
34e36c15 JJ |
141 | if (hwirq < 0) { |
142 | rc = hwirq; | |
143 | pr_debug("%s: fail allocating msi interrupt\n", | |
144 | __func__); | |
145 | goto out_free; | |
146 | } | |
147 | ||
148 | virq = irq_create_mapping(msi_data->irqhost, hwirq); | |
149 | ||
150 | if (virq == NO_IRQ) { | |
7e7ab367 | 151 | pr_debug("%s: fail mapping hwirq 0x%x\n", |
34e36c15 | 152 | __func__, hwirq); |
7e7ab367 | 153 | msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); |
34e36c15 JJ |
154 | rc = -ENOSPC; |
155 | goto out_free; | |
156 | } | |
157 | set_irq_msi(virq, entry); | |
158 | ||
159 | fsl_compose_msi_msg(pdev, hwirq, &msg); | |
160 | write_msi_msg(virq, &msg); | |
161 | } | |
162 | return 0; | |
163 | ||
164 | out_free: | |
165 | return rc; | |
166 | } | |
167 | ||
692d1037 | 168 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
34e36c15 JJ |
169 | { |
170 | unsigned int cascade_irq; | |
171 | struct fsl_msi *msi_data = fsl_msi; | |
172 | int msir_index = -1; | |
173 | u32 msir_value = 0; | |
174 | u32 intr_index; | |
175 | u32 have_shift = 0; | |
176 | ||
239007b8 | 177 | raw_spin_lock(&desc->lock); |
34e36c15 JJ |
178 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
179 | if (desc->chip->mask_ack) | |
180 | desc->chip->mask_ack(irq); | |
181 | else { | |
182 | desc->chip->mask(irq); | |
183 | desc->chip->ack(irq); | |
184 | } | |
185 | } | |
186 | ||
187 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
188 | goto unlock; | |
189 | ||
692d1037 | 190 | msir_index = (int)desc->handler_data; |
34e36c15 JJ |
191 | |
192 | if (msir_index >= NR_MSI_REG) | |
193 | cascade_irq = NO_IRQ; | |
194 | ||
195 | desc->status |= IRQ_INPROGRESS; | |
196 | switch (fsl_msi->feature & FSL_PIC_IP_MASK) { | |
197 | case FSL_PIC_IP_MPIC: | |
198 | msir_value = fsl_msi_read(msi_data->msi_regs, | |
199 | msir_index * 0x10); | |
200 | break; | |
201 | case FSL_PIC_IP_IPIC: | |
202 | msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4); | |
203 | break; | |
204 | } | |
205 | ||
206 | while (msir_value) { | |
207 | intr_index = ffs(msir_value) - 1; | |
208 | ||
209 | cascade_irq = irq_linear_revmap(msi_data->irqhost, | |
692d1037 AV |
210 | msir_index * IRQS_PER_MSI_REG + |
211 | intr_index + have_shift); | |
34e36c15 JJ |
212 | if (cascade_irq != NO_IRQ) |
213 | generic_handle_irq(cascade_irq); | |
692d1037 AV |
214 | have_shift += intr_index + 1; |
215 | msir_value = msir_value >> (intr_index + 1); | |
34e36c15 JJ |
216 | } |
217 | desc->status &= ~IRQ_INPROGRESS; | |
218 | ||
219 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | |
220 | case FSL_PIC_IP_MPIC: | |
221 | desc->chip->eoi(irq); | |
222 | break; | |
223 | case FSL_PIC_IP_IPIC: | |
224 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | |
225 | desc->chip->unmask(irq); | |
226 | break; | |
227 | } | |
228 | unlock: | |
239007b8 | 229 | raw_spin_unlock(&desc->lock); |
34e36c15 JJ |
230 | } |
231 | ||
232 | static int __devinit fsl_of_msi_probe(struct of_device *dev, | |
233 | const struct of_device_id *match) | |
234 | { | |
235 | struct fsl_msi *msi; | |
236 | struct resource res; | |
237 | int err, i, count; | |
238 | int rc; | |
239 | int virt_msir; | |
240 | const u32 *p; | |
692d1037 | 241 | struct fsl_msi_feature *features = match->data; |
34e36c15 JJ |
242 | |
243 | printk(KERN_DEBUG "Setting up Freescale MSI support\n"); | |
244 | ||
245 | msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); | |
246 | if (!msi) { | |
247 | dev_err(&dev->dev, "No memory for MSI structure\n"); | |
248 | err = -ENOMEM; | |
249 | goto error_out; | |
250 | } | |
251 | ||
61c7a080 | 252 | msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR, |
611cd90c | 253 | NR_MSI_IRQS, &fsl_msi_host_ops, 0); |
34e36c15 | 254 | |
34e36c15 JJ |
255 | if (msi->irqhost == NULL) { |
256 | dev_err(&dev->dev, "No memory for MSI irqhost\n"); | |
34e36c15 JJ |
257 | err = -ENOMEM; |
258 | goto error_out; | |
259 | } | |
260 | ||
261 | /* Get the MSI reg base */ | |
61c7a080 | 262 | err = of_address_to_resource(dev->dev.of_node, 0, &res); |
34e36c15 JJ |
263 | if (err) { |
264 | dev_err(&dev->dev, "%s resource error!\n", | |
61c7a080 | 265 | dev->dev.of_node->full_name); |
34e36c15 JJ |
266 | goto error_out; |
267 | } | |
268 | ||
269 | msi->msi_regs = ioremap(res.start, res.end - res.start + 1); | |
270 | if (!msi->msi_regs) { | |
271 | dev_err(&dev->dev, "ioremap problem failed\n"); | |
272 | goto error_out; | |
273 | } | |
274 | ||
692d1037 | 275 | msi->feature = features->fsl_pic_ip; |
34e36c15 JJ |
276 | |
277 | msi->irqhost->host_data = msi; | |
278 | ||
279 | msi->msi_addr_hi = 0x0; | |
3da34aae | 280 | msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff); |
34e36c15 JJ |
281 | |
282 | rc = fsl_msi_init_allocator(msi); | |
283 | if (rc) { | |
284 | dev_err(&dev->dev, "Error allocating MSI bitmap\n"); | |
285 | goto error_out; | |
286 | } | |
287 | ||
61c7a080 | 288 | p = of_get_property(dev->dev.of_node, "interrupts", &count); |
34e36c15 JJ |
289 | if (!p) { |
290 | dev_err(&dev->dev, "no interrupts property found on %s\n", | |
61c7a080 | 291 | dev->dev.of_node->full_name); |
34e36c15 JJ |
292 | err = -ENODEV; |
293 | goto error_out; | |
294 | } | |
295 | if (count % 8 != 0) { | |
296 | dev_err(&dev->dev, "Malformed interrupts property on %s\n", | |
61c7a080 | 297 | dev->dev.of_node->full_name); |
34e36c15 JJ |
298 | err = -EINVAL; |
299 | goto error_out; | |
300 | } | |
301 | ||
302 | count /= sizeof(u32); | |
303 | for (i = 0; i < count / 2; i++) { | |
304 | if (i > NR_MSI_REG) | |
305 | break; | |
61c7a080 | 306 | virt_msir = irq_of_parse_and_map(dev->dev.of_node, i); |
34e36c15 JJ |
307 | if (virt_msir != NO_IRQ) { |
308 | set_irq_data(virt_msir, (void *)i); | |
309 | set_irq_chained_handler(virt_msir, fsl_msi_cascade); | |
310 | } | |
311 | } | |
312 | ||
313 | fsl_msi = msi; | |
314 | ||
315 | WARN_ON(ppc_md.setup_msi_irqs); | |
316 | ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; | |
317 | ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; | |
318 | ppc_md.msi_check_device = fsl_msi_check_device; | |
319 | return 0; | |
320 | error_out: | |
321 | kfree(msi); | |
322 | return err; | |
323 | } | |
324 | ||
325 | static const struct fsl_msi_feature mpic_msi_feature = { | |
326 | .fsl_pic_ip = FSL_PIC_IP_MPIC, | |
327 | .msiir_offset = 0x140, | |
328 | }; | |
329 | ||
330 | static const struct fsl_msi_feature ipic_msi_feature = { | |
331 | .fsl_pic_ip = FSL_PIC_IP_IPIC, | |
332 | .msiir_offset = 0x38, | |
333 | }; | |
334 | ||
335 | static const struct of_device_id fsl_of_msi_ids[] = { | |
336 | { | |
337 | .compatible = "fsl,mpic-msi", | |
338 | .data = (void *)&mpic_msi_feature, | |
339 | }, | |
340 | { | |
341 | .compatible = "fsl,ipic-msi", | |
342 | .data = (void *)&ipic_msi_feature, | |
343 | }, | |
344 | {} | |
345 | }; | |
346 | ||
347 | static struct of_platform_driver fsl_of_msi_driver = { | |
348 | .name = "fsl-msi", | |
349 | .match_table = fsl_of_msi_ids, | |
350 | .probe = fsl_of_msi_probe, | |
351 | }; | |
352 | ||
353 | static __init int fsl_of_msi_init(void) | |
354 | { | |
355 | return of_register_platform_driver(&fsl_of_msi_driver); | |
356 | } | |
357 | ||
358 | subsys_initcall(fsl_of_msi_init); |