]>
Commit | Line | Data |
---|---|---|
f9bd170a PM |
1 | /* |
2 | * i8259 interrupt controller driver. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
0ebfff14 BH |
9 | #undef DEBUG |
10 | ||
1da177e4 LT |
11 | #include <linux/init.h> |
12 | #include <linux/ioport.h> | |
13 | #include <linux/interrupt.h> | |
0ebfff14 BH |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
1da177e4 LT |
16 | #include <asm/io.h> |
17 | #include <asm/i8259.h> | |
0ebfff14 | 18 | #include <asm/prom.h> |
1da177e4 | 19 | |
f9bd170a | 20 | static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */ |
1da177e4 | 21 | |
f9bd170a | 22 | static unsigned char cached_8259[2] = { 0xff, 0xff }; |
1da177e4 LT |
23 | #define cached_A1 (cached_8259[0]) |
24 | #define cached_21 (cached_8259[1]) | |
25 | ||
26 | static DEFINE_SPINLOCK(i8259_lock); | |
27 | ||
0ebfff14 | 28 | static struct irq_host *i8259_host; |
1da177e4 LT |
29 | |
30 | /* | |
31 | * Acknowledge the IRQ using either the PCI host bridge's interrupt | |
32 | * acknowledge feature or poll. How i8259_init() is called determines | |
33 | * which is called. It should be noted that polling is broken on some | |
34 | * IBM and Motorola PReP boxes so we must use the int-ack feature on them. | |
35 | */ | |
35a84c2f | 36 | unsigned int i8259_irq(void) |
1da177e4 LT |
37 | { |
38 | int irq; | |
0ebfff14 | 39 | int lock = 0; |
1da177e4 LT |
40 | |
41 | /* Either int-ack or poll for the IRQ */ | |
42 | if (pci_intack) | |
f9bd170a | 43 | irq = readb(pci_intack); |
1da177e4 | 44 | else { |
0ebfff14 BH |
45 | spin_lock(&i8259_lock); |
46 | lock = 1; | |
47 | ||
1da177e4 LT |
48 | /* Perform an interrupt acknowledge cycle on controller 1. */ |
49 | outb(0x0C, 0x20); /* prepare for poll */ | |
50 | irq = inb(0x20) & 7; | |
51 | if (irq == 2 ) { | |
52 | /* | |
53 | * Interrupt is cascaded so perform interrupt | |
54 | * acknowledge on controller 2. | |
55 | */ | |
56 | outb(0x0C, 0xA0); /* prepare for poll */ | |
57 | irq = (inb(0xA0) & 7) + 8; | |
58 | } | |
59 | } | |
60 | ||
61 | if (irq == 7) { | |
62 | /* | |
63 | * This may be a spurious interrupt. | |
64 | * | |
65 | * Read the interrupt status register (ISR). If the most | |
66 | * significant bit is not set then there is no valid | |
67 | * interrupt. | |
68 | */ | |
69 | if (!pci_intack) | |
70 | outb(0x0B, 0x20); /* ISR register */ | |
71 | if(~inb(0x20) & 0x80) | |
0ebfff14 BH |
72 | irq = NO_IRQ; |
73 | } else if (irq == 0xff) | |
74 | irq = NO_IRQ; | |
1da177e4 | 75 | |
0ebfff14 BH |
76 | if (lock) |
77 | spin_unlock(&i8259_lock); | |
78 | return irq; | |
f9bd170a PM |
79 | } |
80 | ||
1da177e4 LT |
81 | static void i8259_mask_and_ack_irq(unsigned int irq_nr) |
82 | { | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&i8259_lock, flags); | |
1da177e4 LT |
86 | if (irq_nr > 7) { |
87 | cached_A1 |= 1 << (irq_nr-8); | |
f9bd170a PM |
88 | inb(0xA1); /* DUMMY */ |
89 | outb(cached_A1, 0xA1); | |
90 | outb(0x20, 0xA0); /* Non-specific EOI */ | |
91 | outb(0x20, 0x20); /* Non-specific EOI to cascade */ | |
1da177e4 LT |
92 | } else { |
93 | cached_21 |= 1 << irq_nr; | |
f9bd170a PM |
94 | inb(0x21); /* DUMMY */ |
95 | outb(cached_21, 0x21); | |
96 | outb(0x20, 0x20); /* Non-specific EOI */ | |
1da177e4 LT |
97 | } |
98 | spin_unlock_irqrestore(&i8259_lock, flags); | |
99 | } | |
100 | ||
101 | static void i8259_set_irq_mask(int irq_nr) | |
102 | { | |
103 | outb(cached_A1,0xA1); | |
104 | outb(cached_21,0x21); | |
105 | } | |
106 | ||
107 | static void i8259_mask_irq(unsigned int irq_nr) | |
108 | { | |
109 | unsigned long flags; | |
110 | ||
0ebfff14 BH |
111 | pr_debug("i8259_mask_irq(%d)\n", irq_nr); |
112 | ||
1da177e4 | 113 | spin_lock_irqsave(&i8259_lock, flags); |
f9bd170a | 114 | if (irq_nr < 8) |
1da177e4 LT |
115 | cached_21 |= 1 << irq_nr; |
116 | else | |
117 | cached_A1 |= 1 << (irq_nr-8); | |
118 | i8259_set_irq_mask(irq_nr); | |
119 | spin_unlock_irqrestore(&i8259_lock, flags); | |
120 | } | |
121 | ||
122 | static void i8259_unmask_irq(unsigned int irq_nr) | |
123 | { | |
124 | unsigned long flags; | |
125 | ||
0ebfff14 BH |
126 | pr_debug("i8259_unmask_irq(%d)\n", irq_nr); |
127 | ||
1da177e4 | 128 | spin_lock_irqsave(&i8259_lock, flags); |
f9bd170a | 129 | if (irq_nr < 8) |
1da177e4 LT |
130 | cached_21 &= ~(1 << irq_nr); |
131 | else | |
132 | cached_A1 &= ~(1 << (irq_nr-8)); | |
133 | i8259_set_irq_mask(irq_nr); | |
134 | spin_unlock_irqrestore(&i8259_lock, flags); | |
135 | } | |
136 | ||
b9e5b4e6 BH |
137 | static struct irq_chip i8259_pic = { |
138 | .typename = " i8259 ", | |
139 | .mask = i8259_mask_irq, | |
140 | .unmask = i8259_unmask_irq, | |
141 | .mask_ack = i8259_mask_and_ack_irq, | |
1da177e4 LT |
142 | }; |
143 | ||
144 | static struct resource pic1_iores = { | |
145 | .name = "8259 (master)", | |
146 | .start = 0x20, | |
147 | .end = 0x21, | |
148 | .flags = IORESOURCE_BUSY, | |
149 | }; | |
150 | ||
151 | static struct resource pic2_iores = { | |
152 | .name = "8259 (slave)", | |
153 | .start = 0xa0, | |
154 | .end = 0xa1, | |
155 | .flags = IORESOURCE_BUSY, | |
156 | }; | |
157 | ||
158 | static struct resource pic_edgectrl_iores = { | |
159 | .name = "8259 edge control", | |
160 | .start = 0x4d0, | |
161 | .end = 0x4d1, | |
162 | .flags = IORESOURCE_BUSY, | |
163 | }; | |
164 | ||
0ebfff14 BH |
165 | static int i8259_host_match(struct irq_host *h, struct device_node *node) |
166 | { | |
52964f87 | 167 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
168 | } |
169 | ||
170 | static int i8259_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 171 | irq_hw_number_t hw) |
0ebfff14 BH |
172 | { |
173 | pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw); | |
174 | ||
175 | /* We block the internal cascade */ | |
176 | if (hw == 2) | |
177 | get_irq_desc(virq)->status |= IRQ_NOREQUEST; | |
178 | ||
6e99e458 | 179 | /* We use the level handler only for now, we might want to |
0ebfff14 BH |
180 | * be more cautious here but that works for now |
181 | */ | |
182 | get_irq_desc(virq)->status |= IRQ_LEVEL; | |
183 | set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq); | |
184 | return 0; | |
185 | } | |
186 | ||
187 | static void i8259_host_unmap(struct irq_host *h, unsigned int virq) | |
188 | { | |
189 | /* Make sure irq is masked in hardware */ | |
190 | i8259_mask_irq(virq); | |
191 | ||
192 | /* remove chip and handler */ | |
193 | set_irq_chip_and_handler(virq, NULL, NULL); | |
194 | ||
195 | /* Make sure it's completed */ | |
196 | synchronize_irq(virq); | |
197 | } | |
198 | ||
199 | static int i8259_host_xlate(struct irq_host *h, struct device_node *ct, | |
200 | u32 *intspec, unsigned int intsize, | |
201 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
202 | { | |
203 | static unsigned char map_isa_senses[4] = { | |
204 | IRQ_TYPE_LEVEL_LOW, | |
205 | IRQ_TYPE_LEVEL_HIGH, | |
206 | IRQ_TYPE_EDGE_FALLING, | |
207 | IRQ_TYPE_EDGE_RISING, | |
208 | }; | |
209 | ||
210 | *out_hwirq = intspec[0]; | |
211 | if (intsize > 1 && intspec[1] < 4) | |
212 | *out_flags = map_isa_senses[intspec[1]]; | |
213 | else | |
214 | *out_flags = IRQ_TYPE_NONE; | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static struct irq_host_ops i8259_host_ops = { | |
220 | .match = i8259_host_match, | |
221 | .map = i8259_host_map, | |
222 | .unmap = i8259_host_unmap, | |
223 | .xlate = i8259_host_xlate, | |
1da177e4 LT |
224 | }; |
225 | ||
f4d4c354 BH |
226 | struct irq_host *i8259_get_host(void) |
227 | { | |
228 | return i8259_host; | |
229 | } | |
230 | ||
40681b95 | 231 | /** |
0ebfff14 BH |
232 | * i8259_init - Initialize the legacy controller |
233 | * @node: device node of the legacy PIC (can be NULL, but then, it will match | |
234 | * all interrupts, so beware) | |
235 | * @intack_addr: PCI interrupt acknowledge (real) address which will return | |
236 | * the active irq from the 8259 | |
1da177e4 | 237 | */ |
0ebfff14 | 238 | void i8259_init(struct device_node *node, unsigned long intack_addr) |
1da177e4 LT |
239 | { |
240 | unsigned long flags; | |
241 | ||
0ebfff14 | 242 | /* initialize the controller */ |
1da177e4 | 243 | spin_lock_irqsave(&i8259_lock, flags); |
0ebfff14 BH |
244 | |
245 | /* Mask all first */ | |
246 | outb(0xff, 0xA1); | |
247 | outb(0xff, 0x21); | |
f9bd170a | 248 | |
1da177e4 LT |
249 | /* init master interrupt controller */ |
250 | outb(0x11, 0x20); /* Start init sequence */ | |
251 | outb(0x00, 0x21); /* Vector base */ | |
252 | outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */ | |
253 | outb(0x01, 0x21); /* Select 8086 mode */ | |
254 | ||
255 | /* init slave interrupt controller */ | |
256 | outb(0x11, 0xA0); /* Start init sequence */ | |
257 | outb(0x08, 0xA1); /* Vector base */ | |
258 | outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */ | |
259 | outb(0x01, 0xA1); /* Select 8086 mode */ | |
260 | ||
0ebfff14 BH |
261 | /* That thing is slow */ |
262 | udelay(100); | |
263 | ||
1da177e4 LT |
264 | /* always read ISR */ |
265 | outb(0x0B, 0x20); | |
266 | outb(0x0B, 0xA0); | |
267 | ||
0ebfff14 BH |
268 | /* Unmask the internal cascade */ |
269 | cached_21 &= ~(1 << 2); | |
270 | ||
271 | /* Set interrupt masks */ | |
1da177e4 LT |
272 | outb(cached_A1, 0xA1); |
273 | outb(cached_21, 0x21); | |
274 | ||
275 | spin_unlock_irqrestore(&i8259_lock, flags); | |
276 | ||
0ebfff14 | 277 | /* create a legacy host */ |
52964f87 ME |
278 | i8259_host = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LEGACY, |
279 | 0, &i8259_host_ops, 0); | |
0ebfff14 BH |
280 | if (i8259_host == NULL) { |
281 | printk(KERN_ERR "i8259: failed to allocate irq host !\n"); | |
282 | return; | |
b9e5b4e6 | 283 | } |
9d2ba6fa | 284 | |
1da177e4 | 285 | /* reserve our resources */ |
0ebfff14 BH |
286 | /* XXX should we continue doing that ? it seems to cause problems |
287 | * with further requesting of PCI IO resources for that range... | |
288 | * need to look into it. | |
289 | */ | |
1da177e4 LT |
290 | request_resource(&ioport_resource, &pic1_iores); |
291 | request_resource(&ioport_resource, &pic2_iores); | |
292 | request_resource(&ioport_resource, &pic_edgectrl_iores); | |
293 | ||
294 | if (intack_addr != 0) | |
295 | pci_intack = ioremap(intack_addr, 1); | |
f9bd170a | 296 | |
0ebfff14 | 297 | printk(KERN_INFO "i8259 legacy interrupt controller initialized\n"); |
1da177e4 | 298 | } |