[mirror_ubuntu-artful-kernel.git] / arch / powerpc / sysdev / indirect_pci.c

/*
 * Support for indirect PCI bridges.
 *
 * Copyright (C) 1998 Gabriel Paubert.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>

static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
		     int len, u32 *val)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	volatile void __iomem *cfg_data;
	u8 cfg_type = 0;
	u32 bus_no, reg;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
		if (bus->number != hose->first_busno)
			return PCIBIOS_DEVICE_NOT_FOUND;
		if (devfn != 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
	}

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
			return PCIBIOS_DEVICE_NOT_FOUND;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
		if (bus->number != hose->first_busno)
			cfg_type = 1;

	bus_no = (bus->number == hose->first_busno) ?
			hose->self_busno : bus->number;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
	else
		reg = offset & 0xfc;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));
	else
		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + (offset & 3);
	switch (len) {
	case 1:
		*val = in_8(cfg_data);
		break;
	case 2:
		*val = in_le16(cfg_data);
		break;
	default:
		*val = in_le32(cfg_data);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int
indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
		      int len, u32 val)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	volatile void __iomem *cfg_data;
	u8 cfg_type = 0;
	u32 bus_no, reg;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
		if (bus->number != hose->first_busno)
			return PCIBIOS_DEVICE_NOT_FOUND;
		if (devfn != 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
	}

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
			return PCIBIOS_DEVICE_NOT_FOUND;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
		if (bus->number != hose->first_busno)
			cfg_type = 1;

	bus_no = (bus->number == hose->first_busno) ?
			hose->self_busno : bus->number;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
	else
		reg = offset & 0xfc;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));
	else
		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));

	/* surpress setting of PCI_PRIMARY_BUS */
	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
		if ((offset == PCI_PRIMARY_BUS) &&
			(bus->number == hose->first_busno))
		val &= 0xffffff00;

	/* Workaround for PCI_28 Errata in 440EPx/GRx */
	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
			offset == PCI_CACHE_LINE_SIZE) {
		val = 0;
	}

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + (offset & 3);
	switch (len) {
	case 1:
		out_8(cfg_data, val);
		break;
	case 2:
		out_le16(cfg_data, val);
		break;
	default:
		out_le32(cfg_data, val);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops indirect_pci_ops =
{
	.read = indirect_read_config,
	.write = indirect_write_config,
};

void __init
setup_indirect_pci(struct pci_controller* hose,
		   resource_size_t cfg_addr,
		   resource_size_t cfg_data, u32 flags)
{
	resource_size_t base = cfg_addr & PAGE_MASK;
	void __iomem *mbase;

	mbase = ioremap(base, PAGE_SIZE);
	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
	if ((cfg_data & PAGE_MASK) != base)
		mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
	hose->ops = &indirect_pci_ops;
	hose->indirect_type = flags;
}
Commit	Line	Data
daec962e PM	1	/*
	2	* Support for indirect PCI bridges.
	3	*
	4	* Copyright (C) 1998 Gabriel Paubert.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/pci.h>
	14	#include <linux/delay.h>
	15	#include <linux/string.h>
	16	#include <linux/init.h>
	17
	18	#include <asm/io.h>
	19	#include <asm/prom.h>
	20	#include <asm/pci-bridge.h>
	21	#include <asm/machdep.h>
	22
daec962e PM	23	static int
	24	indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
	25	int len, u32 *val)
	26	{
19afa407	27	struct pci_controller *hose = pci_bus_to_host(bus);
daec962e PM	28	volatile void __iomem *cfg_data;
daec962e PM	29	u8 cfg_type = 0;
ab0f9ad3	30	u32 bus_no, reg;
daec962e	31
62c66c8e KG	32	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
	33	if (bus->number != hose->first_busno)
	34	return PCIBIOS_DEVICE_NOT_FOUND;
	35	if (devfn != 0)
	36	return PCIBIOS_DEVICE_NOT_FOUND;
	37	}
	38
daec962e	39	if (ppc_md.pci_exclude_device)
7d52c7b0	40	if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
daec962e	41	return PCIBIOS_DEVICE_NOT_FOUND;
62c66c8e	42
ab0f9ad3	43	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
daec962e PM	44	if (bus->number != hose->first_busno)
	45	cfg_type = 1;
	46
5ab65ecd	47	bus_no = (bus->number == hose->first_busno) ?
0a3786c5	48	hose->self_busno : bus->number;
5ab65ecd	49
ab0f9ad3 KG	50	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
	51	reg = ((offset & 0xf00) << 16) \| (offset & 0xfc);
	52	else
	53	reg = offset & 0xfc;
	54
2e56ff20 KG	55	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
	56	out_be32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	57	(devfn << 8) \| reg \| cfg_type));
	58	else
	59	out_le32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	60	(devfn << 8) \| reg \| cfg_type));
daec962e PM	61
	62	/*
	63	* Note: the caller has already checked that offset is
	64	* suitably aligned and that len is 1, 2 or 4.
	65	*/
	66	cfg_data = hose->cfg_data + (offset & 3);
	67	switch (len) {
	68	case 1:
	69	*val = in_8(cfg_data);
	70	break;
	71	case 2:
	72	*val = in_le16(cfg_data);
	73	break;
	74	default:
	75	*val = in_le32(cfg_data);
	76	break;
	77	}
	78	return PCIBIOS_SUCCESSFUL;
	79	}
	80
	81	static int
	82	indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
	83	int len, u32 val)
	84	{
19afa407	85	struct pci_controller *hose = pci_bus_to_host(bus);
daec962e PM	86	volatile void __iomem *cfg_data;
daec962e PM	87	u8 cfg_type = 0;
ab0f9ad3	88	u32 bus_no, reg;
daec962e	89
62c66c8e KG	90	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
	91	if (bus->number != hose->first_busno)
	92	return PCIBIOS_DEVICE_NOT_FOUND;
	93	if (devfn != 0)
	94	return PCIBIOS_DEVICE_NOT_FOUND;
	95	}
	96
daec962e	97	if (ppc_md.pci_exclude_device)
7d52c7b0	98	if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
daec962e PM	99	return PCIBIOS_DEVICE_NOT_FOUND;
daec962e PM	100
ab0f9ad3	101	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
daec962e PM	102	if (bus->number != hose->first_busno)
	103	cfg_type = 1;
	104
5ab65ecd	105	bus_no = (bus->number == hose->first_busno) ?
0a3786c5	106	hose->self_busno : bus->number;
5ab65ecd	107
ab0f9ad3 KG	108	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
	109	reg = ((offset & 0xf00) << 16) \| (offset & 0xfc);
	110	else
	111	reg = offset & 0xfc;
	112
2e56ff20 KG	113	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
	114	out_be32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	115	(devfn << 8) \| reg \| cfg_type));
	116	else
	117	out_le32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	118	(devfn << 8) \| reg \| cfg_type));
daec962e	119
476f5779 KG	120	/* surpress setting of PCI_PRIMARY_BUS */
	121	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
	122	if ((offset == PCI_PRIMARY_BUS) &&
	123	(bus->number == hose->first_busno))
	124	val &= 0xffffff00;
	125
5ce4b596 JB	126	/* Workaround for PCI_28 Errata in 440EPx/GRx */
	127	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
	128	offset == PCI_CACHE_LINE_SIZE) {
	129	val = 0;
	130	}
	131
daec962e PM	132	/*
	133	* Note: the caller has already checked that offset is
	134	* suitably aligned and that len is 1, 2 or 4.
	135	*/
	136	cfg_data = hose->cfg_data + (offset & 3);
	137	switch (len) {
	138	case 1:
	139	out_8(cfg_data, val);
	140	break;
	141	case 2:
	142	out_le16(cfg_data, val);
	143	break;
	144	default:
	145	out_le32(cfg_data, val);
	146	break;
	147	}
	148	return PCIBIOS_SUCCESSFUL;
	149	}
	150
	151	static struct pci_ops indirect_pci_ops =
	152	{
c78d453b NL	153	.read = indirect_read_config,
c78d453b NL	154	.write = indirect_write_config,
daec962e PM	155	};
daec962e PM	156
daec962e	157	void __init
d94bad82 VB	158	setup_indirect_pci(struct pci_controller* hose,
	159	resource_size_t cfg_addr,
	160	resource_size_t cfg_data, u32 flags)
daec962e	161	{
d94bad82	162	resource_size_t base = cfg_addr & PAGE_MASK;
d5269966	163	void __iomem *mbase;
daec962e PM	164
daec962e PM	165	mbase = ioremap(base, PAGE_SIZE);
d5269966	166	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
daec962e PM	167	if ((cfg_data & PAGE_MASK) != base)
daec962e PM	168	mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
d5269966 KG	169	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
d5269966 KG	170	hose->ops = &indirect_pci_ops;
7659c038	171	hose->indirect_type = flags;
daec962e	172	}