projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 1da177e4 LT |
2 | * IPIC private definitions and structure. |
| 3 | * | |
| 4c8d3d99 | 4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
| 1da177e4 LT |
5 | * |
| 6 | * Copyright 2005 Freescale Semiconductor, Inc | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License as published by the | |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 11 | * option) any later version. | |
| 12 | */ | |
| 13 | #ifndef __IPIC_H__ | |
| 14 | #define __IPIC_H__ | |
| 15 | ||
| 16 | #include <asm/ipic.h> | |
| 17 | ||
| b9f0f1bb KP |
18 | #define NR_IPIC_INTS 128 |
| 19 | ||
| 20 | /* External IRQS */ | |
| 21 | #define IPIC_IRQ_EXT0 48 | |
| 22 | #define IPIC_IRQ_EXT1 17 | |
| 23 | #define IPIC_IRQ_EXT7 23 | |
| 24 | ||
| 25 | /* Default Priority Registers */ | |
| f03ca957 | 26 | #define IPIC_PRIORITY_DEFAULT 0x05309770 |
| 1da177e4 LT |
27 | |
| 28 | /* System Global Interrupt Configuration Register */ | |
| 29 | #define SICFR_IPSA 0x00010000 | |
| f03ca957 LY |
30 | #define SICFR_IPSB 0x00020000 |
| 31 | #define SICFR_IPSC 0x00040000 | |
| 1da177e4 LT |
32 | #define SICFR_IPSD 0x00080000 |
| 33 | #define SICFR_MPSA 0x00200000 | |
| 34 | #define SICFR_MPSB 0x00400000 | |
| 35 | ||
| 36 | /* System External Interrupt Mask Register */ | |
| 37 | #define SEMSR_SIRQ0 0x00008000 | |
| 38 | ||
| 39 | /* System Error Control Register */ | |
| 40 | #define SERCR_MCPR 0x00000001 | |
| 41 | ||
| 42 | struct ipic { | |
| 43 | volatile u32 __iomem *regs; | |
| b9f0f1bb KP |
44 | |
| 45 | /* The remapper for this IPIC */ | |
| 46 | struct irq_host *irqhost; | |
| 1da177e4 LT |
47 | }; |
| 48 | ||
| 49 | struct ipic_info { | |
| 77d4309e LY |
50 | u8 ack; /* pending register offset from base if the irq |
| 51 | supports ack operation */ | |
| 1da177e4 LT |
52 | u8 mask; /* mask register offset from base */ |
| 53 | u8 prio; /* priority register offset from base */ | |
| 54 | u8 force; /* force register offset from base */ | |
| 55 | u8 bit; /* register bit position (as per doc) | |
| 56 | bit mask = 1 << (31 - bit) */ | |
| 57 | u8 prio_mask; /* priority mask value */ | |
| 58 | }; | |
| 59 | ||
| 60 | #endif /* __IPIC_H__ */ |