[mirror_ubuntu-kernels.git] / arch / powerpc / sysdev / ipic.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * IPIC private definitions and structure.
 *
 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 *
 * Copyright 2005 Freescale Semiconductor, Inc
 */
#ifndef __IPIC_H__
#define __IPIC_H__

#include <asm/ipic.h>

#define NR_IPIC_INTS 128

/* External IRQS */
#define IPIC_IRQ_EXT0 48
#define IPIC_IRQ_EXT1 17
#define IPIC_IRQ_EXT7 23

/* Default Priority Registers */
#define IPIC_PRIORITY_DEFAULT 0x05309770

/* System Global Interrupt Configuration Register */
#define	SICFR_IPSA	0x00010000
#define	SICFR_IPSB	0x00020000
#define	SICFR_IPSC	0x00040000
#define	SICFR_IPSD	0x00080000
#define	SICFR_MPSA	0x00200000
#define	SICFR_MPSB	0x00400000

/* System External Interrupt Mask Register */
#define	SEMSR_SIRQ0	0x00008000

/* System Error Control Register */
#define SERCR_MCPR	0x00000001

struct ipic {
	volatile u32 __iomem	*regs;

	/* The remapper for this IPIC */
	struct irq_domain		*irqhost;
};

struct ipic_info {
	u8	ack;		/* pending register offset from base if the irq
				   supports ack operation */
	u8	mask;		/* mask register offset from base */
	u8	prio;		/* priority register offset from base */
	u8	force;		/* force register offset from base */
	u8	bit;		/* register bit position (as per doc)
				   bit mask = 1 << (31 - bit) */
	u8	prio_mask;	/* priority mask value */
};

#endif /* __IPIC_H__ */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4	2	/*
1da177e4 LT	3	* IPIC private definitions and structure.
1da177e4 LT	4	*
4c8d3d99	5	* Maintainer: Kumar Gala <galak@kernel.crashing.org>
1da177e4 LT	6	*
1da177e4 LT	7	* Copyright 2005 Freescale Semiconductor, Inc
1da177e4 LT	8	*/
	9	#ifndef __IPIC_H__
	10	#define __IPIC_H__
	11
	12	#include <asm/ipic.h>
	13
b9f0f1bb KP	14	#define NR_IPIC_INTS 128
	15
	16	/* External IRQS */
	17	#define IPIC_IRQ_EXT0 48
	18	#define IPIC_IRQ_EXT1 17
	19	#define IPIC_IRQ_EXT7 23
	20
	21	/* Default Priority Registers */
f03ca957	22	#define IPIC_PRIORITY_DEFAULT 0x05309770
1da177e4 LT	23
	24	/* System Global Interrupt Configuration Register */
	25	#define SICFR_IPSA 0x00010000
f03ca957 LY	26	#define SICFR_IPSB 0x00020000
f03ca957 LY	27	#define SICFR_IPSC 0x00040000
1da177e4 LT	28	#define SICFR_IPSD 0x00080000
	29	#define SICFR_MPSA 0x00200000
	30	#define SICFR_MPSB 0x00400000
	31
	32	/* System External Interrupt Mask Register */
	33	#define SEMSR_SIRQ0 0x00008000
	34
	35	/* System Error Control Register */
	36	#define SERCR_MCPR 0x00000001
	37
	38	struct ipic {
	39	volatile u32 __iomem *regs;
b9f0f1bb KP	40
b9f0f1bb KP	41	/* The remapper for this IPIC */
bae1d8f1	42	struct irq_domain *irqhost;
1da177e4 LT	43	};
	44
	45	struct ipic_info {
77d4309e LY	46	u8 ack; /* pending register offset from base if the irq
77d4309e LY	47	supports ack operation */
1da177e4 LT	48	u8 mask; /* mask register offset from base */
	49	u8 prio; /* priority register offset from base */
	50	u8 force; /* force register offset from base */
	51	u8 bit; /* register bit position (as per doc)
	52	bit mask = 1 << (31 - bit) */
	53	u8 prio_mask; /* priority mask value */
	54	};
	55
	56	#endif /* __IPIC_H__ */