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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
22d168ce | 9 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
14cf11af PM |
10 | * |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file COPYING in the main directory of this archive | |
13 | * for more details. | |
14 | */ | |
15 | ||
16 | #undef DEBUG | |
1beb6a7d BH |
17 | #undef DEBUG_IPI |
18 | #undef DEBUG_IRQ | |
19 | #undef DEBUG_LOW | |
14cf11af | 20 | |
14cf11af PM |
21 | #include <linux/types.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/bootmem.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
f5a592f7 | 31 | #include <linux/syscore_ops.h> |
76462232 | 32 | #include <linux/ratelimit.h> |
14cf11af PM |
33 | |
34 | #include <asm/ptrace.h> | |
35 | #include <asm/signal.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/machdep.h> | |
40 | #include <asm/mpic.h> | |
41 | #include <asm/smp.h> | |
42 | ||
a7de7c74 ME |
43 | #include "mpic.h" |
44 | ||
14cf11af PM |
45 | #ifdef DEBUG |
46 | #define DBG(fmt...) printk(fmt) | |
47 | #else | |
48 | #define DBG(fmt...) | |
49 | #endif | |
50 | ||
51 | static struct mpic *mpics; | |
52 | static struct mpic *mpic_primary; | |
203041ad | 53 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
14cf11af | 54 | |
c0c0d996 | 55 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
56 | #ifdef CONFIG_IRQ_ALL_CPUS |
57 | #define distribute_irqs (1) | |
58 | #else | |
59 | #define distribute_irqs (0) | |
60 | #endif | |
c0c0d996 | 61 | #endif |
14cf11af | 62 | |
7233593b ZR |
63 | #ifdef CONFIG_MPIC_WEIRD |
64 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
65 | [0] = { /* Original OpenPIC compatible MPIC */ | |
66 | MPIC_GREG_BASE, | |
67 | MPIC_GREG_FEATURE_0, | |
68 | MPIC_GREG_GLOBAL_CONF_0, | |
69 | MPIC_GREG_VENDOR_ID, | |
70 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
71 | MPIC_GREG_IPI_STRIDE, | |
72 | MPIC_GREG_SPURIOUS, | |
73 | MPIC_GREG_TIMER_FREQ, | |
74 | ||
75 | MPIC_TIMER_BASE, | |
76 | MPIC_TIMER_STRIDE, | |
77 | MPIC_TIMER_CURRENT_CNT, | |
78 | MPIC_TIMER_BASE_CNT, | |
79 | MPIC_TIMER_VECTOR_PRI, | |
80 | MPIC_TIMER_DESTINATION, | |
81 | ||
82 | MPIC_CPU_BASE, | |
83 | MPIC_CPU_STRIDE, | |
84 | MPIC_CPU_IPI_DISPATCH_0, | |
85 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
86 | MPIC_CPU_CURRENT_TASK_PRI, | |
87 | MPIC_CPU_WHOAMI, | |
88 | MPIC_CPU_INTACK, | |
89 | MPIC_CPU_EOI, | |
f365355e | 90 | MPIC_CPU_MCACK, |
7233593b ZR |
91 | |
92 | MPIC_IRQ_BASE, | |
93 | MPIC_IRQ_STRIDE, | |
94 | MPIC_IRQ_VECTOR_PRI, | |
95 | MPIC_VECPRI_VECTOR_MASK, | |
96 | MPIC_VECPRI_POLARITY_POSITIVE, | |
97 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
98 | MPIC_VECPRI_SENSE_LEVEL, | |
99 | MPIC_VECPRI_SENSE_EDGE, | |
100 | MPIC_VECPRI_POLARITY_MASK, | |
101 | MPIC_VECPRI_SENSE_MASK, | |
102 | MPIC_IRQ_DESTINATION | |
103 | }, | |
104 | [1] = { /* Tsi108/109 PIC */ | |
105 | TSI108_GREG_BASE, | |
106 | TSI108_GREG_FEATURE_0, | |
107 | TSI108_GREG_GLOBAL_CONF_0, | |
108 | TSI108_GREG_VENDOR_ID, | |
109 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
110 | TSI108_GREG_IPI_STRIDE, | |
111 | TSI108_GREG_SPURIOUS, | |
112 | TSI108_GREG_TIMER_FREQ, | |
113 | ||
114 | TSI108_TIMER_BASE, | |
115 | TSI108_TIMER_STRIDE, | |
116 | TSI108_TIMER_CURRENT_CNT, | |
117 | TSI108_TIMER_BASE_CNT, | |
118 | TSI108_TIMER_VECTOR_PRI, | |
119 | TSI108_TIMER_DESTINATION, | |
120 | ||
121 | TSI108_CPU_BASE, | |
122 | TSI108_CPU_STRIDE, | |
123 | TSI108_CPU_IPI_DISPATCH_0, | |
124 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
125 | TSI108_CPU_CURRENT_TASK_PRI, | |
126 | TSI108_CPU_WHOAMI, | |
127 | TSI108_CPU_INTACK, | |
128 | TSI108_CPU_EOI, | |
f365355e | 129 | TSI108_CPU_MCACK, |
7233593b ZR |
130 | |
131 | TSI108_IRQ_BASE, | |
132 | TSI108_IRQ_STRIDE, | |
133 | TSI108_IRQ_VECTOR_PRI, | |
134 | TSI108_VECPRI_VECTOR_MASK, | |
135 | TSI108_VECPRI_POLARITY_POSITIVE, | |
136 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
137 | TSI108_VECPRI_SENSE_LEVEL, | |
138 | TSI108_VECPRI_SENSE_EDGE, | |
139 | TSI108_VECPRI_POLARITY_MASK, | |
140 | TSI108_VECPRI_SENSE_MASK, | |
141 | TSI108_IRQ_DESTINATION | |
142 | }, | |
143 | }; | |
144 | ||
145 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
146 | ||
147 | #else /* CONFIG_MPIC_WEIRD */ | |
148 | ||
149 | #define MPIC_INFO(name) MPIC_##name | |
150 | ||
151 | #endif /* CONFIG_MPIC_WEIRD */ | |
152 | ||
d6a2639b MI |
153 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
154 | { | |
155 | unsigned int cpu = 0; | |
156 | ||
157 | if (mpic->flags & MPIC_PRIMARY) | |
158 | cpu = hard_smp_processor_id(); | |
159 | ||
160 | return cpu; | |
161 | } | |
162 | ||
14cf11af PM |
163 | /* |
164 | * Register accessor functions | |
165 | */ | |
166 | ||
167 | ||
fbf0274e BH |
168 | static inline u32 _mpic_read(enum mpic_reg_type type, |
169 | struct mpic_reg_bank *rb, | |
170 | unsigned int reg) | |
14cf11af | 171 | { |
fbf0274e BH |
172 | switch(type) { |
173 | #ifdef CONFIG_PPC_DCR | |
174 | case mpic_access_dcr: | |
83f34df4 | 175 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
176 | #endif |
177 | case mpic_access_mmio_be: | |
178 | return in_be32(rb->base + (reg >> 2)); | |
179 | case mpic_access_mmio_le: | |
180 | default: | |
181 | return in_le32(rb->base + (reg >> 2)); | |
182 | } | |
14cf11af PM |
183 | } |
184 | ||
fbf0274e BH |
185 | static inline void _mpic_write(enum mpic_reg_type type, |
186 | struct mpic_reg_bank *rb, | |
187 | unsigned int reg, u32 value) | |
14cf11af | 188 | { |
fbf0274e BH |
189 | switch(type) { |
190 | #ifdef CONFIG_PPC_DCR | |
191 | case mpic_access_dcr: | |
d9d1063d JB |
192 | dcr_write(rb->dhost, reg, value); |
193 | break; | |
fbf0274e BH |
194 | #endif |
195 | case mpic_access_mmio_be: | |
d9d1063d JB |
196 | out_be32(rb->base + (reg >> 2), value); |
197 | break; | |
fbf0274e BH |
198 | case mpic_access_mmio_le: |
199 | default: | |
d9d1063d JB |
200 | out_le32(rb->base + (reg >> 2), value); |
201 | break; | |
fbf0274e | 202 | } |
14cf11af PM |
203 | } |
204 | ||
205 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
206 | { | |
fbf0274e | 207 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
208 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
209 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 210 | |
fbf0274e BH |
211 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
212 | type = mpic_access_mmio_be; | |
213 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
214 | } |
215 | ||
216 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
217 | { | |
7233593b ZR |
218 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
219 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 220 | |
fbf0274e | 221 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
222 | } |
223 | ||
ea94187f SW |
224 | static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) |
225 | { | |
226 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + | |
227 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); | |
228 | ||
229 | if (tm >= 4) | |
230 | offset += 0x1000 / 4; | |
231 | ||
232 | return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); | |
233 | } | |
234 | ||
235 | static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) | |
236 | { | |
237 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + | |
238 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); | |
239 | ||
240 | if (tm >= 4) | |
241 | offset += 0x1000 / 4; | |
242 | ||
243 | _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); | |
244 | } | |
245 | ||
14cf11af PM |
246 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
247 | { | |
d6a2639b | 248 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 249 | |
fbf0274e | 250 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
251 | } |
252 | ||
253 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
254 | { | |
d6a2639b | 255 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 256 | |
fbf0274e | 257 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
258 | } |
259 | ||
260 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
261 | { | |
262 | unsigned int isu = src_no >> mpic->isu_shift; | |
263 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 264 | unsigned int val; |
14cf11af | 265 | |
11a6b292 ME |
266 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
267 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
268 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
269 | if (reg == 0) | |
11a6b292 ME |
270 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
271 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 272 | #endif |
11a6b292 | 273 | return val; |
14cf11af PM |
274 | } |
275 | ||
276 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
277 | unsigned int reg, u32 value) | |
278 | { | |
279 | unsigned int isu = src_no >> mpic->isu_shift; | |
280 | unsigned int idx = src_no & mpic->isu_mask; | |
281 | ||
fbf0274e | 282 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 283 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
284 | |
285 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
286 | if (reg == 0) | |
11a6b292 ME |
287 | mpic->isu_reg0_shadow[src_no] = |
288 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 289 | #endif |
14cf11af PM |
290 | } |
291 | ||
fbf0274e BH |
292 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
293 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
294 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
295 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
ea94187f SW |
296 | #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) |
297 | #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) | |
14cf11af PM |
298 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) |
299 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
300 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
301 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
302 | ||
303 | ||
304 | /* | |
305 | * Low level utility functions | |
306 | */ | |
307 | ||
308 | ||
c51a3fdc | 309 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
310 | struct mpic_reg_bank *rb, unsigned int offset, |
311 | unsigned int size) | |
312 | { | |
313 | rb->base = ioremap(phys_addr + offset, size); | |
314 | BUG_ON(rb->base == NULL); | |
315 | } | |
316 | ||
317 | #ifdef CONFIG_PPC_DCR | |
5a2642f6 BH |
318 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
319 | struct mpic_reg_bank *rb, | |
fbf0274e BH |
320 | unsigned int offset, unsigned int size) |
321 | { | |
0411a5e2 ME |
322 | const u32 *dbasep; |
323 | ||
5a2642f6 | 324 | dbasep = of_get_property(node, "dcr-reg", NULL); |
0411a5e2 | 325 | |
5a2642f6 | 326 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
fbf0274e BH |
327 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
328 | } | |
329 | ||
5a2642f6 BH |
330 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
331 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, | |
332 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
333 | { |
334 | if (mpic->flags & MPIC_USES_DCR) | |
5a2642f6 | 335 | _mpic_map_dcr(mpic, node, rb, offset, size); |
fbf0274e BH |
336 | else |
337 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
338 | } | |
339 | #else /* CONFIG_PPC_DCR */ | |
5a2642f6 | 340 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
341 | #endif /* !CONFIG_PPC_DCR */ |
342 | ||
343 | ||
14cf11af PM |
344 | |
345 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
346 | * reads from IPI registers | |
347 | */ | |
348 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
349 | { | |
350 | u32 r; | |
351 | ||
7233593b ZR |
352 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
353 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
354 | |
355 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
356 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
357 | mpic->flags |= MPIC_BROKEN_IPI; | |
358 | } | |
359 | } | |
360 | ||
6cfef5b2 | 361 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
362 | |
363 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
364 | * to force the edge setting on the MPIC and do the ack workaround. | |
365 | */ | |
1beb6a7d | 366 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 367 | { |
1beb6a7d | 368 | if (source >= 128 || !mpic->fixups) |
14cf11af | 369 | return 0; |
1beb6a7d | 370 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
371 | } |
372 | ||
c4b22f26 | 373 | |
1beb6a7d | 374 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 375 | { |
1beb6a7d | 376 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 377 | |
1beb6a7d BH |
378 | if (fixup->applebase) { |
379 | unsigned int soff = (fixup->index >> 3) & ~3; | |
380 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
381 | writel(mask, fixup->applebase + soff); | |
382 | } else { | |
203041ad | 383 | raw_spin_lock(&mpic->fixup_lock); |
1beb6a7d BH |
384 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
385 | writel(fixup->data, fixup->base + 4); | |
203041ad | 386 | raw_spin_unlock(&mpic->fixup_lock); |
1beb6a7d | 387 | } |
14cf11af PM |
388 | } |
389 | ||
1beb6a7d | 390 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
24a3f2e8 | 391 | bool level) |
1beb6a7d BH |
392 | { |
393 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
394 | unsigned long flags; | |
395 | u32 tmp; | |
396 | ||
397 | if (fixup->base == NULL) | |
398 | return; | |
399 | ||
24a3f2e8 TG |
400 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
401 | source, fixup->index); | |
203041ad | 402 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
403 | /* Enable and configure */ |
404 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
405 | tmp = readl(fixup->base + 4); | |
406 | tmp &= ~(0x23U); | |
24a3f2e8 | 407 | if (level) |
1beb6a7d BH |
408 | tmp |= 0x22; |
409 | writel(tmp, fixup->base + 4); | |
203041ad | 410 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
411 | |
412 | #ifdef CONFIG_PM | |
413 | /* use the lowest bit inverted to the actual HW, | |
414 | * set if this fixup was enabled, clear otherwise */ | |
415 | mpic->save_data[source].fixup_data = tmp | 1; | |
416 | #endif | |
1beb6a7d BH |
417 | } |
418 | ||
24a3f2e8 | 419 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
1beb6a7d BH |
420 | { |
421 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
422 | unsigned long flags; | |
423 | u32 tmp; | |
424 | ||
425 | if (fixup->base == NULL) | |
426 | return; | |
427 | ||
24a3f2e8 | 428 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
1beb6a7d BH |
429 | |
430 | /* Disable */ | |
203041ad | 431 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
432 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
433 | tmp = readl(fixup->base + 4); | |
72b13819 | 434 | tmp |= 1; |
1beb6a7d | 435 | writel(tmp, fixup->base + 4); |
203041ad | 436 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
437 | |
438 | #ifdef CONFIG_PM | |
439 | /* use the lowest bit inverted to the actual HW, | |
440 | * set if this fixup was enabled, clear otherwise */ | |
441 | mpic->save_data[source].fixup_data = tmp & ~1; | |
442 | #endif | |
1beb6a7d | 443 | } |
14cf11af | 444 | |
812fd1fd ME |
445 | #ifdef CONFIG_PCI_MSI |
446 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
447 | unsigned int devfn) | |
448 | { | |
449 | u8 __iomem *base; | |
450 | u8 pos, flags; | |
451 | u64 addr = 0; | |
452 | ||
453 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
454 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
455 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
456 | if (id == PCI_CAP_ID_HT) { | |
457 | id = readb(devbase + pos + 3); | |
458 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
459 | break; | |
460 | } | |
461 | } | |
462 | ||
463 | if (pos == 0) | |
464 | return; | |
465 | ||
466 | base = devbase + pos; | |
467 | ||
468 | flags = readb(base + HT_MSI_FLAGS); | |
469 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
470 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
471 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
472 | } | |
473 | ||
fe333321 | 474 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
475 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
476 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
477 | ||
478 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
479 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
480 | } | |
481 | #else | |
482 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
483 | unsigned int devfn) | |
484 | { | |
485 | return; | |
486 | } | |
487 | #endif | |
488 | ||
1beb6a7d BH |
489 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
490 | unsigned int devfn, u32 vdid) | |
14cf11af | 491 | { |
c4b22f26 | 492 | int i, irq, n; |
1beb6a7d | 493 | u8 __iomem *base; |
14cf11af | 494 | u32 tmp; |
c4b22f26 | 495 | u8 pos; |
14cf11af | 496 | |
1beb6a7d BH |
497 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
498 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
499 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 500 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 501 | id = readb(devbase + pos + 3); |
beb7cc82 | 502 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
503 | break; |
504 | } | |
14cf11af | 505 | } |
c4b22f26 SB |
506 | if (pos == 0) |
507 | return; | |
508 | ||
1beb6a7d BH |
509 | base = devbase + pos; |
510 | writeb(0x01, base + 2); | |
511 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 512 | |
1beb6a7d BH |
513 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
514 | " has %d irqs\n", | |
515 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
516 | |
517 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
518 | writeb(0x10 + 2 * i, base + 2); |
519 | tmp = readl(base + 4); | |
14cf11af | 520 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
521 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
522 | /* mask it , will be unmasked later */ | |
523 | tmp |= 0x1; | |
524 | writel(tmp, base + 4); | |
525 | mpic->fixups[irq].index = i; | |
526 | mpic->fixups[irq].base = base; | |
527 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
528 | if ((vdid & 0xffff) == 0x106b) | |
529 | mpic->fixups[irq].applebase = devbase + 0x60; | |
530 | else | |
531 | mpic->fixups[irq].applebase = NULL; | |
532 | writeb(0x11 + 2 * i, base + 2); | |
533 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
534 | } |
535 | } | |
536 | ||
c4b22f26 | 537 | |
1beb6a7d | 538 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
539 | { |
540 | unsigned int devfn; | |
541 | u8 __iomem *cfgspace; | |
542 | ||
1beb6a7d | 543 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
544 | |
545 | /* Allocate fixups array */ | |
ea96025a | 546 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 547 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
548 | |
549 | /* Init spinlock */ | |
203041ad | 550 | raw_spin_lock_init(&mpic->fixup_lock); |
14cf11af | 551 | |
c4b22f26 SB |
552 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
553 | * so we only need to map 64kB. | |
14cf11af | 554 | */ |
c4b22f26 | 555 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
556 | BUG_ON(cfgspace == NULL); |
557 | ||
1beb6a7d BH |
558 | /* Now we scan all slots. We do a very quick scan, we read the header |
559 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 560 | */ |
c4b22f26 | 561 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
562 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
563 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
564 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 565 | u16 s; |
14cf11af PM |
566 | |
567 | DBG("devfn %x, l: %x\n", devfn, l); | |
568 | ||
569 | /* If no device, skip */ | |
570 | if (l == 0xffffffff || l == 0x00000000 || | |
571 | l == 0x0000ffff || l == 0xffff0000) | |
572 | goto next; | |
1beb6a7d BH |
573 | /* Check if is supports capability lists */ |
574 | s = readw(devbase + PCI_STATUS); | |
575 | if (!(s & PCI_STATUS_CAP_LIST)) | |
576 | goto next; | |
14cf11af | 577 | |
1beb6a7d | 578 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 579 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 580 | |
14cf11af PM |
581 | next: |
582 | /* next device, if function 0 */ | |
c4b22f26 | 583 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
584 | devfn += 7; |
585 | } | |
586 | } | |
587 | ||
6cfef5b2 | 588 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
589 | |
590 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
591 | { | |
592 | return 0; | |
593 | } | |
594 | ||
595 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
596 | { | |
597 | } | |
598 | ||
6cfef5b2 | 599 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 600 | |
14cf11af | 601 | /* Find an mpic associated with a given linux interrupt */ |
d69a78d7 | 602 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 603 | { |
0ebfff14 BH |
604 | if (irq < NUM_ISA_INTERRUPTS) |
605 | return NULL; | |
7df2457d | 606 | |
ec775d0e | 607 | return irq_get_chip_data(irq); |
d69a78d7 | 608 | } |
7df2457d | 609 | |
d69a78d7 TB |
610 | /* Determine if the linux irq is an IPI */ |
611 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) | |
612 | { | |
476eb491 | 613 | unsigned int src = virq_to_hw(irq); |
0ebfff14 | 614 | |
d69a78d7 | 615 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
616 | } |
617 | ||
ea94187f SW |
618 | /* Determine if the linux irq is a timer */ |
619 | static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq) | |
620 | { | |
621 | unsigned int src = virq_to_hw(irq); | |
622 | ||
623 | return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); | |
624 | } | |
d69a78d7 | 625 | |
14cf11af PM |
626 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
627 | static inline u32 mpic_physmask(u32 cpumask) | |
628 | { | |
629 | int i; | |
630 | u32 mask = 0; | |
631 | ||
ebc04215 | 632 | for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) |
14cf11af PM |
633 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
634 | return mask; | |
635 | } | |
636 | ||
637 | #ifdef CONFIG_SMP | |
638 | /* Get the mpic structure from the IPI number */ | |
835c0553 | 639 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
14cf11af | 640 | { |
835c0553 | 641 | return irq_data_get_irq_chip_data(d); |
14cf11af PM |
642 | } |
643 | #endif | |
644 | ||
645 | /* Get the mpic structure from the irq number */ | |
646 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
647 | { | |
ec775d0e | 648 | return irq_get_chip_data(irq); |
835c0553 LB |
649 | } |
650 | ||
651 | /* Get the mpic structure from the irq data */ | |
652 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | |
653 | { | |
654 | return irq_data_get_irq_chip_data(d); | |
14cf11af PM |
655 | } |
656 | ||
657 | /* Send an EOI */ | |
658 | static inline void mpic_eoi(struct mpic *mpic) | |
659 | { | |
7233593b ZR |
660 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
661 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
662 | } |
663 | ||
14cf11af PM |
664 | /* |
665 | * Linux descriptor level callbacks | |
666 | */ | |
667 | ||
668 | ||
835c0553 | 669 | void mpic_unmask_irq(struct irq_data *d) |
14cf11af PM |
670 | { |
671 | unsigned int loops = 100000; | |
835c0553 | 672 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 673 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 674 | |
835c0553 | 675 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
14cf11af | 676 | |
7233593b ZR |
677 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
678 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 679 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
680 | /* make sure mask gets to controller before we return to user */ |
681 | do { | |
682 | if (!loops--) { | |
8bfc5e36 SW |
683 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
684 | __func__, src); | |
14cf11af PM |
685 | break; |
686 | } | |
7233593b | 687 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
688 | } |
689 | ||
835c0553 | 690 | void mpic_mask_irq(struct irq_data *d) |
14cf11af PM |
691 | { |
692 | unsigned int loops = 100000; | |
835c0553 | 693 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 694 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 695 | |
835c0553 | 696 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
14cf11af | 697 | |
7233593b ZR |
698 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
699 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 700 | MPIC_VECPRI_MASK); |
14cf11af PM |
701 | |
702 | /* make sure mask gets to controller before we return to user */ | |
703 | do { | |
704 | if (!loops--) { | |
8bfc5e36 SW |
705 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
706 | __func__, src); | |
14cf11af PM |
707 | break; |
708 | } | |
7233593b | 709 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
710 | } |
711 | ||
835c0553 | 712 | void mpic_end_irq(struct irq_data *d) |
1beb6a7d | 713 | { |
835c0553 | 714 | struct mpic *mpic = mpic_from_irq_data(d); |
b9e5b4e6 BH |
715 | |
716 | #ifdef DEBUG_IRQ | |
835c0553 | 717 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
b9e5b4e6 BH |
718 | #endif |
719 | /* We always EOI on end_irq() even for edge interrupts since that | |
720 | * should only lower the priority, the MPIC should have properly | |
721 | * latched another edge interrupt coming in anyway | |
722 | */ | |
723 | ||
724 | mpic_eoi(mpic); | |
725 | } | |
726 | ||
6cfef5b2 | 727 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 728 | |
835c0553 | 729 | static void mpic_unmask_ht_irq(struct irq_data *d) |
b9e5b4e6 | 730 | { |
835c0553 | 731 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 732 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 733 | |
835c0553 | 734 | mpic_unmask_irq(d); |
1beb6a7d | 735 | |
24a3f2e8 | 736 | if (irqd_is_level_type(d)) |
b9e5b4e6 BH |
737 | mpic_ht_end_irq(mpic, src); |
738 | } | |
739 | ||
835c0553 | 740 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
b9e5b4e6 | 741 | { |
835c0553 | 742 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 743 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 744 | |
835c0553 | 745 | mpic_unmask_irq(d); |
24a3f2e8 | 746 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
b9e5b4e6 BH |
747 | |
748 | return 0; | |
1beb6a7d BH |
749 | } |
750 | ||
835c0553 | 751 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
b9e5b4e6 | 752 | { |
835c0553 | 753 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 754 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 755 | |
24a3f2e8 | 756 | mpic_shutdown_ht_interrupt(mpic, src); |
835c0553 | 757 | mpic_mask_irq(d); |
b9e5b4e6 BH |
758 | } |
759 | ||
835c0553 | 760 | static void mpic_end_ht_irq(struct irq_data *d) |
14cf11af | 761 | { |
835c0553 | 762 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 763 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 764 | |
1beb6a7d | 765 | #ifdef DEBUG_IRQ |
835c0553 | 766 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
1beb6a7d | 767 | #endif |
14cf11af PM |
768 | /* We always EOI on end_irq() even for edge interrupts since that |
769 | * should only lower the priority, the MPIC should have properly | |
770 | * latched another edge interrupt coming in anyway | |
771 | */ | |
772 | ||
24a3f2e8 | 773 | if (irqd_is_level_type(d)) |
b9e5b4e6 | 774 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
775 | mpic_eoi(mpic); |
776 | } | |
6cfef5b2 | 777 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 778 | |
14cf11af PM |
779 | #ifdef CONFIG_SMP |
780 | ||
835c0553 | 781 | static void mpic_unmask_ipi(struct irq_data *d) |
14cf11af | 782 | { |
835c0553 | 783 | struct mpic *mpic = mpic_from_ipi(d); |
476eb491 | 784 | unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
14cf11af | 785 | |
835c0553 | 786 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
14cf11af PM |
787 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
788 | } | |
789 | ||
835c0553 | 790 | static void mpic_mask_ipi(struct irq_data *d) |
14cf11af PM |
791 | { |
792 | /* NEVER disable an IPI... that's just plain wrong! */ | |
793 | } | |
794 | ||
835c0553 | 795 | static void mpic_end_ipi(struct irq_data *d) |
14cf11af | 796 | { |
835c0553 | 797 | struct mpic *mpic = mpic_from_ipi(d); |
14cf11af PM |
798 | |
799 | /* | |
800 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
801 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
802 | * applying to them. We EOI them late to avoid re-entering. | |
14cf11af PM |
803 | */ |
804 | mpic_eoi(mpic); | |
805 | } | |
806 | ||
807 | #endif /* CONFIG_SMP */ | |
808 | ||
ea94187f SW |
809 | static void mpic_unmask_tm(struct irq_data *d) |
810 | { | |
811 | struct mpic *mpic = mpic_from_irq_data(d); | |
812 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; | |
813 | ||
77ef4899 | 814 | DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); |
ea94187f SW |
815 | mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); |
816 | mpic_tm_read(src); | |
817 | } | |
818 | ||
819 | static void mpic_mask_tm(struct irq_data *d) | |
820 | { | |
821 | struct mpic *mpic = mpic_from_irq_data(d); | |
822 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; | |
823 | ||
824 | mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); | |
825 | mpic_tm_read(src); | |
826 | } | |
827 | ||
835c0553 LB |
828 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
829 | bool force) | |
14cf11af | 830 | { |
835c0553 | 831 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 832 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 833 | |
3c10c9c4 | 834 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 835 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 836 | |
3c10c9c4 KG |
837 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
838 | } else { | |
2a116f3d | 839 | u32 mask = cpumask_bits(cpumask)[0]; |
14cf11af | 840 | |
2a116f3d | 841 | mask &= cpumask_bits(cpu_online_mask)[0]; |
3c10c9c4 KG |
842 | |
843 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
2a116f3d | 844 | mpic_physmask(mask)); |
3c10c9c4 | 845 | } |
d5dedd45 YL |
846 | |
847 | return 0; | |
14cf11af PM |
848 | } |
849 | ||
7233593b | 850 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 851 | { |
0ebfff14 | 852 | /* Now convert sense value */ |
6e99e458 | 853 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 854 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
855 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
856 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 857 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 858 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
859 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
860 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 861 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
862 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
863 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
864 | case IRQ_TYPE_LEVEL_LOW: |
865 | default: | |
7233593b ZR |
866 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
867 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 868 | } |
6e99e458 BH |
869 | } |
870 | ||
835c0553 | 871 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
6e99e458 | 872 | { |
835c0553 | 873 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 874 | unsigned int src = irqd_to_hwirq(d); |
6e99e458 BH |
875 | unsigned int vecpri, vold, vnew; |
876 | ||
06fe98e6 | 877 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
835c0553 | 878 | mpic, d->irq, src, flow_type); |
6e99e458 BH |
879 | |
880 | if (src >= mpic->irq_count) | |
881 | return -EINVAL; | |
882 | ||
883 | if (flow_type == IRQ_TYPE_NONE) | |
884 | if (mpic->senses && src < mpic->senses_count) | |
885 | flow_type = mpic->senses[src]; | |
886 | if (flow_type == IRQ_TYPE_NONE) | |
887 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
888 | ||
24a3f2e8 | 889 | irqd_set_trigger_type(d, flow_type); |
6e99e458 BH |
890 | |
891 | if (mpic_is_ht_interrupt(mpic, src)) | |
892 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
893 | MPIC_VECPRI_SENSE_EDGE; | |
894 | else | |
7233593b | 895 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 896 | |
7233593b ZR |
897 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
898 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
899 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
900 | vnew |= vecpri; |
901 | if (vold != vnew) | |
7233593b | 902 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 | 903 | |
e075cd70 | 904 | return IRQ_SET_MASK_OK_NOCOPY; |
0ebfff14 BH |
905 | } |
906 | ||
38958dd9 OJ |
907 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
908 | { | |
909 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 910 | unsigned int src = virq_to_hw(virq); |
38958dd9 OJ |
911 | unsigned int vecpri; |
912 | ||
913 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
914 | mpic, virq, src, vector); | |
915 | ||
916 | if (src >= mpic->irq_count) | |
917 | return; | |
918 | ||
919 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
920 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
921 | vecpri |= vector; | |
922 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
923 | } | |
924 | ||
dfec2202 MI |
925 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
926 | { | |
927 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 928 | unsigned int src = virq_to_hw(virq); |
dfec2202 MI |
929 | |
930 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | |
931 | mpic, virq, src, cpuid); | |
932 | ||
933 | if (src >= mpic->irq_count) | |
934 | return; | |
935 | ||
936 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | |
937 | } | |
938 | ||
b9e5b4e6 | 939 | static struct irq_chip mpic_irq_chip = { |
835c0553 LB |
940 | .irq_mask = mpic_mask_irq, |
941 | .irq_unmask = mpic_unmask_irq, | |
942 | .irq_eoi = mpic_end_irq, | |
943 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
944 | }; |
945 | ||
946 | #ifdef CONFIG_SMP | |
947 | static struct irq_chip mpic_ipi_chip = { | |
835c0553 LB |
948 | .irq_mask = mpic_mask_ipi, |
949 | .irq_unmask = mpic_unmask_ipi, | |
950 | .irq_eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
951 | }; |
952 | #endif /* CONFIG_SMP */ | |
953 | ||
ea94187f SW |
954 | static struct irq_chip mpic_tm_chip = { |
955 | .irq_mask = mpic_mask_tm, | |
956 | .irq_unmask = mpic_unmask_tm, | |
957 | .irq_eoi = mpic_end_irq, | |
958 | }; | |
959 | ||
6cfef5b2 | 960 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 961 | static struct irq_chip mpic_irq_ht_chip = { |
835c0553 LB |
962 | .irq_startup = mpic_startup_ht_irq, |
963 | .irq_shutdown = mpic_shutdown_ht_irq, | |
964 | .irq_mask = mpic_mask_irq, | |
965 | .irq_unmask = mpic_unmask_ht_irq, | |
966 | .irq_eoi = mpic_end_ht_irq, | |
967 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 | 968 | }; |
6cfef5b2 | 969 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 970 | |
14cf11af | 971 | |
0ebfff14 BH |
972 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
973 | { | |
0ebfff14 | 974 | /* Exact match, unless mpic node is NULL */ |
52964f87 | 975 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
976 | } |
977 | ||
978 | static int mpic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 979 | irq_hw_number_t hw) |
0ebfff14 | 980 | { |
0ebfff14 | 981 | struct mpic *mpic = h->host_data; |
6e99e458 | 982 | struct irq_chip *chip; |
0ebfff14 | 983 | |
06fe98e6 | 984 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 985 | |
7df2457d | 986 | if (hw == mpic->spurious_vec) |
0ebfff14 | 987 | return -EINVAL; |
7fd72186 BH |
988 | if (mpic->protected && test_bit(hw, mpic->protected)) |
989 | return -EINVAL; | |
06fe98e6 | 990 | |
0ebfff14 | 991 | #ifdef CONFIG_SMP |
7df2457d | 992 | else if (hw >= mpic->ipi_vecs[0]) { |
0ebfff14 BH |
993 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
994 | ||
06fe98e6 | 995 | DBG("mpic: mapping as IPI\n"); |
ec775d0e TG |
996 | irq_set_chip_data(virq, mpic); |
997 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, | |
0ebfff14 BH |
998 | handle_percpu_irq); |
999 | return 0; | |
1000 | } | |
1001 | #endif /* CONFIG_SMP */ | |
1002 | ||
ea94187f SW |
1003 | if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { |
1004 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); | |
1005 | ||
1006 | DBG("mpic: mapping as timer\n"); | |
1007 | irq_set_chip_data(virq, mpic); | |
1008 | irq_set_chip_and_handler(virq, &mpic->hc_tm, | |
1009 | handle_fasteoi_irq); | |
1010 | return 0; | |
1011 | } | |
1012 | ||
0ebfff14 BH |
1013 | if (hw >= mpic->irq_count) |
1014 | return -EINVAL; | |
1015 | ||
a7de7c74 ME |
1016 | mpic_msi_reserve_hwirq(mpic, hw); |
1017 | ||
6e99e458 | 1018 | /* Default chip */ |
0ebfff14 BH |
1019 | chip = &mpic->hc_irq; |
1020 | ||
6cfef5b2 | 1021 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 1022 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 1023 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 1024 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 1025 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 1026 | |
06fe98e6 | 1027 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 | 1028 | |
ec775d0e TG |
1029 | irq_set_chip_data(virq, mpic); |
1030 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
1031 | |
1032 | /* Set default irq type */ | |
ec775d0e | 1033 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
6e99e458 | 1034 | |
dfec2202 MI |
1035 | /* If the MPIC was reset, then all vectors have already been |
1036 | * initialized. Otherwise, a per source lazy initialization | |
1037 | * is done here. | |
1038 | */ | |
1039 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { | |
dfec2202 | 1040 | mpic_set_vector(virq, hw); |
d6a2639b | 1041 | mpic_set_destination(virq, mpic_processor_id(mpic)); |
dfec2202 MI |
1042 | mpic_irq_set_priority(virq, 8); |
1043 | } | |
1044 | ||
0ebfff14 BH |
1045 | return 0; |
1046 | } | |
1047 | ||
1048 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 1049 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
1050 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
1051 | ||
1052 | { | |
22d168ce | 1053 | struct mpic *mpic = h->host_data; |
0ebfff14 BH |
1054 | static unsigned char map_mpic_senses[4] = { |
1055 | IRQ_TYPE_EDGE_RISING, | |
1056 | IRQ_TYPE_LEVEL_LOW, | |
1057 | IRQ_TYPE_LEVEL_HIGH, | |
1058 | IRQ_TYPE_EDGE_FALLING, | |
1059 | }; | |
1060 | ||
1061 | *out_hwirq = intspec[0]; | |
22d168ce SW |
1062 | if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { |
1063 | /* | |
1064 | * Freescale MPIC with extended intspec: | |
1065 | * First two cells are as usual. Third specifies | |
1066 | * an "interrupt type". Fourth is type-specific data. | |
1067 | * | |
1068 | * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | |
1069 | */ | |
1070 | switch (intspec[2]) { | |
1071 | case 0: | |
1072 | case 1: /* no EISR/EIMR support for now, treat as shared IRQ */ | |
1073 | break; | |
1074 | case 2: | |
1075 | if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) | |
1076 | return -EINVAL; | |
1077 | ||
1078 | *out_hwirq = mpic->ipi_vecs[intspec[0]]; | |
1079 | break; | |
1080 | case 3: | |
1081 | if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) | |
1082 | return -EINVAL; | |
1083 | ||
1084 | *out_hwirq = mpic->timer_vecs[intspec[0]]; | |
1085 | break; | |
1086 | default: | |
1087 | pr_debug("%s: unknown irq type %u\n", | |
1088 | __func__, intspec[2]); | |
1089 | return -EINVAL; | |
1090 | } | |
1091 | ||
1092 | *out_flags = map_mpic_senses[intspec[1] & 3]; | |
1093 | } else if (intsize > 1) { | |
06fe98e6 BH |
1094 | u32 mask = 0x3; |
1095 | ||
1096 | /* Apple invented a new race of encoding on machines with | |
1097 | * an HT APIC. They encode, among others, the index within | |
1098 | * the HT APIC. We don't care about it here since thankfully, | |
1099 | * it appears that they have the APIC already properly | |
1100 | * configured, and thus our current fixup code that reads the | |
1101 | * APIC config works fine. However, we still need to mask out | |
1102 | * bits in the specifier to make sure we only get bit 0 which | |
1103 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1104 | * as their bit 1 means something else. | |
1105 | */ | |
1106 | if (machine_is(powermac)) | |
1107 | mask = 0x1; | |
1108 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1109 | } else | |
0ebfff14 BH |
1110 | *out_flags = IRQ_TYPE_NONE; |
1111 | ||
06fe98e6 BH |
1112 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1113 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1114 | ||
0ebfff14 BH |
1115 | return 0; |
1116 | } | |
1117 | ||
1118 | static struct irq_host_ops mpic_host_ops = { | |
1119 | .match = mpic_host_match, | |
1120 | .map = mpic_host_map, | |
1121 | .xlate = mpic_host_xlate, | |
1122 | }; | |
1123 | ||
dfec2202 MI |
1124 | static int mpic_reset_prohibited(struct device_node *node) |
1125 | { | |
1126 | return node && of_get_property(node, "pic-no-reset", NULL); | |
1127 | } | |
1128 | ||
14cf11af PM |
1129 | /* |
1130 | * Exported functions | |
1131 | */ | |
1132 | ||
0ebfff14 | 1133 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1134 | phys_addr_t phys_addr, |
14cf11af PM |
1135 | unsigned int flags, |
1136 | unsigned int isu_size, | |
14cf11af | 1137 | unsigned int irq_count, |
14cf11af PM |
1138 | const char *name) |
1139 | { | |
5bdb6f2e KM |
1140 | int i, psize, intvec_top; |
1141 | struct mpic *mpic; | |
1142 | u32 greg_feature; | |
1143 | const char *vers; | |
1144 | const u32 *psrc; | |
8bf41568 | 1145 | |
5bdb6f2e KM |
1146 | /* This code assumes that a non-NULL device node is passed in */ |
1147 | BUG_ON(!node); | |
8bf41568 | 1148 | |
5bdb6f2e KM |
1149 | /* Pick the physical address from the device tree if unspecified */ |
1150 | if (!phys_addr) { | |
8bf41568 KM |
1151 | /* Check if it is DCR-based */ |
1152 | if (of_get_property(node, "dcr-reg", NULL)) { | |
1153 | flags |= MPIC_USES_DCR; | |
1154 | } else { | |
1155 | struct resource r; | |
1156 | if (of_address_to_resource(node, 0, &r)) | |
1157 | return NULL; | |
1158 | phys_addr = r.start; | |
1159 | } | |
1160 | } | |
14cf11af | 1161 | |
85355bb2 | 1162 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af PM |
1163 | if (mpic == NULL) |
1164 | return NULL; | |
85355bb2 | 1165 | |
14cf11af PM |
1166 | mpic->name = name; |
1167 | ||
b9e5b4e6 | 1168 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1169 | mpic->hc_irq.name = name; |
14cf11af | 1170 | if (flags & MPIC_PRIMARY) |
835c0553 | 1171 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1172 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1173 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1174 | mpic->hc_ht_irq.name = name; |
b9e5b4e6 | 1175 | if (flags & MPIC_PRIMARY) |
835c0553 | 1176 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1177 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1178 | |
14cf11af | 1179 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1180 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1181 | mpic->hc_ipi.name = name; |
14cf11af PM |
1182 | #endif /* CONFIG_SMP */ |
1183 | ||
ea94187f SW |
1184 | mpic->hc_tm = mpic_tm_chip; |
1185 | mpic->hc_tm.name = name; | |
1186 | ||
14cf11af PM |
1187 | mpic->flags = flags; |
1188 | mpic->isu_size = isu_size; | |
14cf11af | 1189 | mpic->irq_count = irq_count; |
14cf11af | 1190 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1191 | |
7df2457d OJ |
1192 | if (flags & MPIC_LARGE_VECTORS) |
1193 | intvec_top = 2047; | |
1194 | else | |
1195 | intvec_top = 255; | |
1196 | ||
ea94187f SW |
1197 | mpic->timer_vecs[0] = intvec_top - 12; |
1198 | mpic->timer_vecs[1] = intvec_top - 11; | |
1199 | mpic->timer_vecs[2] = intvec_top - 10; | |
1200 | mpic->timer_vecs[3] = intvec_top - 9; | |
1201 | mpic->timer_vecs[4] = intvec_top - 8; | |
1202 | mpic->timer_vecs[5] = intvec_top - 7; | |
1203 | mpic->timer_vecs[6] = intvec_top - 6; | |
1204 | mpic->timer_vecs[7] = intvec_top - 5; | |
7df2457d OJ |
1205 | mpic->ipi_vecs[0] = intvec_top - 4; |
1206 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1207 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1208 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1209 | mpic->spurious_vec = intvec_top; | |
1210 | ||
a959ff56 | 1211 | /* Check for "big-endian" in device-tree */ |
5bdb6f2e | 1212 | if (of_get_property(node, "big-endian", NULL) != NULL) |
a959ff56 | 1213 | mpic->flags |= MPIC_BIG_ENDIAN; |
5bdb6f2e | 1214 | if (of_device_is_compatible(node, "fsl,mpic")) |
22d168ce | 1215 | mpic->flags |= MPIC_FSL; |
a959ff56 | 1216 | |
7fd72186 | 1217 | /* Look for protected sources */ |
5bdb6f2e KM |
1218 | psrc = of_get_property(node, "protected-sources", &psize); |
1219 | if (psrc) { | |
1220 | /* Allocate a bitmap with one bit per interrupt */ | |
1221 | unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); | |
1222 | mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); | |
1223 | BUG_ON(mpic->protected == NULL); | |
1224 | for (i = 0; i < psize/sizeof(u32); i++) { | |
1225 | if (psrc[i] > intvec_top) | |
1226 | continue; | |
1227 | __set_bit(psrc[i], mpic->protected); | |
7fd72186 BH |
1228 | } |
1229 | } | |
a959ff56 | 1230 | |
7233593b ZR |
1231 | #ifdef CONFIG_MPIC_WEIRD |
1232 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
1233 | #endif | |
1234 | ||
fbf0274e | 1235 | /* default register type */ |
8bf41568 KM |
1236 | if (flags & MPIC_BIG_ENDIAN) |
1237 | mpic->reg_type = mpic_access_mmio_be; | |
1238 | else | |
1239 | mpic->reg_type = mpic_access_mmio_le; | |
a959ff56 | 1240 | |
8bf41568 KM |
1241 | /* |
1242 | * An MPIC with a "dcr-reg" property must be accessed that way, but | |
1243 | * only if the kernel includes DCR support. | |
1244 | */ | |
fbf0274e | 1245 | #ifdef CONFIG_PPC_DCR |
8bf41568 | 1246 | if (flags & MPIC_USES_DCR) |
fbf0274e | 1247 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1248 | #else |
8bf41568 KM |
1249 | BUG_ON(flags & MPIC_USES_DCR); |
1250 | #endif | |
a959ff56 | 1251 | |
14cf11af | 1252 | /* Map the global registers */ |
8bf41568 KM |
1253 | mpic_map(mpic, node, phys_addr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1254 | mpic_map(mpic, node, phys_addr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
1255 | |
1256 | /* Reset */ | |
dfec2202 MI |
1257 | |
1258 | /* When using a device-node, reset requests are only honored if the MPIC | |
1259 | * is allowed to reset. | |
1260 | */ | |
1261 | if (mpic_reset_prohibited(node)) | |
1262 | mpic->flags |= MPIC_NO_RESET; | |
1263 | ||
1264 | if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { | |
1265 | printk(KERN_DEBUG "mpic: Resetting\n"); | |
7233593b ZR |
1266 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1267 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1268 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1269 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1270 | & MPIC_GREG_GCONF_RESET) |
1271 | mb(); | |
1272 | } | |
1273 | ||
d91e4ea7 KG |
1274 | /* CoreInt */ |
1275 | if (flags & MPIC_ENABLE_COREINT) | |
1276 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1277 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1278 | | MPIC_GREG_GCONF_COREINT); | |
1279 | ||
f365355e OJ |
1280 | if (flags & MPIC_ENABLE_MCK) |
1281 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1282 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1283 | | MPIC_GREG_GCONF_MCK); | |
1284 | ||
14b92470 TT |
1285 | /* |
1286 | * Read feature register. For non-ISU MPICs, num sources as well. On | |
1287 | * ISU MPICs, sources are counted as ISUs are added | |
14cf11af | 1288 | */ |
d9d1063d | 1289 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
5073e7ee | 1290 | if (isu_size == 0) { |
475ca391 KG |
1291 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
1292 | mpic->num_sources = mpic->irq_count; | |
1293 | else | |
1294 | mpic->num_sources = | |
1295 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1296 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
5073e7ee | 1297 | } |
14cf11af | 1298 | |
14b92470 TT |
1299 | /* |
1300 | * The MPIC driver will crash if there are more cores than we | |
1301 | * can initialize, so we may as well catch that problem here. | |
1302 | */ | |
1303 | BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); | |
1304 | ||
14cf11af | 1305 | /* Map the per-CPU registers */ |
14b92470 TT |
1306 | for_each_possible_cpu(i) { |
1307 | unsigned int cpu = get_hard_smp_processor_id(i); | |
1308 | ||
8bf41568 | 1309 | mpic_map(mpic, node, phys_addr, &mpic->cpuregs[cpu], |
14b92470 | 1310 | MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), |
fbf0274e | 1311 | 0x1000); |
14cf11af PM |
1312 | } |
1313 | ||
1314 | /* Initialize main ISU if none provided */ | |
1315 | if (mpic->isu_size == 0) { | |
1316 | mpic->isu_size = mpic->num_sources; | |
8bf41568 | 1317 | mpic_map(mpic, node, phys_addr, &mpic->isus[0], |
fbf0274e | 1318 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1319 | } |
1320 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1321 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1322 | ||
31207dab KG |
1323 | mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
1324 | isu_size ? isu_size : mpic->num_sources, | |
1325 | &mpic_host_ops, | |
1326 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); | |
1327 | if (mpic->irqhost == NULL) | |
1328 | return NULL; | |
1329 | ||
1330 | mpic->irqhost->host_data = mpic; | |
1331 | ||
14cf11af | 1332 | /* Display version */ |
d9d1063d | 1333 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1334 | case 1: |
1335 | vers = "1.0"; | |
1336 | break; | |
1337 | case 2: | |
1338 | vers = "1.2"; | |
1339 | break; | |
1340 | case 3: | |
1341 | vers = "1.3"; | |
1342 | break; | |
1343 | default: | |
1344 | vers = "<unknown>"; | |
1345 | break; | |
1346 | } | |
a959ff56 BH |
1347 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1348 | " max %d CPUs\n", | |
8bf41568 | 1349 | name, vers, (unsigned long long)phys_addr, num_possible_cpus()); |
a959ff56 BH |
1350 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", |
1351 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1352 | |
1353 | mpic->next = mpics; | |
1354 | mpics = mpic; | |
1355 | ||
0ebfff14 | 1356 | if (flags & MPIC_PRIMARY) { |
14cf11af | 1357 | mpic_primary = mpic; |
0ebfff14 BH |
1358 | irq_set_default_host(mpic->irqhost); |
1359 | } | |
14cf11af PM |
1360 | |
1361 | return mpic; | |
1362 | } | |
1363 | ||
1364 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1365 | phys_addr_t paddr) |
14cf11af PM |
1366 | { |
1367 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1368 | ||
1369 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1370 | ||
5a2642f6 BH |
1371 | mpic_map(mpic, mpic->irqhost->of_node, |
1372 | paddr, &mpic->isus[isu_num], 0, | |
fbf0274e | 1373 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1374 | |
14cf11af PM |
1375 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1376 | mpic->num_sources = isu_first + mpic->isu_size; | |
1377 | } | |
1378 | ||
0ebfff14 BH |
1379 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1380 | { | |
1381 | mpic->senses = senses; | |
1382 | mpic->senses_count = count; | |
1383 | } | |
1384 | ||
14cf11af PM |
1385 | void __init mpic_init(struct mpic *mpic) |
1386 | { | |
1387 | int i; | |
cc353c30 | 1388 | int cpu; |
14cf11af PM |
1389 | |
1390 | BUG_ON(mpic->num_sources == 0); | |
1391 | ||
1392 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1393 | ||
1394 | /* Set current processor priority to max */ | |
7233593b | 1395 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af | 1396 | |
ea94187f | 1397 | /* Initialize timers to our reserved vectors and mask them for now */ |
14cf11af PM |
1398 | for (i = 0; i < 4; i++) { |
1399 | mpic_write(mpic->tmregs, | |
7233593b | 1400 | i * MPIC_INFO(TIMER_STRIDE) + |
ea94187f SW |
1401 | MPIC_INFO(TIMER_DESTINATION), |
1402 | 1 << hard_smp_processor_id()); | |
14cf11af | 1403 | mpic_write(mpic->tmregs, |
7233593b ZR |
1404 | i * MPIC_INFO(TIMER_STRIDE) + |
1405 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af | 1406 | MPIC_VECPRI_MASK | |
ea94187f | 1407 | (9 << MPIC_VECPRI_PRIORITY_SHIFT) | |
7df2457d | 1408 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1409 | } |
1410 | ||
1411 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1412 | mpic_test_broken_ipi(mpic); | |
1413 | for (i = 0; i < 4; i++) { | |
1414 | mpic_ipi_write(i, | |
1415 | MPIC_VECPRI_MASK | | |
1416 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1417 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1418 | } |
1419 | ||
1420 | /* Initialize interrupt sources */ | |
1421 | if (mpic->irq_count == 0) | |
1422 | mpic->irq_count = mpic->num_sources; | |
1423 | ||
1beb6a7d | 1424 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1425 | DBG("MPIC flags: %x\n", mpic->flags); |
05af7bd2 | 1426 | if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { |
3669e930 | 1427 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1428 | mpic_u3msi_init(mpic); |
1429 | } | |
14cf11af | 1430 | |
38958dd9 OJ |
1431 | mpic_pasemi_msi_init(mpic); |
1432 | ||
d6a2639b | 1433 | cpu = mpic_processor_id(mpic); |
cc353c30 | 1434 | |
dfec2202 MI |
1435 | if (!(mpic->flags & MPIC_NO_RESET)) { |
1436 | for (i = 0; i < mpic->num_sources; i++) { | |
1437 | /* start with vector = source number, and masked */ | |
1438 | u32 vecpri = MPIC_VECPRI_MASK | i | | |
1439 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1440 | |
dfec2202 MI |
1441 | /* check if protected */ |
1442 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1443 | continue; | |
1444 | /* init hw */ | |
1445 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
1446 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); | |
1447 | } | |
14cf11af PM |
1448 | } |
1449 | ||
7df2457d OJ |
1450 | /* Init spurious vector */ |
1451 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1452 | |
7233593b ZR |
1453 | /* Disable 8259 passthrough, if supported */ |
1454 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1455 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1456 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1457 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1458 | |
d87bf3be OJ |
1459 | if (mpic->flags & MPIC_NO_BIAS) |
1460 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1461 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1462 | | MPIC_GREG_GCONF_NO_BIAS); | |
1463 | ||
14cf11af | 1464 | /* Set current processor priority to 0 */ |
7233593b | 1465 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1466 | |
1467 | #ifdef CONFIG_PM | |
1468 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1469 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1470 | GFP_KERNEL); | |
3669e930 JB |
1471 | BUG_ON(mpic->save_data == NULL); |
1472 | #endif | |
14cf11af PM |
1473 | } |
1474 | ||
868ea0c9 MG |
1475 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1476 | { | |
1477 | u32 v; | |
1478 | ||
1479 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1480 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1481 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1482 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1483 | } | |
14cf11af | 1484 | |
868ea0c9 MG |
1485 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1486 | { | |
ba1826e5 | 1487 | unsigned long flags; |
868ea0c9 MG |
1488 | u32 v; |
1489 | ||
203041ad | 1490 | raw_spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1491 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1492 | if (enable) | |
1493 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1494 | else | |
1495 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1496 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
203041ad | 1497 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1498 | } |
14cf11af PM |
1499 | |
1500 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1501 | { | |
d69a78d7 | 1502 | struct mpic *mpic = mpic_find(irq); |
476eb491 | 1503 | unsigned int src = virq_to_hw(irq); |
14cf11af PM |
1504 | unsigned long flags; |
1505 | u32 reg; | |
1506 | ||
06a901c5 SR |
1507 | if (!mpic) |
1508 | return; | |
1509 | ||
203041ad | 1510 | raw_spin_lock_irqsave(&mpic_lock, flags); |
d69a78d7 | 1511 | if (mpic_is_ipi(mpic, irq)) { |
7df2457d | 1512 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1513 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1514 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af | 1515 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
ea94187f SW |
1516 | } else if (mpic_is_tm(mpic, irq)) { |
1517 | reg = mpic_tm_read(src - mpic->timer_vecs[0]) & | |
1518 | ~MPIC_VECPRI_PRIORITY_MASK; | |
1519 | mpic_tm_write(src - mpic->timer_vecs[0], | |
1520 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); | |
14cf11af | 1521 | } else { |
7233593b | 1522 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1523 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1524 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1525 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1526 | } | |
203041ad | 1527 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1528 | } |
1529 | ||
14cf11af PM |
1530 | void mpic_setup_this_cpu(void) |
1531 | { | |
1532 | #ifdef CONFIG_SMP | |
1533 | struct mpic *mpic = mpic_primary; | |
1534 | unsigned long flags; | |
1535 | u32 msk = 1 << hard_smp_processor_id(); | |
1536 | unsigned int i; | |
1537 | ||
1538 | BUG_ON(mpic == NULL); | |
1539 | ||
1540 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1541 | ||
203041ad | 1542 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1543 | |
1544 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1545 | * until changed via /proc. That's how it's done on x86. If we want | |
1546 | * it differently, then we should make sure we also change the default | |
a53da52f | 1547 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1548 | */ |
1549 | if (distribute_irqs) { | |
1550 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1551 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1552 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1553 | } |
1554 | ||
1555 | /* Set current processor priority to 0 */ | |
7233593b | 1556 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af | 1557 | |
203041ad | 1558 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1559 | #endif /* CONFIG_SMP */ |
1560 | } | |
1561 | ||
1562 | int mpic_cpu_get_priority(void) | |
1563 | { | |
1564 | struct mpic *mpic = mpic_primary; | |
1565 | ||
7233593b | 1566 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1567 | } |
1568 | ||
1569 | void mpic_cpu_set_priority(int prio) | |
1570 | { | |
1571 | struct mpic *mpic = mpic_primary; | |
1572 | ||
1573 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1574 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1575 | } |
1576 | ||
14cf11af PM |
1577 | void mpic_teardown_this_cpu(int secondary) |
1578 | { | |
1579 | struct mpic *mpic = mpic_primary; | |
1580 | unsigned long flags; | |
1581 | u32 msk = 1 << hard_smp_processor_id(); | |
1582 | unsigned int i; | |
1583 | ||
1584 | BUG_ON(mpic == NULL); | |
1585 | ||
1586 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
203041ad | 1587 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1588 | |
1589 | /* let the mpic know we don't want intrs. */ | |
1590 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1591 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1592 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1593 | |
1594 | /* Set current processor priority to max */ | |
7233593b | 1595 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1596 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1597 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1598 | */ | |
1599 | mpic_eoi(mpic); | |
14cf11af | 1600 | |
203041ad | 1601 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1602 | } |
1603 | ||
1604 | ||
f365355e | 1605 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1606 | { |
0ebfff14 | 1607 | u32 src; |
14cf11af | 1608 | |
f365355e | 1609 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1610 | #ifdef DEBUG_LOW |
f365355e | 1611 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1612 | #endif |
5cddd2e3 JB |
1613 | if (unlikely(src == mpic->spurious_vec)) { |
1614 | if (mpic->flags & MPIC_SPV_EOI) | |
1615 | mpic_eoi(mpic); | |
0ebfff14 | 1616 | return NO_IRQ; |
5cddd2e3 | 1617 | } |
7fd72186 | 1618 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
76462232 CD |
1619 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
1620 | mpic->name, (int)src); | |
7fd72186 BH |
1621 | mpic_eoi(mpic); |
1622 | return NO_IRQ; | |
1623 | } | |
1624 | ||
0ebfff14 | 1625 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1626 | } |
1627 | ||
f365355e OJ |
1628 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1629 | { | |
1630 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1631 | } | |
1632 | ||
35a84c2f | 1633 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1634 | { |
1635 | struct mpic *mpic = mpic_primary; | |
1636 | ||
1637 | BUG_ON(mpic == NULL); | |
1638 | ||
35a84c2f | 1639 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1640 | } |
1641 | ||
d91e4ea7 KG |
1642 | unsigned int mpic_get_coreint_irq(void) |
1643 | { | |
1644 | #ifdef CONFIG_BOOKE | |
1645 | struct mpic *mpic = mpic_primary; | |
1646 | u32 src; | |
1647 | ||
1648 | BUG_ON(mpic == NULL); | |
1649 | ||
1650 | src = mfspr(SPRN_EPR); | |
1651 | ||
1652 | if (unlikely(src == mpic->spurious_vec)) { | |
1653 | if (mpic->flags & MPIC_SPV_EOI) | |
1654 | mpic_eoi(mpic); | |
1655 | return NO_IRQ; | |
1656 | } | |
1657 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
76462232 CD |
1658 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
1659 | mpic->name, (int)src); | |
d91e4ea7 KG |
1660 | return NO_IRQ; |
1661 | } | |
1662 | ||
1663 | return irq_linear_revmap(mpic->irqhost, src); | |
1664 | #else | |
1665 | return NO_IRQ; | |
1666 | #endif | |
1667 | } | |
1668 | ||
f365355e OJ |
1669 | unsigned int mpic_get_mcirq(void) |
1670 | { | |
1671 | struct mpic *mpic = mpic_primary; | |
1672 | ||
1673 | BUG_ON(mpic == NULL); | |
1674 | ||
1675 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1676 | } | |
14cf11af PM |
1677 | |
1678 | #ifdef CONFIG_SMP | |
1679 | void mpic_request_ipis(void) | |
1680 | { | |
1681 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1682 | int i; |
14cf11af | 1683 | BUG_ON(mpic == NULL); |
14cf11af | 1684 | |
8354be9c | 1685 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
0ebfff14 BH |
1686 | |
1687 | for (i = 0; i < 4; i++) { | |
1688 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1689 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1690 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1691 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1692 | continue; | |
d16f1b64 | 1693 | } |
78608dd3 | 1694 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1695 | } |
14cf11af | 1696 | } |
a9c59264 | 1697 | |
3caba98f | 1698 | void smp_mpic_message_pass(int cpu, int msg) |
2ef613cb BH |
1699 | { |
1700 | struct mpic *mpic = mpic_primary; | |
3caba98f | 1701 | u32 physmask; |
2ef613cb BH |
1702 | |
1703 | BUG_ON(mpic == NULL); | |
1704 | ||
a9c59264 PM |
1705 | /* make sure we're sending something that translates to an IPI */ |
1706 | if ((unsigned int)msg > 3) { | |
1707 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1708 | smp_processor_id(), msg); | |
1709 | return; | |
1710 | } | |
3caba98f MM |
1711 | |
1712 | #ifdef DEBUG_IPI | |
1713 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); | |
1714 | #endif | |
1715 | ||
1716 | physmask = 1 << get_hard_smp_processor_id(cpu); | |
1717 | ||
1718 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + | |
1719 | msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); | |
a9c59264 | 1720 | } |
775aeff4 ME |
1721 | |
1722 | int __init smp_mpic_probe(void) | |
1723 | { | |
1724 | int nr_cpus; | |
1725 | ||
1726 | DBG("smp_mpic_probe()...\n"); | |
1727 | ||
2ef613cb | 1728 | nr_cpus = cpumask_weight(cpu_possible_mask); |
775aeff4 ME |
1729 | |
1730 | DBG("nr_cpus: %d\n", nr_cpus); | |
1731 | ||
1732 | if (nr_cpus > 1) | |
1733 | mpic_request_ipis(); | |
1734 | ||
1735 | return nr_cpus; | |
1736 | } | |
1737 | ||
1738 | void __devinit smp_mpic_setup_cpu(int cpu) | |
1739 | { | |
1740 | mpic_setup_this_cpu(); | |
1741 | } | |
66953ebe MM |
1742 | |
1743 | void mpic_reset_core(int cpu) | |
1744 | { | |
1745 | struct mpic *mpic = mpic_primary; | |
1746 | u32 pir; | |
1747 | int cpuid = get_hard_smp_processor_id(cpu); | |
44f16fcf | 1748 | int i; |
66953ebe MM |
1749 | |
1750 | /* Set target bit for core reset */ | |
1751 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1752 | pir |= (1 << cpuid); | |
1753 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1754 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1755 | ||
1756 | /* Restore target bit after reset complete */ | |
1757 | pir &= ~(1 << cpuid); | |
1758 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1759 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
44f16fcf MM |
1760 | |
1761 | /* Perform 15 EOI on each reset core to clear pending interrupts. | |
1762 | * This is required for FSL CoreNet based devices */ | |
1763 | if (mpic->flags & MPIC_FSL) { | |
1764 | for (i = 0; i < 15; i++) { | |
1765 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], | |
1766 | MPIC_CPU_EOI, 0); | |
1767 | } | |
1768 | } | |
66953ebe | 1769 | } |
14cf11af | 1770 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1771 | |
1772 | #ifdef CONFIG_PM | |
f5a592f7 | 1773 | static void mpic_suspend_one(struct mpic *mpic) |
3669e930 | 1774 | { |
3669e930 JB |
1775 | int i; |
1776 | ||
1777 | for (i = 0; i < mpic->num_sources; i++) { | |
1778 | mpic->save_data[i].vecprio = | |
1779 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1780 | mpic->save_data[i].dest = | |
1781 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1782 | } | |
f5a592f7 RW |
1783 | } |
1784 | ||
1785 | static int mpic_suspend(void) | |
1786 | { | |
1787 | struct mpic *mpic = mpics; | |
1788 | ||
1789 | while (mpic) { | |
1790 | mpic_suspend_one(mpic); | |
1791 | mpic = mpic->next; | |
1792 | } | |
3669e930 JB |
1793 | |
1794 | return 0; | |
1795 | } | |
1796 | ||
f5a592f7 | 1797 | static void mpic_resume_one(struct mpic *mpic) |
3669e930 | 1798 | { |
3669e930 JB |
1799 | int i; |
1800 | ||
1801 | for (i = 0; i < mpic->num_sources; i++) { | |
1802 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1803 | mpic->save_data[i].vecprio); | |
1804 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1805 | mpic->save_data[i].dest); | |
1806 | ||
1807 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
7c9d9360 | 1808 | if (mpic->fixups) { |
3669e930 JB |
1809 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
1810 | ||
1811 | if (fixup->base) { | |
1812 | /* we use the lowest bit in an inverted meaning */ | |
1813 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1814 | continue; | |
1815 | ||
1816 | /* Enable and configure */ | |
1817 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1818 | ||
1819 | writel(mpic->save_data[i].fixup_data & ~1, | |
1820 | fixup->base + 4); | |
1821 | } | |
1822 | } | |
1823 | #endif | |
1824 | } /* end for loop */ | |
f5a592f7 | 1825 | } |
3669e930 | 1826 | |
f5a592f7 RW |
1827 | static void mpic_resume(void) |
1828 | { | |
1829 | struct mpic *mpic = mpics; | |
1830 | ||
1831 | while (mpic) { | |
1832 | mpic_resume_one(mpic); | |
1833 | mpic = mpic->next; | |
1834 | } | |
3669e930 | 1835 | } |
3669e930 | 1836 | |
f5a592f7 | 1837 | static struct syscore_ops mpic_syscore_ops = { |
3669e930 JB |
1838 | .resume = mpic_resume, |
1839 | .suspend = mpic_suspend, | |
3669e930 JB |
1840 | }; |
1841 | ||
1842 | static int mpic_init_sys(void) | |
1843 | { | |
f5a592f7 RW |
1844 | register_syscore_ops(&mpic_syscore_ops); |
1845 | return 0; | |
3669e930 JB |
1846 | } |
1847 | ||
1848 | device_initcall(mpic_init_sys); | |
f5a592f7 | 1849 | #endif |