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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file COPYING in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | ||
15 | #undef DEBUG | |
1beb6a7d BH |
16 | #undef DEBUG_IPI |
17 | #undef DEBUG_IRQ | |
18 | #undef DEBUG_LOW | |
14cf11af | 19 | |
14cf11af PM |
20 | #include <linux/types.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/bootmem.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/pci.h> | |
29 | ||
30 | #include <asm/ptrace.h> | |
31 | #include <asm/signal.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/irq.h> | |
35 | #include <asm/machdep.h> | |
36 | #include <asm/mpic.h> | |
37 | #include <asm/smp.h> | |
38 | ||
39 | #ifdef DEBUG | |
40 | #define DBG(fmt...) printk(fmt) | |
41 | #else | |
42 | #define DBG(fmt...) | |
43 | #endif | |
44 | ||
45 | static struct mpic *mpics; | |
46 | static struct mpic *mpic_primary; | |
47 | static DEFINE_SPINLOCK(mpic_lock); | |
48 | ||
c0c0d996 | 49 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
50 | #ifdef CONFIG_IRQ_ALL_CPUS |
51 | #define distribute_irqs (1) | |
52 | #else | |
53 | #define distribute_irqs (0) | |
54 | #endif | |
c0c0d996 | 55 | #endif |
14cf11af | 56 | |
7233593b ZR |
57 | #ifdef CONFIG_MPIC_WEIRD |
58 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
59 | [0] = { /* Original OpenPIC compatible MPIC */ | |
60 | MPIC_GREG_BASE, | |
61 | MPIC_GREG_FEATURE_0, | |
62 | MPIC_GREG_GLOBAL_CONF_0, | |
63 | MPIC_GREG_VENDOR_ID, | |
64 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
65 | MPIC_GREG_IPI_STRIDE, | |
66 | MPIC_GREG_SPURIOUS, | |
67 | MPIC_GREG_TIMER_FREQ, | |
68 | ||
69 | MPIC_TIMER_BASE, | |
70 | MPIC_TIMER_STRIDE, | |
71 | MPIC_TIMER_CURRENT_CNT, | |
72 | MPIC_TIMER_BASE_CNT, | |
73 | MPIC_TIMER_VECTOR_PRI, | |
74 | MPIC_TIMER_DESTINATION, | |
75 | ||
76 | MPIC_CPU_BASE, | |
77 | MPIC_CPU_STRIDE, | |
78 | MPIC_CPU_IPI_DISPATCH_0, | |
79 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
80 | MPIC_CPU_CURRENT_TASK_PRI, | |
81 | MPIC_CPU_WHOAMI, | |
82 | MPIC_CPU_INTACK, | |
83 | MPIC_CPU_EOI, | |
84 | ||
85 | MPIC_IRQ_BASE, | |
86 | MPIC_IRQ_STRIDE, | |
87 | MPIC_IRQ_VECTOR_PRI, | |
88 | MPIC_VECPRI_VECTOR_MASK, | |
89 | MPIC_VECPRI_POLARITY_POSITIVE, | |
90 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
91 | MPIC_VECPRI_SENSE_LEVEL, | |
92 | MPIC_VECPRI_SENSE_EDGE, | |
93 | MPIC_VECPRI_POLARITY_MASK, | |
94 | MPIC_VECPRI_SENSE_MASK, | |
95 | MPIC_IRQ_DESTINATION | |
96 | }, | |
97 | [1] = { /* Tsi108/109 PIC */ | |
98 | TSI108_GREG_BASE, | |
99 | TSI108_GREG_FEATURE_0, | |
100 | TSI108_GREG_GLOBAL_CONF_0, | |
101 | TSI108_GREG_VENDOR_ID, | |
102 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
103 | TSI108_GREG_IPI_STRIDE, | |
104 | TSI108_GREG_SPURIOUS, | |
105 | TSI108_GREG_TIMER_FREQ, | |
106 | ||
107 | TSI108_TIMER_BASE, | |
108 | TSI108_TIMER_STRIDE, | |
109 | TSI108_TIMER_CURRENT_CNT, | |
110 | TSI108_TIMER_BASE_CNT, | |
111 | TSI108_TIMER_VECTOR_PRI, | |
112 | TSI108_TIMER_DESTINATION, | |
113 | ||
114 | TSI108_CPU_BASE, | |
115 | TSI108_CPU_STRIDE, | |
116 | TSI108_CPU_IPI_DISPATCH_0, | |
117 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
118 | TSI108_CPU_CURRENT_TASK_PRI, | |
119 | TSI108_CPU_WHOAMI, | |
120 | TSI108_CPU_INTACK, | |
121 | TSI108_CPU_EOI, | |
122 | ||
123 | TSI108_IRQ_BASE, | |
124 | TSI108_IRQ_STRIDE, | |
125 | TSI108_IRQ_VECTOR_PRI, | |
126 | TSI108_VECPRI_VECTOR_MASK, | |
127 | TSI108_VECPRI_POLARITY_POSITIVE, | |
128 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
129 | TSI108_VECPRI_SENSE_LEVEL, | |
130 | TSI108_VECPRI_SENSE_EDGE, | |
131 | TSI108_VECPRI_POLARITY_MASK, | |
132 | TSI108_VECPRI_SENSE_MASK, | |
133 | TSI108_IRQ_DESTINATION | |
134 | }, | |
135 | }; | |
136 | ||
137 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
138 | ||
139 | #else /* CONFIG_MPIC_WEIRD */ | |
140 | ||
141 | #define MPIC_INFO(name) MPIC_##name | |
142 | ||
143 | #endif /* CONFIG_MPIC_WEIRD */ | |
144 | ||
14cf11af PM |
145 | /* |
146 | * Register accessor functions | |
147 | */ | |
148 | ||
149 | ||
fbf0274e BH |
150 | static inline u32 _mpic_read(enum mpic_reg_type type, |
151 | struct mpic_reg_bank *rb, | |
152 | unsigned int reg) | |
14cf11af | 153 | { |
fbf0274e BH |
154 | switch(type) { |
155 | #ifdef CONFIG_PPC_DCR | |
156 | case mpic_access_dcr: | |
157 | return dcr_read(rb->dhost, | |
158 | rb->dbase + reg + rb->doff); | |
159 | #endif | |
160 | case mpic_access_mmio_be: | |
161 | return in_be32(rb->base + (reg >> 2)); | |
162 | case mpic_access_mmio_le: | |
163 | default: | |
164 | return in_le32(rb->base + (reg >> 2)); | |
165 | } | |
14cf11af PM |
166 | } |
167 | ||
fbf0274e BH |
168 | static inline void _mpic_write(enum mpic_reg_type type, |
169 | struct mpic_reg_bank *rb, | |
170 | unsigned int reg, u32 value) | |
14cf11af | 171 | { |
fbf0274e BH |
172 | switch(type) { |
173 | #ifdef CONFIG_PPC_DCR | |
174 | case mpic_access_dcr: | |
175 | return dcr_write(rb->dhost, | |
176 | rb->dbase + reg + rb->doff, value); | |
177 | #endif | |
178 | case mpic_access_mmio_be: | |
179 | return out_be32(rb->base + (reg >> 2), value); | |
180 | case mpic_access_mmio_le: | |
181 | default: | |
182 | return out_le32(rb->base + (reg >> 2), value); | |
183 | } | |
14cf11af PM |
184 | } |
185 | ||
186 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
187 | { | |
fbf0274e | 188 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
189 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
190 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 191 | |
fbf0274e BH |
192 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
193 | type = mpic_access_mmio_be; | |
194 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
195 | } |
196 | ||
197 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
198 | { | |
7233593b ZR |
199 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
200 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 201 | |
fbf0274e | 202 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
203 | } |
204 | ||
205 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) | |
206 | { | |
207 | unsigned int cpu = 0; | |
208 | ||
209 | if (mpic->flags & MPIC_PRIMARY) | |
210 | cpu = hard_smp_processor_id(); | |
fbf0274e | 211 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
212 | } |
213 | ||
214 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
215 | { | |
216 | unsigned int cpu = 0; | |
217 | ||
218 | if (mpic->flags & MPIC_PRIMARY) | |
219 | cpu = hard_smp_processor_id(); | |
220 | ||
fbf0274e | 221 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
222 | } |
223 | ||
224 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
225 | { | |
226 | unsigned int isu = src_no >> mpic->isu_shift; | |
227 | unsigned int idx = src_no & mpic->isu_mask; | |
228 | ||
fbf0274e | 229 | return _mpic_read(mpic->reg_type, &mpic->isus[isu], |
7233593b | 230 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); |
14cf11af PM |
231 | } |
232 | ||
233 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
234 | unsigned int reg, u32 value) | |
235 | { | |
236 | unsigned int isu = src_no >> mpic->isu_shift; | |
237 | unsigned int idx = src_no & mpic->isu_mask; | |
238 | ||
fbf0274e | 239 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 240 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
14cf11af PM |
241 | } |
242 | ||
fbf0274e BH |
243 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
244 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
245 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
246 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
247 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) | |
248 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
249 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
250 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
251 | ||
252 | ||
253 | /* | |
254 | * Low level utility functions | |
255 | */ | |
256 | ||
257 | ||
fbf0274e BH |
258 | static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr, |
259 | struct mpic_reg_bank *rb, unsigned int offset, | |
260 | unsigned int size) | |
261 | { | |
262 | rb->base = ioremap(phys_addr + offset, size); | |
263 | BUG_ON(rb->base == NULL); | |
264 | } | |
265 | ||
266 | #ifdef CONFIG_PPC_DCR | |
267 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, | |
268 | unsigned int offset, unsigned int size) | |
269 | { | |
270 | rb->dbase = mpic->dcr_base; | |
271 | rb->doff = offset; | |
272 | rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size); | |
273 | BUG_ON(!DCR_MAP_OK(rb->dhost)); | |
274 | } | |
275 | ||
276 | static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr, | |
277 | struct mpic_reg_bank *rb, unsigned int offset, | |
278 | unsigned int size) | |
279 | { | |
280 | if (mpic->flags & MPIC_USES_DCR) | |
281 | _mpic_map_dcr(mpic, rb, offset, size); | |
282 | else | |
283 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
284 | } | |
285 | #else /* CONFIG_PPC_DCR */ | |
286 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) | |
287 | #endif /* !CONFIG_PPC_DCR */ | |
288 | ||
289 | ||
14cf11af PM |
290 | |
291 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
292 | * reads from IPI registers | |
293 | */ | |
294 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
295 | { | |
296 | u32 r; | |
297 | ||
7233593b ZR |
298 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
299 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
300 | |
301 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
302 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
303 | mpic->flags |= MPIC_BROKEN_IPI; | |
304 | } | |
305 | } | |
306 | ||
307 | #ifdef CONFIG_MPIC_BROKEN_U3 | |
308 | ||
309 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
310 | * to force the edge setting on the MPIC and do the ack workaround. | |
311 | */ | |
1beb6a7d | 312 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 313 | { |
1beb6a7d | 314 | if (source >= 128 || !mpic->fixups) |
14cf11af | 315 | return 0; |
1beb6a7d | 316 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
317 | } |
318 | ||
c4b22f26 | 319 | |
1beb6a7d | 320 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 321 | { |
1beb6a7d | 322 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 323 | |
1beb6a7d BH |
324 | if (fixup->applebase) { |
325 | unsigned int soff = (fixup->index >> 3) & ~3; | |
326 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
327 | writel(mask, fixup->applebase + soff); | |
328 | } else { | |
329 | spin_lock(&mpic->fixup_lock); | |
330 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); | |
331 | writel(fixup->data, fixup->base + 4); | |
332 | spin_unlock(&mpic->fixup_lock); | |
333 | } | |
14cf11af PM |
334 | } |
335 | ||
1beb6a7d BH |
336 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
337 | unsigned int irqflags) | |
338 | { | |
339 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
340 | unsigned long flags; | |
341 | u32 tmp; | |
342 | ||
343 | if (fixup->base == NULL) | |
344 | return; | |
345 | ||
06fe98e6 | 346 | DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", |
1beb6a7d BH |
347 | source, irqflags, fixup->index); |
348 | spin_lock_irqsave(&mpic->fixup_lock, flags); | |
349 | /* Enable and configure */ | |
350 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
351 | tmp = readl(fixup->base + 4); | |
352 | tmp &= ~(0x23U); | |
353 | if (irqflags & IRQ_LEVEL) | |
354 | tmp |= 0x22; | |
355 | writel(tmp, fixup->base + 4); | |
356 | spin_unlock_irqrestore(&mpic->fixup_lock, flags); | |
357 | } | |
358 | ||
359 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | |
360 | unsigned int irqflags) | |
361 | { | |
362 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
363 | unsigned long flags; | |
364 | u32 tmp; | |
365 | ||
366 | if (fixup->base == NULL) | |
367 | return; | |
368 | ||
06fe98e6 | 369 | DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); |
1beb6a7d BH |
370 | |
371 | /* Disable */ | |
372 | spin_lock_irqsave(&mpic->fixup_lock, flags); | |
373 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
374 | tmp = readl(fixup->base + 4); | |
72b13819 | 375 | tmp |= 1; |
1beb6a7d BH |
376 | writel(tmp, fixup->base + 4); |
377 | spin_unlock_irqrestore(&mpic->fixup_lock, flags); | |
378 | } | |
14cf11af | 379 | |
1beb6a7d BH |
380 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
381 | unsigned int devfn, u32 vdid) | |
14cf11af | 382 | { |
c4b22f26 | 383 | int i, irq, n; |
1beb6a7d | 384 | u8 __iomem *base; |
14cf11af | 385 | u32 tmp; |
c4b22f26 | 386 | u8 pos; |
14cf11af | 387 | |
1beb6a7d BH |
388 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
389 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
390 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 391 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 392 | id = readb(devbase + pos + 3); |
e78d0169 | 393 | if (id == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
394 | break; |
395 | } | |
14cf11af | 396 | } |
c4b22f26 SB |
397 | if (pos == 0) |
398 | return; | |
399 | ||
1beb6a7d BH |
400 | base = devbase + pos; |
401 | writeb(0x01, base + 2); | |
402 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 403 | |
1beb6a7d BH |
404 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
405 | " has %d irqs\n", | |
406 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
407 | |
408 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
409 | writeb(0x10 + 2 * i, base + 2); |
410 | tmp = readl(base + 4); | |
14cf11af | 411 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
412 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
413 | /* mask it , will be unmasked later */ | |
414 | tmp |= 0x1; | |
415 | writel(tmp, base + 4); | |
416 | mpic->fixups[irq].index = i; | |
417 | mpic->fixups[irq].base = base; | |
418 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
419 | if ((vdid & 0xffff) == 0x106b) | |
420 | mpic->fixups[irq].applebase = devbase + 0x60; | |
421 | else | |
422 | mpic->fixups[irq].applebase = NULL; | |
423 | writeb(0x11 + 2 * i, base + 2); | |
424 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
425 | } |
426 | } | |
427 | ||
c4b22f26 | 428 | |
1beb6a7d | 429 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
430 | { |
431 | unsigned int devfn; | |
432 | u8 __iomem *cfgspace; | |
433 | ||
1beb6a7d | 434 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
435 | |
436 | /* Allocate fixups array */ | |
437 | mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); | |
438 | BUG_ON(mpic->fixups == NULL); | |
439 | memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); | |
440 | ||
441 | /* Init spinlock */ | |
442 | spin_lock_init(&mpic->fixup_lock); | |
443 | ||
c4b22f26 SB |
444 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
445 | * so we only need to map 64kB. | |
14cf11af | 446 | */ |
c4b22f26 | 447 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
448 | BUG_ON(cfgspace == NULL); |
449 | ||
1beb6a7d BH |
450 | /* Now we scan all slots. We do a very quick scan, we read the header |
451 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 452 | */ |
c4b22f26 | 453 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
454 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
455 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
456 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 457 | u16 s; |
14cf11af PM |
458 | |
459 | DBG("devfn %x, l: %x\n", devfn, l); | |
460 | ||
461 | /* If no device, skip */ | |
462 | if (l == 0xffffffff || l == 0x00000000 || | |
463 | l == 0x0000ffff || l == 0xffff0000) | |
464 | goto next; | |
1beb6a7d BH |
465 | /* Check if is supports capability lists */ |
466 | s = readw(devbase + PCI_STATUS); | |
467 | if (!(s & PCI_STATUS_CAP_LIST)) | |
468 | goto next; | |
14cf11af | 469 | |
1beb6a7d | 470 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
c4b22f26 | 471 | |
14cf11af PM |
472 | next: |
473 | /* next device, if function 0 */ | |
c4b22f26 | 474 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
475 | devfn += 7; |
476 | } | |
477 | } | |
478 | ||
6e99e458 BH |
479 | #else /* CONFIG_MPIC_BROKEN_U3 */ |
480 | ||
481 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
482 | { | |
483 | return 0; | |
484 | } | |
485 | ||
486 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
487 | { | |
488 | } | |
489 | ||
14cf11af PM |
490 | #endif /* CONFIG_MPIC_BROKEN_U3 */ |
491 | ||
492 | ||
0ebfff14 BH |
493 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
494 | ||
14cf11af PM |
495 | /* Find an mpic associated with a given linux interrupt */ |
496 | static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) | |
497 | { | |
0ebfff14 BH |
498 | unsigned int src = mpic_irq_to_hw(irq); |
499 | ||
500 | if (irq < NUM_ISA_INTERRUPTS) | |
501 | return NULL; | |
502 | if (is_ipi) | |
503 | *is_ipi = (src >= MPIC_VEC_IPI_0 && src <= MPIC_VEC_IPI_3); | |
504 | ||
505 | return irq_desc[irq].chip_data; | |
14cf11af PM |
506 | } |
507 | ||
508 | /* Convert a cpu mask from logical to physical cpu numbers. */ | |
509 | static inline u32 mpic_physmask(u32 cpumask) | |
510 | { | |
511 | int i; | |
512 | u32 mask = 0; | |
513 | ||
514 | for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) | |
515 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); | |
516 | return mask; | |
517 | } | |
518 | ||
519 | #ifdef CONFIG_SMP | |
520 | /* Get the mpic structure from the IPI number */ | |
521 | static inline struct mpic * mpic_from_ipi(unsigned int ipi) | |
522 | { | |
b9e5b4e6 | 523 | return irq_desc[ipi].chip_data; |
14cf11af PM |
524 | } |
525 | #endif | |
526 | ||
527 | /* Get the mpic structure from the irq number */ | |
528 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
529 | { | |
b9e5b4e6 | 530 | return irq_desc[irq].chip_data; |
14cf11af PM |
531 | } |
532 | ||
533 | /* Send an EOI */ | |
534 | static inline void mpic_eoi(struct mpic *mpic) | |
535 | { | |
7233593b ZR |
536 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
537 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
538 | } |
539 | ||
540 | #ifdef CONFIG_SMP | |
7d12e780 | 541 | static irqreturn_t mpic_ipi_action(int irq, void *dev_id) |
14cf11af | 542 | { |
7d12e780 | 543 | smp_message_recv(mpic_irq_to_hw(irq) - MPIC_VEC_IPI_0); |
14cf11af PM |
544 | return IRQ_HANDLED; |
545 | } | |
546 | #endif /* CONFIG_SMP */ | |
547 | ||
548 | /* | |
549 | * Linux descriptor level callbacks | |
550 | */ | |
551 | ||
552 | ||
b9e5b4e6 | 553 | static void mpic_unmask_irq(unsigned int irq) |
14cf11af PM |
554 | { |
555 | unsigned int loops = 100000; | |
556 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 557 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af | 558 | |
bd561c79 | 559 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); |
14cf11af | 560 | |
7233593b ZR |
561 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
562 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 563 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
564 | /* make sure mask gets to controller before we return to user */ |
565 | do { | |
566 | if (!loops--) { | |
567 | printk(KERN_ERR "mpic_enable_irq timeout\n"); | |
568 | break; | |
569 | } | |
7233593b | 570 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
571 | } |
572 | ||
b9e5b4e6 | 573 | static void mpic_mask_irq(unsigned int irq) |
14cf11af PM |
574 | { |
575 | unsigned int loops = 100000; | |
576 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 577 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
578 | |
579 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); | |
580 | ||
7233593b ZR |
581 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
582 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 583 | MPIC_VECPRI_MASK); |
14cf11af PM |
584 | |
585 | /* make sure mask gets to controller before we return to user */ | |
586 | do { | |
587 | if (!loops--) { | |
588 | printk(KERN_ERR "mpic_enable_irq timeout\n"); | |
589 | break; | |
590 | } | |
7233593b | 591 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
592 | } |
593 | ||
b9e5b4e6 | 594 | static void mpic_end_irq(unsigned int irq) |
1beb6a7d | 595 | { |
b9e5b4e6 BH |
596 | struct mpic *mpic = mpic_from_irq(irq); |
597 | ||
598 | #ifdef DEBUG_IRQ | |
599 | DBG("%s: end_irq: %d\n", mpic->name, irq); | |
600 | #endif | |
601 | /* We always EOI on end_irq() even for edge interrupts since that | |
602 | * should only lower the priority, the MPIC should have properly | |
603 | * latched another edge interrupt coming in anyway | |
604 | */ | |
605 | ||
606 | mpic_eoi(mpic); | |
607 | } | |
608 | ||
1beb6a7d | 609 | #ifdef CONFIG_MPIC_BROKEN_U3 |
b9e5b4e6 BH |
610 | |
611 | static void mpic_unmask_ht_irq(unsigned int irq) | |
612 | { | |
1beb6a7d | 613 | struct mpic *mpic = mpic_from_irq(irq); |
0ebfff14 | 614 | unsigned int src = mpic_irq_to_hw(irq); |
1beb6a7d | 615 | |
b9e5b4e6 | 616 | mpic_unmask_irq(irq); |
1beb6a7d | 617 | |
b9e5b4e6 BH |
618 | if (irq_desc[irq].status & IRQ_LEVEL) |
619 | mpic_ht_end_irq(mpic, src); | |
620 | } | |
621 | ||
622 | static unsigned int mpic_startup_ht_irq(unsigned int irq) | |
623 | { | |
624 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 625 | unsigned int src = mpic_irq_to_hw(irq); |
1beb6a7d | 626 | |
b9e5b4e6 BH |
627 | mpic_unmask_irq(irq); |
628 | mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); | |
629 | ||
630 | return 0; | |
1beb6a7d BH |
631 | } |
632 | ||
b9e5b4e6 BH |
633 | static void mpic_shutdown_ht_irq(unsigned int irq) |
634 | { | |
635 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 636 | unsigned int src = mpic_irq_to_hw(irq); |
b9e5b4e6 BH |
637 | |
638 | mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); | |
639 | mpic_mask_irq(irq); | |
640 | } | |
641 | ||
642 | static void mpic_end_ht_irq(unsigned int irq) | |
14cf11af PM |
643 | { |
644 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 645 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af | 646 | |
1beb6a7d | 647 | #ifdef DEBUG_IRQ |
14cf11af | 648 | DBG("%s: end_irq: %d\n", mpic->name, irq); |
1beb6a7d | 649 | #endif |
14cf11af PM |
650 | /* We always EOI on end_irq() even for edge interrupts since that |
651 | * should only lower the priority, the MPIC should have properly | |
652 | * latched another edge interrupt coming in anyway | |
653 | */ | |
654 | ||
b9e5b4e6 BH |
655 | if (irq_desc[irq].status & IRQ_LEVEL) |
656 | mpic_ht_end_irq(mpic, src); | |
14cf11af PM |
657 | mpic_eoi(mpic); |
658 | } | |
6e99e458 | 659 | #endif /* !CONFIG_MPIC_BROKEN_U3 */ |
b9e5b4e6 | 660 | |
14cf11af PM |
661 | #ifdef CONFIG_SMP |
662 | ||
b9e5b4e6 | 663 | static void mpic_unmask_ipi(unsigned int irq) |
14cf11af PM |
664 | { |
665 | struct mpic *mpic = mpic_from_ipi(irq); | |
0ebfff14 | 666 | unsigned int src = mpic_irq_to_hw(irq) - MPIC_VEC_IPI_0; |
14cf11af PM |
667 | |
668 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); | |
669 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); | |
670 | } | |
671 | ||
b9e5b4e6 | 672 | static void mpic_mask_ipi(unsigned int irq) |
14cf11af PM |
673 | { |
674 | /* NEVER disable an IPI... that's just plain wrong! */ | |
675 | } | |
676 | ||
677 | static void mpic_end_ipi(unsigned int irq) | |
678 | { | |
679 | struct mpic *mpic = mpic_from_ipi(irq); | |
680 | ||
681 | /* | |
682 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
683 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
684 | * applying to them. We EOI them late to avoid re-entering. | |
6714465e | 685 | * We mark IPI's with IRQF_DISABLED as they must run with |
14cf11af PM |
686 | * irqs disabled. |
687 | */ | |
688 | mpic_eoi(mpic); | |
689 | } | |
690 | ||
691 | #endif /* CONFIG_SMP */ | |
692 | ||
693 | static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) | |
694 | { | |
695 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 696 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
697 | |
698 | cpumask_t tmp; | |
699 | ||
700 | cpus_and(tmp, cpumask, cpu_online_map); | |
701 | ||
7233593b | 702 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), |
14cf11af PM |
703 | mpic_physmask(cpus_addr(tmp)[0])); |
704 | } | |
705 | ||
7233593b | 706 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 707 | { |
0ebfff14 | 708 | /* Now convert sense value */ |
6e99e458 | 709 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 710 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
711 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
712 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 713 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 714 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
715 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
716 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 717 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
718 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
719 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
720 | case IRQ_TYPE_LEVEL_LOW: |
721 | default: | |
7233593b ZR |
722 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
723 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 724 | } |
6e99e458 BH |
725 | } |
726 | ||
727 | static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) | |
728 | { | |
729 | struct mpic *mpic = mpic_from_irq(virq); | |
730 | unsigned int src = mpic_irq_to_hw(virq); | |
731 | struct irq_desc *desc = get_irq_desc(virq); | |
732 | unsigned int vecpri, vold, vnew; | |
733 | ||
06fe98e6 BH |
734 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
735 | mpic, virq, src, flow_type); | |
6e99e458 BH |
736 | |
737 | if (src >= mpic->irq_count) | |
738 | return -EINVAL; | |
739 | ||
740 | if (flow_type == IRQ_TYPE_NONE) | |
741 | if (mpic->senses && src < mpic->senses_count) | |
742 | flow_type = mpic->senses[src]; | |
743 | if (flow_type == IRQ_TYPE_NONE) | |
744 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
745 | ||
746 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | |
747 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | |
748 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
749 | desc->status |= IRQ_LEVEL; | |
750 | ||
751 | if (mpic_is_ht_interrupt(mpic, src)) | |
752 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
753 | MPIC_VECPRI_SENSE_EDGE; | |
754 | else | |
7233593b | 755 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 756 | |
7233593b ZR |
757 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
758 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
759 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
760 | vnew |= vecpri; |
761 | if (vold != vnew) | |
7233593b | 762 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 BH |
763 | |
764 | return 0; | |
0ebfff14 BH |
765 | } |
766 | ||
b9e5b4e6 | 767 | static struct irq_chip mpic_irq_chip = { |
6e99e458 BH |
768 | .mask = mpic_mask_irq, |
769 | .unmask = mpic_unmask_irq, | |
770 | .eoi = mpic_end_irq, | |
771 | .set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
772 | }; |
773 | ||
774 | #ifdef CONFIG_SMP | |
775 | static struct irq_chip mpic_ipi_chip = { | |
6e99e458 BH |
776 | .mask = mpic_mask_ipi, |
777 | .unmask = mpic_unmask_ipi, | |
778 | .eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
779 | }; |
780 | #endif /* CONFIG_SMP */ | |
781 | ||
782 | #ifdef CONFIG_MPIC_BROKEN_U3 | |
783 | static struct irq_chip mpic_irq_ht_chip = { | |
784 | .startup = mpic_startup_ht_irq, | |
785 | .shutdown = mpic_shutdown_ht_irq, | |
786 | .mask = mpic_mask_irq, | |
787 | .unmask = mpic_unmask_ht_irq, | |
788 | .eoi = mpic_end_ht_irq, | |
6e99e458 | 789 | .set_type = mpic_set_irq_type, |
b9e5b4e6 BH |
790 | }; |
791 | #endif /* CONFIG_MPIC_BROKEN_U3 */ | |
792 | ||
14cf11af | 793 | |
0ebfff14 BH |
794 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
795 | { | |
796 | struct mpic *mpic = h->host_data; | |
797 | ||
798 | /* Exact match, unless mpic node is NULL */ | |
799 | return mpic->of_node == NULL || mpic->of_node == node; | |
800 | } | |
801 | ||
802 | static int mpic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 803 | irq_hw_number_t hw) |
0ebfff14 | 804 | { |
0ebfff14 | 805 | struct mpic *mpic = h->host_data; |
6e99e458 | 806 | struct irq_chip *chip; |
0ebfff14 | 807 | |
06fe98e6 | 808 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 BH |
809 | |
810 | if (hw == MPIC_VEC_SPURRIOUS) | |
811 | return -EINVAL; | |
06fe98e6 | 812 | |
0ebfff14 BH |
813 | #ifdef CONFIG_SMP |
814 | else if (hw >= MPIC_VEC_IPI_0) { | |
815 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); | |
816 | ||
06fe98e6 | 817 | DBG("mpic: mapping as IPI\n"); |
0ebfff14 BH |
818 | set_irq_chip_data(virq, mpic); |
819 | set_irq_chip_and_handler(virq, &mpic->hc_ipi, | |
820 | handle_percpu_irq); | |
821 | return 0; | |
822 | } | |
823 | #endif /* CONFIG_SMP */ | |
824 | ||
825 | if (hw >= mpic->irq_count) | |
826 | return -EINVAL; | |
827 | ||
6e99e458 | 828 | /* Default chip */ |
0ebfff14 BH |
829 | chip = &mpic->hc_irq; |
830 | ||
831 | #ifdef CONFIG_MPIC_BROKEN_U3 | |
832 | /* Check for HT interrupts, override vecpri */ | |
6e99e458 | 833 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 834 | chip = &mpic->hc_ht_irq; |
6e99e458 | 835 | #endif /* CONFIG_MPIC_BROKEN_U3 */ |
0ebfff14 | 836 | |
06fe98e6 | 837 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 BH |
838 | |
839 | set_irq_chip_data(virq, mpic); | |
840 | set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
841 | |
842 | /* Set default irq type */ | |
843 | set_irq_type(virq, IRQ_TYPE_NONE); | |
844 | ||
0ebfff14 BH |
845 | return 0; |
846 | } | |
847 | ||
848 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, | |
849 | u32 *intspec, unsigned int intsize, | |
850 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
851 | ||
852 | { | |
853 | static unsigned char map_mpic_senses[4] = { | |
854 | IRQ_TYPE_EDGE_RISING, | |
855 | IRQ_TYPE_LEVEL_LOW, | |
856 | IRQ_TYPE_LEVEL_HIGH, | |
857 | IRQ_TYPE_EDGE_FALLING, | |
858 | }; | |
859 | ||
860 | *out_hwirq = intspec[0]; | |
06fe98e6 BH |
861 | if (intsize > 1) { |
862 | u32 mask = 0x3; | |
863 | ||
864 | /* Apple invented a new race of encoding on machines with | |
865 | * an HT APIC. They encode, among others, the index within | |
866 | * the HT APIC. We don't care about it here since thankfully, | |
867 | * it appears that they have the APIC already properly | |
868 | * configured, and thus our current fixup code that reads the | |
869 | * APIC config works fine. However, we still need to mask out | |
870 | * bits in the specifier to make sure we only get bit 0 which | |
871 | * is the level/edge bit (the only sense bit exposed by Apple), | |
872 | * as their bit 1 means something else. | |
873 | */ | |
874 | if (machine_is(powermac)) | |
875 | mask = 0x1; | |
876 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
877 | } else | |
0ebfff14 BH |
878 | *out_flags = IRQ_TYPE_NONE; |
879 | ||
06fe98e6 BH |
880 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
881 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
882 | ||
0ebfff14 BH |
883 | return 0; |
884 | } | |
885 | ||
886 | static struct irq_host_ops mpic_host_ops = { | |
887 | .match = mpic_host_match, | |
888 | .map = mpic_host_map, | |
889 | .xlate = mpic_host_xlate, | |
890 | }; | |
891 | ||
14cf11af PM |
892 | /* |
893 | * Exported functions | |
894 | */ | |
895 | ||
0ebfff14 | 896 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 897 | phys_addr_t phys_addr, |
14cf11af PM |
898 | unsigned int flags, |
899 | unsigned int isu_size, | |
14cf11af | 900 | unsigned int irq_count, |
14cf11af PM |
901 | const char *name) |
902 | { | |
903 | struct mpic *mpic; | |
904 | u32 reg; | |
905 | const char *vers; | |
906 | int i; | |
a959ff56 | 907 | u64 paddr = phys_addr; |
14cf11af PM |
908 | |
909 | mpic = alloc_bootmem(sizeof(struct mpic)); | |
910 | if (mpic == NULL) | |
911 | return NULL; | |
912 | ||
14cf11af PM |
913 | memset(mpic, 0, sizeof(struct mpic)); |
914 | mpic->name = name; | |
0ebfff14 | 915 | mpic->of_node = node ? of_node_get(node) : NULL; |
14cf11af | 916 | |
0ebfff14 BH |
917 | mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 256, |
918 | &mpic_host_ops, | |
919 | MPIC_VEC_SPURRIOUS); | |
920 | if (mpic->irqhost == NULL) { | |
921 | of_node_put(node); | |
922 | return NULL; | |
923 | } | |
924 | ||
925 | mpic->irqhost->host_data = mpic; | |
b9e5b4e6 | 926 | mpic->hc_irq = mpic_irq_chip; |
14cf11af | 927 | mpic->hc_irq.typename = name; |
14cf11af PM |
928 | if (flags & MPIC_PRIMARY) |
929 | mpic->hc_irq.set_affinity = mpic_set_affinity; | |
b9e5b4e6 BH |
930 | #ifdef CONFIG_MPIC_BROKEN_U3 |
931 | mpic->hc_ht_irq = mpic_irq_ht_chip; | |
932 | mpic->hc_ht_irq.typename = name; | |
933 | if (flags & MPIC_PRIMARY) | |
934 | mpic->hc_ht_irq.set_affinity = mpic_set_affinity; | |
935 | #endif /* CONFIG_MPIC_BROKEN_U3 */ | |
fbf0274e | 936 | |
14cf11af | 937 | #ifdef CONFIG_SMP |
b9e5b4e6 | 938 | mpic->hc_ipi = mpic_ipi_chip; |
0ebfff14 | 939 | mpic->hc_ipi.typename = name; |
14cf11af PM |
940 | #endif /* CONFIG_SMP */ |
941 | ||
942 | mpic->flags = flags; | |
943 | mpic->isu_size = isu_size; | |
14cf11af | 944 | mpic->irq_count = irq_count; |
14cf11af | 945 | mpic->num_sources = 0; /* so far */ |
14cf11af | 946 | |
a959ff56 BH |
947 | /* Check for "big-endian" in device-tree */ |
948 | if (node && get_property(node, "big-endian", NULL) != NULL) | |
949 | mpic->flags |= MPIC_BIG_ENDIAN; | |
950 | ||
951 | ||
7233593b ZR |
952 | #ifdef CONFIG_MPIC_WEIRD |
953 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
954 | #endif | |
955 | ||
fbf0274e BH |
956 | /* default register type */ |
957 | mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? | |
958 | mpic_access_mmio_be : mpic_access_mmio_le; | |
959 | ||
a959ff56 BH |
960 | /* If no physical address is passed in, a device-node is mandatory */ |
961 | BUG_ON(paddr == 0 && node == NULL); | |
962 | ||
963 | /* If no physical address passed in, check if it's dcr based */ | |
964 | if (paddr == 0 && get_property(node, "dcr-reg", NULL) != NULL) | |
965 | mpic->flags |= MPIC_USES_DCR; | |
966 | ||
fbf0274e BH |
967 | #ifdef CONFIG_PPC_DCR |
968 | if (mpic->flags & MPIC_USES_DCR) { | |
969 | const u32 *dbasep; | |
a959ff56 | 970 | dbasep = get_property(node, "dcr-reg", NULL); |
fbf0274e BH |
971 | BUG_ON(dbasep == NULL); |
972 | mpic->dcr_base = *dbasep; | |
973 | mpic->reg_type = mpic_access_dcr; | |
974 | } | |
975 | #else | |
976 | BUG_ON (mpic->flags & MPIC_USES_DCR); | |
977 | #endif /* CONFIG_PPC_DCR */ | |
978 | ||
a959ff56 BH |
979 | /* If the MPIC is not DCR based, and no physical address was passed |
980 | * in, try to obtain one | |
981 | */ | |
982 | if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { | |
983 | const u32 *reg; | |
984 | reg = get_property(node, "reg", NULL); | |
985 | BUG_ON(reg == NULL); | |
986 | paddr = of_translate_address(node, reg); | |
987 | BUG_ON(paddr == OF_BAD_ADDR); | |
988 | } | |
989 | ||
14cf11af | 990 | /* Map the global registers */ |
a959ff56 BH |
991 | mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
992 | mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
993 | |
994 | /* Reset */ | |
995 | if (flags & MPIC_WANTS_RESET) { | |
7233593b ZR |
996 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
997 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 998 | | MPIC_GREG_GCONF_RESET); |
7233593b | 999 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1000 | & MPIC_GREG_GCONF_RESET) |
1001 | mb(); | |
1002 | } | |
1003 | ||
1004 | /* Read feature register, calculate num CPUs and, for non-ISU | |
1005 | * MPICs, num sources as well. On ISU MPICs, sources are counted | |
1006 | * as ISUs are added | |
1007 | */ | |
7233593b | 1008 | reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
14cf11af PM |
1009 | mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) |
1010 | >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; | |
1011 | if (isu_size == 0) | |
1012 | mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1013 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
1014 | ||
1015 | /* Map the per-CPU registers */ | |
1016 | for (i = 0; i < mpic->num_cpus; i++) { | |
a959ff56 | 1017 | mpic_map(mpic, paddr, &mpic->cpuregs[i], |
fbf0274e BH |
1018 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
1019 | 0x1000); | |
14cf11af PM |
1020 | } |
1021 | ||
1022 | /* Initialize main ISU if none provided */ | |
1023 | if (mpic->isu_size == 0) { | |
1024 | mpic->isu_size = mpic->num_sources; | |
a959ff56 | 1025 | mpic_map(mpic, paddr, &mpic->isus[0], |
fbf0274e | 1026 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1027 | } |
1028 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1029 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1030 | ||
1031 | /* Display version */ | |
1032 | switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { | |
1033 | case 1: | |
1034 | vers = "1.0"; | |
1035 | break; | |
1036 | case 2: | |
1037 | vers = "1.2"; | |
1038 | break; | |
1039 | case 3: | |
1040 | vers = "1.3"; | |
1041 | break; | |
1042 | default: | |
1043 | vers = "<unknown>"; | |
1044 | break; | |
1045 | } | |
a959ff56 BH |
1046 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1047 | " max %d CPUs\n", | |
1048 | name, vers, (unsigned long long)paddr, mpic->num_cpus); | |
1049 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", | |
1050 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1051 | |
1052 | mpic->next = mpics; | |
1053 | mpics = mpic; | |
1054 | ||
0ebfff14 | 1055 | if (flags & MPIC_PRIMARY) { |
14cf11af | 1056 | mpic_primary = mpic; |
0ebfff14 BH |
1057 | irq_set_default_host(mpic->irqhost); |
1058 | } | |
14cf11af PM |
1059 | |
1060 | return mpic; | |
1061 | } | |
1062 | ||
1063 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1064 | phys_addr_t paddr) |
14cf11af PM |
1065 | { |
1066 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1067 | ||
1068 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1069 | ||
a959ff56 | 1070 | mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, |
fbf0274e | 1071 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1072 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1073 | mpic->num_sources = isu_first + mpic->isu_size; | |
1074 | } | |
1075 | ||
0ebfff14 BH |
1076 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1077 | { | |
1078 | mpic->senses = senses; | |
1079 | mpic->senses_count = count; | |
1080 | } | |
1081 | ||
14cf11af PM |
1082 | void __init mpic_init(struct mpic *mpic) |
1083 | { | |
1084 | int i; | |
1085 | ||
1086 | BUG_ON(mpic->num_sources == 0); | |
0ebfff14 BH |
1087 | WARN_ON(mpic->num_sources > MPIC_VEC_IPI_0); |
1088 | ||
1089 | /* Sanitize source count */ | |
1090 | if (mpic->num_sources > MPIC_VEC_IPI_0) | |
1091 | mpic->num_sources = MPIC_VEC_IPI_0; | |
14cf11af PM |
1092 | |
1093 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1094 | ||
1095 | /* Set current processor priority to max */ | |
7233593b | 1096 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af PM |
1097 | |
1098 | /* Initialize timers: just disable them all */ | |
1099 | for (i = 0; i < 4; i++) { | |
1100 | mpic_write(mpic->tmregs, | |
7233593b ZR |
1101 | i * MPIC_INFO(TIMER_STRIDE) + |
1102 | MPIC_INFO(TIMER_DESTINATION), 0); | |
14cf11af | 1103 | mpic_write(mpic->tmregs, |
7233593b ZR |
1104 | i * MPIC_INFO(TIMER_STRIDE) + |
1105 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af PM |
1106 | MPIC_VECPRI_MASK | |
1107 | (MPIC_VEC_TIMER_0 + i)); | |
1108 | } | |
1109 | ||
1110 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1111 | mpic_test_broken_ipi(mpic); | |
1112 | for (i = 0; i < 4; i++) { | |
1113 | mpic_ipi_write(i, | |
1114 | MPIC_VECPRI_MASK | | |
1115 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
1116 | (MPIC_VEC_IPI_0 + i)); | |
14cf11af PM |
1117 | } |
1118 | ||
1119 | /* Initialize interrupt sources */ | |
1120 | if (mpic->irq_count == 0) | |
1121 | mpic->irq_count = mpic->num_sources; | |
1122 | ||
1beb6a7d | 1123 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af PM |
1124 | DBG("MPIC flags: %x\n", mpic->flags); |
1125 | if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY)) | |
b9e5b4e6 | 1126 | mpic_scan_ht_pics(mpic); |
14cf11af PM |
1127 | |
1128 | for (i = 0; i < mpic->num_sources; i++) { | |
1129 | /* start with vector = source number, and masked */ | |
6e99e458 BH |
1130 | u32 vecpri = MPIC_VECPRI_MASK | i | |
1131 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1132 | |
14cf11af | 1133 | /* init hw */ |
7233593b ZR |
1134 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
1135 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
14cf11af | 1136 | 1 << hard_smp_processor_id()); |
14cf11af PM |
1137 | } |
1138 | ||
1139 | /* Init spurrious vector */ | |
7233593b | 1140 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS); |
14cf11af | 1141 | |
7233593b ZR |
1142 | /* Disable 8259 passthrough, if supported */ |
1143 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1144 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1145 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1146 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af PM |
1147 | |
1148 | /* Set current processor priority to 0 */ | |
7233593b | 1149 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af PM |
1150 | } |
1151 | ||
868ea0c9 MG |
1152 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1153 | { | |
1154 | u32 v; | |
1155 | ||
1156 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1157 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1158 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1159 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1160 | } | |
14cf11af | 1161 | |
868ea0c9 MG |
1162 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1163 | { | |
ba1826e5 | 1164 | unsigned long flags; |
868ea0c9 MG |
1165 | u32 v; |
1166 | ||
ba1826e5 | 1167 | spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1168 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1169 | if (enable) | |
1170 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1171 | else | |
1172 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1173 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
ba1826e5 | 1174 | spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1175 | } |
14cf11af PM |
1176 | |
1177 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1178 | { | |
1179 | int is_ipi; | |
1180 | struct mpic *mpic = mpic_find(irq, &is_ipi); | |
0ebfff14 | 1181 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
1182 | unsigned long flags; |
1183 | u32 reg; | |
1184 | ||
1185 | spin_lock_irqsave(&mpic_lock, flags); | |
1186 | if (is_ipi) { | |
0ebfff14 | 1187 | reg = mpic_ipi_read(src - MPIC_VEC_IPI_0) & |
e5356640 | 1188 | ~MPIC_VECPRI_PRIORITY_MASK; |
0ebfff14 | 1189 | mpic_ipi_write(src - MPIC_VEC_IPI_0, |
14cf11af PM |
1190 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1191 | } else { | |
7233593b | 1192 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1193 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1194 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1195 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1196 | } | |
1197 | spin_unlock_irqrestore(&mpic_lock, flags); | |
1198 | } | |
1199 | ||
1200 | unsigned int mpic_irq_get_priority(unsigned int irq) | |
1201 | { | |
1202 | int is_ipi; | |
1203 | struct mpic *mpic = mpic_find(irq, &is_ipi); | |
0ebfff14 | 1204 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
1205 | unsigned long flags; |
1206 | u32 reg; | |
1207 | ||
1208 | spin_lock_irqsave(&mpic_lock, flags); | |
1209 | if (is_ipi) | |
0ebfff14 | 1210 | reg = mpic_ipi_read(src = MPIC_VEC_IPI_0); |
14cf11af | 1211 | else |
7233593b | 1212 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
14cf11af PM |
1213 | spin_unlock_irqrestore(&mpic_lock, flags); |
1214 | return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; | |
1215 | } | |
1216 | ||
1217 | void mpic_setup_this_cpu(void) | |
1218 | { | |
1219 | #ifdef CONFIG_SMP | |
1220 | struct mpic *mpic = mpic_primary; | |
1221 | unsigned long flags; | |
1222 | u32 msk = 1 << hard_smp_processor_id(); | |
1223 | unsigned int i; | |
1224 | ||
1225 | BUG_ON(mpic == NULL); | |
1226 | ||
1227 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1228 | ||
1229 | spin_lock_irqsave(&mpic_lock, flags); | |
1230 | ||
1231 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1232 | * until changed via /proc. That's how it's done on x86. If we want | |
1233 | * it differently, then we should make sure we also change the default | |
a53da52f | 1234 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1235 | */ |
1236 | if (distribute_irqs) { | |
1237 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1238 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1239 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1240 | } |
1241 | ||
1242 | /* Set current processor priority to 0 */ | |
7233593b | 1243 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af PM |
1244 | |
1245 | spin_unlock_irqrestore(&mpic_lock, flags); | |
1246 | #endif /* CONFIG_SMP */ | |
1247 | } | |
1248 | ||
1249 | int mpic_cpu_get_priority(void) | |
1250 | { | |
1251 | struct mpic *mpic = mpic_primary; | |
1252 | ||
7233593b | 1253 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1254 | } |
1255 | ||
1256 | void mpic_cpu_set_priority(int prio) | |
1257 | { | |
1258 | struct mpic *mpic = mpic_primary; | |
1259 | ||
1260 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1261 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1262 | } |
1263 | ||
1264 | /* | |
1265 | * XXX: someone who knows mpic should check this. | |
1266 | * do we need to eoi the ipi including for kexec cpu here (see xics comments)? | |
1267 | * or can we reset the mpic in the new kernel? | |
1268 | */ | |
1269 | void mpic_teardown_this_cpu(int secondary) | |
1270 | { | |
1271 | struct mpic *mpic = mpic_primary; | |
1272 | unsigned long flags; | |
1273 | u32 msk = 1 << hard_smp_processor_id(); | |
1274 | unsigned int i; | |
1275 | ||
1276 | BUG_ON(mpic == NULL); | |
1277 | ||
1278 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1279 | spin_lock_irqsave(&mpic_lock, flags); | |
1280 | ||
1281 | /* let the mpic know we don't want intrs. */ | |
1282 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1283 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1284 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1285 | |
1286 | /* Set current processor priority to max */ | |
7233593b | 1287 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af PM |
1288 | |
1289 | spin_unlock_irqrestore(&mpic_lock, flags); | |
1290 | } | |
1291 | ||
1292 | ||
1293 | void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) | |
1294 | { | |
1295 | struct mpic *mpic = mpic_primary; | |
1296 | ||
1297 | BUG_ON(mpic == NULL); | |
1298 | ||
1beb6a7d | 1299 | #ifdef DEBUG_IPI |
14cf11af | 1300 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); |
1beb6a7d | 1301 | #endif |
14cf11af | 1302 | |
7233593b ZR |
1303 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + |
1304 | ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), | |
14cf11af PM |
1305 | mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); |
1306 | } | |
1307 | ||
35a84c2f | 1308 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
14cf11af | 1309 | { |
0ebfff14 | 1310 | u32 src; |
14cf11af | 1311 | |
7233593b | 1312 | src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1313 | #ifdef DEBUG_LOW |
0ebfff14 | 1314 | DBG("%s: get_one_irq(): %d\n", mpic->name, src); |
1beb6a7d | 1315 | #endif |
0ebfff14 BH |
1316 | if (unlikely(src == MPIC_VEC_SPURRIOUS)) |
1317 | return NO_IRQ; | |
1318 | return irq_linear_revmap(mpic->irqhost, src); | |
14cf11af PM |
1319 | } |
1320 | ||
35a84c2f | 1321 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1322 | { |
1323 | struct mpic *mpic = mpic_primary; | |
1324 | ||
1325 | BUG_ON(mpic == NULL); | |
1326 | ||
35a84c2f | 1327 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1328 | } |
1329 | ||
1330 | ||
1331 | #ifdef CONFIG_SMP | |
1332 | void mpic_request_ipis(void) | |
1333 | { | |
1334 | struct mpic *mpic = mpic_primary; | |
0ebfff14 BH |
1335 | int i; |
1336 | static char *ipi_names[] = { | |
1337 | "IPI0 (call function)", | |
1338 | "IPI1 (reschedule)", | |
1339 | "IPI2 (unused)", | |
1340 | "IPI3 (debugger break)", | |
1341 | }; | |
14cf11af | 1342 | BUG_ON(mpic == NULL); |
14cf11af | 1343 | |
0ebfff14 BH |
1344 | printk(KERN_INFO "mpic: requesting IPIs ... \n"); |
1345 | ||
1346 | for (i = 0; i < 4; i++) { | |
1347 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
6e99e458 | 1348 | MPIC_VEC_IPI_0 + i); |
0ebfff14 BH |
1349 | if (vipi == NO_IRQ) { |
1350 | printk(KERN_ERR "Failed to map IPI %d\n", i); | |
1351 | break; | |
1352 | } | |
1353 | request_irq(vipi, mpic_ipi_action, IRQF_DISABLED, | |
1354 | ipi_names[i], mpic); | |
1355 | } | |
14cf11af | 1356 | } |
a9c59264 PM |
1357 | |
1358 | void smp_mpic_message_pass(int target, int msg) | |
1359 | { | |
1360 | /* make sure we're sending something that translates to an IPI */ | |
1361 | if ((unsigned int)msg > 3) { | |
1362 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1363 | smp_processor_id(), msg); | |
1364 | return; | |
1365 | } | |
1366 | switch (target) { | |
1367 | case MSG_ALL: | |
1368 | mpic_send_ipi(msg, 0xffffffff); | |
1369 | break; | |
1370 | case MSG_ALL_BUT_SELF: | |
1371 | mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); | |
1372 | break; | |
1373 | default: | |
1374 | mpic_send_ipi(msg, 1 << target); | |
1375 | break; | |
1376 | } | |
1377 | } | |
14cf11af | 1378 | #endif /* CONFIG_SMP */ |