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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file COPYING in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | ||
15 | #undef DEBUG | |
1beb6a7d BH |
16 | #undef DEBUG_IPI |
17 | #undef DEBUG_IRQ | |
18 | #undef DEBUG_LOW | |
14cf11af | 19 | |
14cf11af PM |
20 | #include <linux/types.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/bootmem.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/pci.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
14cf11af PM |
30 | |
31 | #include <asm/ptrace.h> | |
32 | #include <asm/signal.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/machdep.h> | |
37 | #include <asm/mpic.h> | |
38 | #include <asm/smp.h> | |
39 | ||
a7de7c74 ME |
40 | #include "mpic.h" |
41 | ||
14cf11af PM |
42 | #ifdef DEBUG |
43 | #define DBG(fmt...) printk(fmt) | |
44 | #else | |
45 | #define DBG(fmt...) | |
46 | #endif | |
47 | ||
48 | static struct mpic *mpics; | |
49 | static struct mpic *mpic_primary; | |
203041ad | 50 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
14cf11af | 51 | |
c0c0d996 | 52 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
53 | #ifdef CONFIG_IRQ_ALL_CPUS |
54 | #define distribute_irqs (1) | |
55 | #else | |
56 | #define distribute_irqs (0) | |
57 | #endif | |
c0c0d996 | 58 | #endif |
14cf11af | 59 | |
7233593b ZR |
60 | #ifdef CONFIG_MPIC_WEIRD |
61 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
62 | [0] = { /* Original OpenPIC compatible MPIC */ | |
63 | MPIC_GREG_BASE, | |
64 | MPIC_GREG_FEATURE_0, | |
65 | MPIC_GREG_GLOBAL_CONF_0, | |
66 | MPIC_GREG_VENDOR_ID, | |
67 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
68 | MPIC_GREG_IPI_STRIDE, | |
69 | MPIC_GREG_SPURIOUS, | |
70 | MPIC_GREG_TIMER_FREQ, | |
71 | ||
72 | MPIC_TIMER_BASE, | |
73 | MPIC_TIMER_STRIDE, | |
74 | MPIC_TIMER_CURRENT_CNT, | |
75 | MPIC_TIMER_BASE_CNT, | |
76 | MPIC_TIMER_VECTOR_PRI, | |
77 | MPIC_TIMER_DESTINATION, | |
78 | ||
79 | MPIC_CPU_BASE, | |
80 | MPIC_CPU_STRIDE, | |
81 | MPIC_CPU_IPI_DISPATCH_0, | |
82 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
83 | MPIC_CPU_CURRENT_TASK_PRI, | |
84 | MPIC_CPU_WHOAMI, | |
85 | MPIC_CPU_INTACK, | |
86 | MPIC_CPU_EOI, | |
f365355e | 87 | MPIC_CPU_MCACK, |
7233593b ZR |
88 | |
89 | MPIC_IRQ_BASE, | |
90 | MPIC_IRQ_STRIDE, | |
91 | MPIC_IRQ_VECTOR_PRI, | |
92 | MPIC_VECPRI_VECTOR_MASK, | |
93 | MPIC_VECPRI_POLARITY_POSITIVE, | |
94 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
95 | MPIC_VECPRI_SENSE_LEVEL, | |
96 | MPIC_VECPRI_SENSE_EDGE, | |
97 | MPIC_VECPRI_POLARITY_MASK, | |
98 | MPIC_VECPRI_SENSE_MASK, | |
99 | MPIC_IRQ_DESTINATION | |
100 | }, | |
101 | [1] = { /* Tsi108/109 PIC */ | |
102 | TSI108_GREG_BASE, | |
103 | TSI108_GREG_FEATURE_0, | |
104 | TSI108_GREG_GLOBAL_CONF_0, | |
105 | TSI108_GREG_VENDOR_ID, | |
106 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
107 | TSI108_GREG_IPI_STRIDE, | |
108 | TSI108_GREG_SPURIOUS, | |
109 | TSI108_GREG_TIMER_FREQ, | |
110 | ||
111 | TSI108_TIMER_BASE, | |
112 | TSI108_TIMER_STRIDE, | |
113 | TSI108_TIMER_CURRENT_CNT, | |
114 | TSI108_TIMER_BASE_CNT, | |
115 | TSI108_TIMER_VECTOR_PRI, | |
116 | TSI108_TIMER_DESTINATION, | |
117 | ||
118 | TSI108_CPU_BASE, | |
119 | TSI108_CPU_STRIDE, | |
120 | TSI108_CPU_IPI_DISPATCH_0, | |
121 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
122 | TSI108_CPU_CURRENT_TASK_PRI, | |
123 | TSI108_CPU_WHOAMI, | |
124 | TSI108_CPU_INTACK, | |
125 | TSI108_CPU_EOI, | |
f365355e | 126 | TSI108_CPU_MCACK, |
7233593b ZR |
127 | |
128 | TSI108_IRQ_BASE, | |
129 | TSI108_IRQ_STRIDE, | |
130 | TSI108_IRQ_VECTOR_PRI, | |
131 | TSI108_VECPRI_VECTOR_MASK, | |
132 | TSI108_VECPRI_POLARITY_POSITIVE, | |
133 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
134 | TSI108_VECPRI_SENSE_LEVEL, | |
135 | TSI108_VECPRI_SENSE_EDGE, | |
136 | TSI108_VECPRI_POLARITY_MASK, | |
137 | TSI108_VECPRI_SENSE_MASK, | |
138 | TSI108_IRQ_DESTINATION | |
139 | }, | |
140 | }; | |
141 | ||
142 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
143 | ||
144 | #else /* CONFIG_MPIC_WEIRD */ | |
145 | ||
146 | #define MPIC_INFO(name) MPIC_##name | |
147 | ||
148 | #endif /* CONFIG_MPIC_WEIRD */ | |
149 | ||
d6a2639b MI |
150 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
151 | { | |
152 | unsigned int cpu = 0; | |
153 | ||
154 | if (mpic->flags & MPIC_PRIMARY) | |
155 | cpu = hard_smp_processor_id(); | |
156 | ||
157 | return cpu; | |
158 | } | |
159 | ||
14cf11af PM |
160 | /* |
161 | * Register accessor functions | |
162 | */ | |
163 | ||
164 | ||
fbf0274e BH |
165 | static inline u32 _mpic_read(enum mpic_reg_type type, |
166 | struct mpic_reg_bank *rb, | |
167 | unsigned int reg) | |
14cf11af | 168 | { |
fbf0274e BH |
169 | switch(type) { |
170 | #ifdef CONFIG_PPC_DCR | |
171 | case mpic_access_dcr: | |
83f34df4 | 172 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
173 | #endif |
174 | case mpic_access_mmio_be: | |
175 | return in_be32(rb->base + (reg >> 2)); | |
176 | case mpic_access_mmio_le: | |
177 | default: | |
178 | return in_le32(rb->base + (reg >> 2)); | |
179 | } | |
14cf11af PM |
180 | } |
181 | ||
fbf0274e BH |
182 | static inline void _mpic_write(enum mpic_reg_type type, |
183 | struct mpic_reg_bank *rb, | |
184 | unsigned int reg, u32 value) | |
14cf11af | 185 | { |
fbf0274e BH |
186 | switch(type) { |
187 | #ifdef CONFIG_PPC_DCR | |
188 | case mpic_access_dcr: | |
d9d1063d JB |
189 | dcr_write(rb->dhost, reg, value); |
190 | break; | |
fbf0274e BH |
191 | #endif |
192 | case mpic_access_mmio_be: | |
d9d1063d JB |
193 | out_be32(rb->base + (reg >> 2), value); |
194 | break; | |
fbf0274e BH |
195 | case mpic_access_mmio_le: |
196 | default: | |
d9d1063d JB |
197 | out_le32(rb->base + (reg >> 2), value); |
198 | break; | |
fbf0274e | 199 | } |
14cf11af PM |
200 | } |
201 | ||
202 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
203 | { | |
fbf0274e | 204 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
205 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
206 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 207 | |
fbf0274e BH |
208 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
209 | type = mpic_access_mmio_be; | |
210 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
211 | } |
212 | ||
213 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
214 | { | |
7233593b ZR |
215 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
216 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 217 | |
fbf0274e | 218 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
219 | } |
220 | ||
221 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) | |
222 | { | |
d6a2639b | 223 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 224 | |
fbf0274e | 225 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
226 | } |
227 | ||
228 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
229 | { | |
d6a2639b | 230 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 231 | |
fbf0274e | 232 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
233 | } |
234 | ||
235 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
236 | { | |
237 | unsigned int isu = src_no >> mpic->isu_shift; | |
238 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 239 | unsigned int val; |
14cf11af | 240 | |
11a6b292 ME |
241 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
242 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
243 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
244 | if (reg == 0) | |
11a6b292 ME |
245 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
246 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 247 | #endif |
11a6b292 | 248 | return val; |
14cf11af PM |
249 | } |
250 | ||
251 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
252 | unsigned int reg, u32 value) | |
253 | { | |
254 | unsigned int isu = src_no >> mpic->isu_shift; | |
255 | unsigned int idx = src_no & mpic->isu_mask; | |
256 | ||
fbf0274e | 257 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 258 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
259 | |
260 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
261 | if (reg == 0) | |
11a6b292 ME |
262 | mpic->isu_reg0_shadow[src_no] = |
263 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 264 | #endif |
14cf11af PM |
265 | } |
266 | ||
fbf0274e BH |
267 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
268 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
269 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
270 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
271 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) | |
272 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
273 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
274 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
275 | ||
276 | ||
277 | /* | |
278 | * Low level utility functions | |
279 | */ | |
280 | ||
281 | ||
c51a3fdc | 282 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
283 | struct mpic_reg_bank *rb, unsigned int offset, |
284 | unsigned int size) | |
285 | { | |
286 | rb->base = ioremap(phys_addr + offset, size); | |
287 | BUG_ON(rb->base == NULL); | |
288 | } | |
289 | ||
290 | #ifdef CONFIG_PPC_DCR | |
5a2642f6 BH |
291 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
292 | struct mpic_reg_bank *rb, | |
fbf0274e BH |
293 | unsigned int offset, unsigned int size) |
294 | { | |
0411a5e2 ME |
295 | const u32 *dbasep; |
296 | ||
5a2642f6 | 297 | dbasep = of_get_property(node, "dcr-reg", NULL); |
0411a5e2 | 298 | |
5a2642f6 | 299 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
fbf0274e BH |
300 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
301 | } | |
302 | ||
5a2642f6 BH |
303 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
304 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, | |
305 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
306 | { |
307 | if (mpic->flags & MPIC_USES_DCR) | |
5a2642f6 | 308 | _mpic_map_dcr(mpic, node, rb, offset, size); |
fbf0274e BH |
309 | else |
310 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
311 | } | |
312 | #else /* CONFIG_PPC_DCR */ | |
5a2642f6 | 313 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
314 | #endif /* !CONFIG_PPC_DCR */ |
315 | ||
316 | ||
14cf11af PM |
317 | |
318 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
319 | * reads from IPI registers | |
320 | */ | |
321 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
322 | { | |
323 | u32 r; | |
324 | ||
7233593b ZR |
325 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
326 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
327 | |
328 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
329 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
330 | mpic->flags |= MPIC_BROKEN_IPI; | |
331 | } | |
332 | } | |
333 | ||
6cfef5b2 | 334 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
335 | |
336 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
337 | * to force the edge setting on the MPIC and do the ack workaround. | |
338 | */ | |
1beb6a7d | 339 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 340 | { |
1beb6a7d | 341 | if (source >= 128 || !mpic->fixups) |
14cf11af | 342 | return 0; |
1beb6a7d | 343 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
344 | } |
345 | ||
c4b22f26 | 346 | |
1beb6a7d | 347 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 348 | { |
1beb6a7d | 349 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 350 | |
1beb6a7d BH |
351 | if (fixup->applebase) { |
352 | unsigned int soff = (fixup->index >> 3) & ~3; | |
353 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
354 | writel(mask, fixup->applebase + soff); | |
355 | } else { | |
203041ad | 356 | raw_spin_lock(&mpic->fixup_lock); |
1beb6a7d BH |
357 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
358 | writel(fixup->data, fixup->base + 4); | |
203041ad | 359 | raw_spin_unlock(&mpic->fixup_lock); |
1beb6a7d | 360 | } |
14cf11af PM |
361 | } |
362 | ||
1beb6a7d | 363 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
24a3f2e8 | 364 | bool level) |
1beb6a7d BH |
365 | { |
366 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
367 | unsigned long flags; | |
368 | u32 tmp; | |
369 | ||
370 | if (fixup->base == NULL) | |
371 | return; | |
372 | ||
24a3f2e8 TG |
373 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
374 | source, fixup->index); | |
203041ad | 375 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
376 | /* Enable and configure */ |
377 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
378 | tmp = readl(fixup->base + 4); | |
379 | tmp &= ~(0x23U); | |
24a3f2e8 | 380 | if (level) |
1beb6a7d BH |
381 | tmp |= 0x22; |
382 | writel(tmp, fixup->base + 4); | |
203041ad | 383 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
384 | |
385 | #ifdef CONFIG_PM | |
386 | /* use the lowest bit inverted to the actual HW, | |
387 | * set if this fixup was enabled, clear otherwise */ | |
388 | mpic->save_data[source].fixup_data = tmp | 1; | |
389 | #endif | |
1beb6a7d BH |
390 | } |
391 | ||
24a3f2e8 | 392 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
1beb6a7d BH |
393 | { |
394 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
395 | unsigned long flags; | |
396 | u32 tmp; | |
397 | ||
398 | if (fixup->base == NULL) | |
399 | return; | |
400 | ||
24a3f2e8 | 401 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
1beb6a7d BH |
402 | |
403 | /* Disable */ | |
203041ad | 404 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
405 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
406 | tmp = readl(fixup->base + 4); | |
72b13819 | 407 | tmp |= 1; |
1beb6a7d | 408 | writel(tmp, fixup->base + 4); |
203041ad | 409 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
410 | |
411 | #ifdef CONFIG_PM | |
412 | /* use the lowest bit inverted to the actual HW, | |
413 | * set if this fixup was enabled, clear otherwise */ | |
414 | mpic->save_data[source].fixup_data = tmp & ~1; | |
415 | #endif | |
1beb6a7d | 416 | } |
14cf11af | 417 | |
812fd1fd ME |
418 | #ifdef CONFIG_PCI_MSI |
419 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
420 | unsigned int devfn) | |
421 | { | |
422 | u8 __iomem *base; | |
423 | u8 pos, flags; | |
424 | u64 addr = 0; | |
425 | ||
426 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
427 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
428 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
429 | if (id == PCI_CAP_ID_HT) { | |
430 | id = readb(devbase + pos + 3); | |
431 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
432 | break; | |
433 | } | |
434 | } | |
435 | ||
436 | if (pos == 0) | |
437 | return; | |
438 | ||
439 | base = devbase + pos; | |
440 | ||
441 | flags = readb(base + HT_MSI_FLAGS); | |
442 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
443 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
444 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
445 | } | |
446 | ||
fe333321 | 447 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
448 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
449 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
450 | ||
451 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
452 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
453 | } | |
454 | #else | |
455 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
456 | unsigned int devfn) | |
457 | { | |
458 | return; | |
459 | } | |
460 | #endif | |
461 | ||
1beb6a7d BH |
462 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
463 | unsigned int devfn, u32 vdid) | |
14cf11af | 464 | { |
c4b22f26 | 465 | int i, irq, n; |
1beb6a7d | 466 | u8 __iomem *base; |
14cf11af | 467 | u32 tmp; |
c4b22f26 | 468 | u8 pos; |
14cf11af | 469 | |
1beb6a7d BH |
470 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
471 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
472 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 473 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 474 | id = readb(devbase + pos + 3); |
beb7cc82 | 475 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
476 | break; |
477 | } | |
14cf11af | 478 | } |
c4b22f26 SB |
479 | if (pos == 0) |
480 | return; | |
481 | ||
1beb6a7d BH |
482 | base = devbase + pos; |
483 | writeb(0x01, base + 2); | |
484 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 485 | |
1beb6a7d BH |
486 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
487 | " has %d irqs\n", | |
488 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
489 | |
490 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
491 | writeb(0x10 + 2 * i, base + 2); |
492 | tmp = readl(base + 4); | |
14cf11af | 493 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
494 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
495 | /* mask it , will be unmasked later */ | |
496 | tmp |= 0x1; | |
497 | writel(tmp, base + 4); | |
498 | mpic->fixups[irq].index = i; | |
499 | mpic->fixups[irq].base = base; | |
500 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
501 | if ((vdid & 0xffff) == 0x106b) | |
502 | mpic->fixups[irq].applebase = devbase + 0x60; | |
503 | else | |
504 | mpic->fixups[irq].applebase = NULL; | |
505 | writeb(0x11 + 2 * i, base + 2); | |
506 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
507 | } |
508 | } | |
509 | ||
c4b22f26 | 510 | |
1beb6a7d | 511 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
512 | { |
513 | unsigned int devfn; | |
514 | u8 __iomem *cfgspace; | |
515 | ||
1beb6a7d | 516 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
517 | |
518 | /* Allocate fixups array */ | |
ea96025a | 519 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 520 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
521 | |
522 | /* Init spinlock */ | |
203041ad | 523 | raw_spin_lock_init(&mpic->fixup_lock); |
14cf11af | 524 | |
c4b22f26 SB |
525 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
526 | * so we only need to map 64kB. | |
14cf11af | 527 | */ |
c4b22f26 | 528 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
529 | BUG_ON(cfgspace == NULL); |
530 | ||
1beb6a7d BH |
531 | /* Now we scan all slots. We do a very quick scan, we read the header |
532 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 533 | */ |
c4b22f26 | 534 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
535 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
536 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
537 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 538 | u16 s; |
14cf11af PM |
539 | |
540 | DBG("devfn %x, l: %x\n", devfn, l); | |
541 | ||
542 | /* If no device, skip */ | |
543 | if (l == 0xffffffff || l == 0x00000000 || | |
544 | l == 0x0000ffff || l == 0xffff0000) | |
545 | goto next; | |
1beb6a7d BH |
546 | /* Check if is supports capability lists */ |
547 | s = readw(devbase + PCI_STATUS); | |
548 | if (!(s & PCI_STATUS_CAP_LIST)) | |
549 | goto next; | |
14cf11af | 550 | |
1beb6a7d | 551 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 552 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 553 | |
14cf11af PM |
554 | next: |
555 | /* next device, if function 0 */ | |
c4b22f26 | 556 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
557 | devfn += 7; |
558 | } | |
559 | } | |
560 | ||
6cfef5b2 | 561 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
562 | |
563 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
564 | { | |
565 | return 0; | |
566 | } | |
567 | ||
568 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
569 | { | |
570 | } | |
571 | ||
6cfef5b2 | 572 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 573 | |
3c10c9c4 | 574 | #ifdef CONFIG_SMP |
2ef613cb | 575 | static int irq_choose_cpu(const struct cpumask *mask) |
3c10c9c4 | 576 | { |
3c10c9c4 KG |
577 | int cpuid; |
578 | ||
38e1313f | 579 | if (cpumask_equal(mask, cpu_all_mask)) { |
2ef613cb | 580 | static int irq_rover = 0; |
203041ad | 581 | static DEFINE_RAW_SPINLOCK(irq_rover_lock); |
3c10c9c4 KG |
582 | unsigned long flags; |
583 | ||
584 | /* Round-robin distribution... */ | |
585 | do_round_robin: | |
203041ad | 586 | raw_spin_lock_irqsave(&irq_rover_lock, flags); |
3c10c9c4 | 587 | |
2ef613cb BH |
588 | irq_rover = cpumask_next(irq_rover, cpu_online_mask); |
589 | if (irq_rover >= nr_cpu_ids) | |
590 | irq_rover = cpumask_first(cpu_online_mask); | |
591 | ||
3c10c9c4 | 592 | cpuid = irq_rover; |
3c10c9c4 | 593 | |
203041ad | 594 | raw_spin_unlock_irqrestore(&irq_rover_lock, flags); |
3c10c9c4 | 595 | } else { |
38e1313f YL |
596 | cpuid = cpumask_first_and(mask, cpu_online_mask); |
597 | if (cpuid >= nr_cpu_ids) | |
3c10c9c4 | 598 | goto do_round_robin; |
3c10c9c4 KG |
599 | } |
600 | ||
7a0d7940 | 601 | return get_hard_smp_processor_id(cpuid); |
3c10c9c4 KG |
602 | } |
603 | #else | |
2ef613cb | 604 | static int irq_choose_cpu(const struct cpumask *mask) |
3c10c9c4 KG |
605 | { |
606 | return hard_smp_processor_id(); | |
607 | } | |
608 | #endif | |
14cf11af PM |
609 | |
610 | /* Find an mpic associated with a given linux interrupt */ | |
d69a78d7 | 611 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 612 | { |
0ebfff14 BH |
613 | if (irq < NUM_ISA_INTERRUPTS) |
614 | return NULL; | |
7df2457d | 615 | |
ec775d0e | 616 | return irq_get_chip_data(irq); |
d69a78d7 | 617 | } |
7df2457d | 618 | |
d69a78d7 TB |
619 | /* Determine if the linux irq is an IPI */ |
620 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) | |
621 | { | |
476eb491 | 622 | unsigned int src = virq_to_hw(irq); |
0ebfff14 | 623 | |
d69a78d7 | 624 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
625 | } |
626 | ||
d69a78d7 | 627 | |
14cf11af PM |
628 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
629 | static inline u32 mpic_physmask(u32 cpumask) | |
630 | { | |
631 | int i; | |
632 | u32 mask = 0; | |
633 | ||
ebc04215 | 634 | for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) |
14cf11af PM |
635 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
636 | return mask; | |
637 | } | |
638 | ||
639 | #ifdef CONFIG_SMP | |
640 | /* Get the mpic structure from the IPI number */ | |
835c0553 | 641 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
14cf11af | 642 | { |
835c0553 | 643 | return irq_data_get_irq_chip_data(d); |
14cf11af PM |
644 | } |
645 | #endif | |
646 | ||
647 | /* Get the mpic structure from the irq number */ | |
648 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
649 | { | |
ec775d0e | 650 | return irq_get_chip_data(irq); |
835c0553 LB |
651 | } |
652 | ||
653 | /* Get the mpic structure from the irq data */ | |
654 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | |
655 | { | |
656 | return irq_data_get_irq_chip_data(d); | |
14cf11af PM |
657 | } |
658 | ||
659 | /* Send an EOI */ | |
660 | static inline void mpic_eoi(struct mpic *mpic) | |
661 | { | |
7233593b ZR |
662 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
663 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
664 | } |
665 | ||
14cf11af PM |
666 | /* |
667 | * Linux descriptor level callbacks | |
668 | */ | |
669 | ||
670 | ||
835c0553 | 671 | void mpic_unmask_irq(struct irq_data *d) |
14cf11af PM |
672 | { |
673 | unsigned int loops = 100000; | |
835c0553 | 674 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 675 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 676 | |
835c0553 | 677 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
14cf11af | 678 | |
7233593b ZR |
679 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
680 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 681 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
682 | /* make sure mask gets to controller before we return to user */ |
683 | do { | |
684 | if (!loops--) { | |
8bfc5e36 SW |
685 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
686 | __func__, src); | |
14cf11af PM |
687 | break; |
688 | } | |
7233593b | 689 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
690 | } |
691 | ||
835c0553 | 692 | void mpic_mask_irq(struct irq_data *d) |
14cf11af PM |
693 | { |
694 | unsigned int loops = 100000; | |
835c0553 | 695 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 696 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 697 | |
835c0553 | 698 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
14cf11af | 699 | |
7233593b ZR |
700 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
701 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 702 | MPIC_VECPRI_MASK); |
14cf11af PM |
703 | |
704 | /* make sure mask gets to controller before we return to user */ | |
705 | do { | |
706 | if (!loops--) { | |
8bfc5e36 SW |
707 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
708 | __func__, src); | |
14cf11af PM |
709 | break; |
710 | } | |
7233593b | 711 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
712 | } |
713 | ||
835c0553 | 714 | void mpic_end_irq(struct irq_data *d) |
1beb6a7d | 715 | { |
835c0553 | 716 | struct mpic *mpic = mpic_from_irq_data(d); |
b9e5b4e6 BH |
717 | |
718 | #ifdef DEBUG_IRQ | |
835c0553 | 719 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
b9e5b4e6 BH |
720 | #endif |
721 | /* We always EOI on end_irq() even for edge interrupts since that | |
722 | * should only lower the priority, the MPIC should have properly | |
723 | * latched another edge interrupt coming in anyway | |
724 | */ | |
725 | ||
726 | mpic_eoi(mpic); | |
727 | } | |
728 | ||
6cfef5b2 | 729 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 730 | |
835c0553 | 731 | static void mpic_unmask_ht_irq(struct irq_data *d) |
b9e5b4e6 | 732 | { |
835c0553 | 733 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 734 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 735 | |
835c0553 | 736 | mpic_unmask_irq(d); |
1beb6a7d | 737 | |
24a3f2e8 | 738 | if (irqd_is_level_type(d)) |
b9e5b4e6 BH |
739 | mpic_ht_end_irq(mpic, src); |
740 | } | |
741 | ||
835c0553 | 742 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
b9e5b4e6 | 743 | { |
835c0553 | 744 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 745 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 746 | |
835c0553 | 747 | mpic_unmask_irq(d); |
24a3f2e8 | 748 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
b9e5b4e6 BH |
749 | |
750 | return 0; | |
1beb6a7d BH |
751 | } |
752 | ||
835c0553 | 753 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
b9e5b4e6 | 754 | { |
835c0553 | 755 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 756 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 757 | |
24a3f2e8 | 758 | mpic_shutdown_ht_interrupt(mpic, src); |
835c0553 | 759 | mpic_mask_irq(d); |
b9e5b4e6 BH |
760 | } |
761 | ||
835c0553 | 762 | static void mpic_end_ht_irq(struct irq_data *d) |
14cf11af | 763 | { |
835c0553 | 764 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 765 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 766 | |
1beb6a7d | 767 | #ifdef DEBUG_IRQ |
835c0553 | 768 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
1beb6a7d | 769 | #endif |
14cf11af PM |
770 | /* We always EOI on end_irq() even for edge interrupts since that |
771 | * should only lower the priority, the MPIC should have properly | |
772 | * latched another edge interrupt coming in anyway | |
773 | */ | |
774 | ||
24a3f2e8 | 775 | if (irqd_is_level_type(d)) |
b9e5b4e6 | 776 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
777 | mpic_eoi(mpic); |
778 | } | |
6cfef5b2 | 779 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 780 | |
14cf11af PM |
781 | #ifdef CONFIG_SMP |
782 | ||
835c0553 | 783 | static void mpic_unmask_ipi(struct irq_data *d) |
14cf11af | 784 | { |
835c0553 | 785 | struct mpic *mpic = mpic_from_ipi(d); |
476eb491 | 786 | unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
14cf11af | 787 | |
835c0553 | 788 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
14cf11af PM |
789 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
790 | } | |
791 | ||
835c0553 | 792 | static void mpic_mask_ipi(struct irq_data *d) |
14cf11af PM |
793 | { |
794 | /* NEVER disable an IPI... that's just plain wrong! */ | |
795 | } | |
796 | ||
835c0553 | 797 | static void mpic_end_ipi(struct irq_data *d) |
14cf11af | 798 | { |
835c0553 | 799 | struct mpic *mpic = mpic_from_ipi(d); |
14cf11af PM |
800 | |
801 | /* | |
802 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
803 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
804 | * applying to them. We EOI them late to avoid re-entering. | |
6714465e | 805 | * We mark IPI's with IRQF_DISABLED as they must run with |
14cf11af PM |
806 | * irqs disabled. |
807 | */ | |
808 | mpic_eoi(mpic); | |
809 | } | |
810 | ||
811 | #endif /* CONFIG_SMP */ | |
812 | ||
835c0553 LB |
813 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
814 | bool force) | |
14cf11af | 815 | { |
835c0553 | 816 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 817 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 818 | |
3c10c9c4 | 819 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 820 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 821 | |
3c10c9c4 KG |
822 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
823 | } else { | |
2a116f3d | 824 | u32 mask = cpumask_bits(cpumask)[0]; |
14cf11af | 825 | |
2a116f3d | 826 | mask &= cpumask_bits(cpu_online_mask)[0]; |
3c10c9c4 KG |
827 | |
828 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
2a116f3d | 829 | mpic_physmask(mask)); |
3c10c9c4 | 830 | } |
d5dedd45 YL |
831 | |
832 | return 0; | |
14cf11af PM |
833 | } |
834 | ||
7233593b | 835 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 836 | { |
0ebfff14 | 837 | /* Now convert sense value */ |
6e99e458 | 838 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 839 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
840 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
841 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 842 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 843 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
844 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
845 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 846 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
847 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
848 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
849 | case IRQ_TYPE_LEVEL_LOW: |
850 | default: | |
7233593b ZR |
851 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
852 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 853 | } |
6e99e458 BH |
854 | } |
855 | ||
835c0553 | 856 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
6e99e458 | 857 | { |
835c0553 | 858 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 859 | unsigned int src = irqd_to_hwirq(d); |
6e99e458 BH |
860 | unsigned int vecpri, vold, vnew; |
861 | ||
06fe98e6 | 862 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
835c0553 | 863 | mpic, d->irq, src, flow_type); |
6e99e458 BH |
864 | |
865 | if (src >= mpic->irq_count) | |
866 | return -EINVAL; | |
867 | ||
868 | if (flow_type == IRQ_TYPE_NONE) | |
869 | if (mpic->senses && src < mpic->senses_count) | |
870 | flow_type = mpic->senses[src]; | |
871 | if (flow_type == IRQ_TYPE_NONE) | |
872 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
873 | ||
24a3f2e8 | 874 | irqd_set_trigger_type(d, flow_type); |
6e99e458 BH |
875 | |
876 | if (mpic_is_ht_interrupt(mpic, src)) | |
877 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
878 | MPIC_VECPRI_SENSE_EDGE; | |
879 | else | |
7233593b | 880 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 881 | |
7233593b ZR |
882 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
883 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
884 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
885 | vnew |= vecpri; |
886 | if (vold != vnew) | |
7233593b | 887 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 | 888 | |
24a3f2e8 | 889 | return IRQ_SET_MASK_OK_NOCOPY;; |
0ebfff14 BH |
890 | } |
891 | ||
38958dd9 OJ |
892 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
893 | { | |
894 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 895 | unsigned int src = virq_to_hw(virq); |
38958dd9 OJ |
896 | unsigned int vecpri; |
897 | ||
898 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
899 | mpic, virq, src, vector); | |
900 | ||
901 | if (src >= mpic->irq_count) | |
902 | return; | |
903 | ||
904 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
905 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
906 | vecpri |= vector; | |
907 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
908 | } | |
909 | ||
dfec2202 MI |
910 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
911 | { | |
912 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 913 | unsigned int src = virq_to_hw(virq); |
dfec2202 MI |
914 | |
915 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | |
916 | mpic, virq, src, cpuid); | |
917 | ||
918 | if (src >= mpic->irq_count) | |
919 | return; | |
920 | ||
921 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | |
922 | } | |
923 | ||
b9e5b4e6 | 924 | static struct irq_chip mpic_irq_chip = { |
835c0553 LB |
925 | .irq_mask = mpic_mask_irq, |
926 | .irq_unmask = mpic_unmask_irq, | |
927 | .irq_eoi = mpic_end_irq, | |
928 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
929 | }; |
930 | ||
931 | #ifdef CONFIG_SMP | |
932 | static struct irq_chip mpic_ipi_chip = { | |
835c0553 LB |
933 | .irq_mask = mpic_mask_ipi, |
934 | .irq_unmask = mpic_unmask_ipi, | |
935 | .irq_eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
936 | }; |
937 | #endif /* CONFIG_SMP */ | |
938 | ||
6cfef5b2 | 939 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 940 | static struct irq_chip mpic_irq_ht_chip = { |
835c0553 LB |
941 | .irq_startup = mpic_startup_ht_irq, |
942 | .irq_shutdown = mpic_shutdown_ht_irq, | |
943 | .irq_mask = mpic_mask_irq, | |
944 | .irq_unmask = mpic_unmask_ht_irq, | |
945 | .irq_eoi = mpic_end_ht_irq, | |
946 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 | 947 | }; |
6cfef5b2 | 948 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 949 | |
14cf11af | 950 | |
0ebfff14 BH |
951 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
952 | { | |
0ebfff14 | 953 | /* Exact match, unless mpic node is NULL */ |
52964f87 | 954 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
955 | } |
956 | ||
957 | static int mpic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 958 | irq_hw_number_t hw) |
0ebfff14 | 959 | { |
0ebfff14 | 960 | struct mpic *mpic = h->host_data; |
6e99e458 | 961 | struct irq_chip *chip; |
0ebfff14 | 962 | |
06fe98e6 | 963 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 964 | |
7df2457d | 965 | if (hw == mpic->spurious_vec) |
0ebfff14 | 966 | return -EINVAL; |
7fd72186 BH |
967 | if (mpic->protected && test_bit(hw, mpic->protected)) |
968 | return -EINVAL; | |
06fe98e6 | 969 | |
0ebfff14 | 970 | #ifdef CONFIG_SMP |
7df2457d | 971 | else if (hw >= mpic->ipi_vecs[0]) { |
0ebfff14 BH |
972 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
973 | ||
06fe98e6 | 974 | DBG("mpic: mapping as IPI\n"); |
ec775d0e TG |
975 | irq_set_chip_data(virq, mpic); |
976 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, | |
0ebfff14 BH |
977 | handle_percpu_irq); |
978 | return 0; | |
979 | } | |
980 | #endif /* CONFIG_SMP */ | |
981 | ||
982 | if (hw >= mpic->irq_count) | |
983 | return -EINVAL; | |
984 | ||
a7de7c74 ME |
985 | mpic_msi_reserve_hwirq(mpic, hw); |
986 | ||
6e99e458 | 987 | /* Default chip */ |
0ebfff14 BH |
988 | chip = &mpic->hc_irq; |
989 | ||
6cfef5b2 | 990 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 991 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 992 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 993 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 994 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 995 | |
06fe98e6 | 996 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 | 997 | |
ec775d0e TG |
998 | irq_set_chip_data(virq, mpic); |
999 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
1000 | |
1001 | /* Set default irq type */ | |
ec775d0e | 1002 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
6e99e458 | 1003 | |
dfec2202 MI |
1004 | /* If the MPIC was reset, then all vectors have already been |
1005 | * initialized. Otherwise, a per source lazy initialization | |
1006 | * is done here. | |
1007 | */ | |
1008 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { | |
dfec2202 | 1009 | mpic_set_vector(virq, hw); |
d6a2639b | 1010 | mpic_set_destination(virq, mpic_processor_id(mpic)); |
dfec2202 MI |
1011 | mpic_irq_set_priority(virq, 8); |
1012 | } | |
1013 | ||
0ebfff14 BH |
1014 | return 0; |
1015 | } | |
1016 | ||
1017 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 1018 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
1019 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
1020 | ||
1021 | { | |
1022 | static unsigned char map_mpic_senses[4] = { | |
1023 | IRQ_TYPE_EDGE_RISING, | |
1024 | IRQ_TYPE_LEVEL_LOW, | |
1025 | IRQ_TYPE_LEVEL_HIGH, | |
1026 | IRQ_TYPE_EDGE_FALLING, | |
1027 | }; | |
1028 | ||
1029 | *out_hwirq = intspec[0]; | |
06fe98e6 BH |
1030 | if (intsize > 1) { |
1031 | u32 mask = 0x3; | |
1032 | ||
1033 | /* Apple invented a new race of encoding on machines with | |
1034 | * an HT APIC. They encode, among others, the index within | |
1035 | * the HT APIC. We don't care about it here since thankfully, | |
1036 | * it appears that they have the APIC already properly | |
1037 | * configured, and thus our current fixup code that reads the | |
1038 | * APIC config works fine. However, we still need to mask out | |
1039 | * bits in the specifier to make sure we only get bit 0 which | |
1040 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1041 | * as their bit 1 means something else. | |
1042 | */ | |
1043 | if (machine_is(powermac)) | |
1044 | mask = 0x1; | |
1045 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1046 | } else | |
0ebfff14 BH |
1047 | *out_flags = IRQ_TYPE_NONE; |
1048 | ||
06fe98e6 BH |
1049 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1050 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1051 | ||
0ebfff14 BH |
1052 | return 0; |
1053 | } | |
1054 | ||
1055 | static struct irq_host_ops mpic_host_ops = { | |
1056 | .match = mpic_host_match, | |
1057 | .map = mpic_host_map, | |
1058 | .xlate = mpic_host_xlate, | |
1059 | }; | |
1060 | ||
dfec2202 MI |
1061 | static int mpic_reset_prohibited(struct device_node *node) |
1062 | { | |
1063 | return node && of_get_property(node, "pic-no-reset", NULL); | |
1064 | } | |
1065 | ||
14cf11af PM |
1066 | /* |
1067 | * Exported functions | |
1068 | */ | |
1069 | ||
0ebfff14 | 1070 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1071 | phys_addr_t phys_addr, |
14cf11af PM |
1072 | unsigned int flags, |
1073 | unsigned int isu_size, | |
14cf11af | 1074 | unsigned int irq_count, |
14cf11af PM |
1075 | const char *name) |
1076 | { | |
1077 | struct mpic *mpic; | |
d9d1063d | 1078 | u32 greg_feature; |
14cf11af PM |
1079 | const char *vers; |
1080 | int i; | |
7df2457d | 1081 | int intvec_top; |
a959ff56 | 1082 | u64 paddr = phys_addr; |
14cf11af | 1083 | |
85355bb2 | 1084 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af PM |
1085 | if (mpic == NULL) |
1086 | return NULL; | |
85355bb2 | 1087 | |
14cf11af PM |
1088 | mpic->name = name; |
1089 | ||
b9e5b4e6 | 1090 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1091 | mpic->hc_irq.name = name; |
14cf11af | 1092 | if (flags & MPIC_PRIMARY) |
835c0553 | 1093 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1094 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1095 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1096 | mpic->hc_ht_irq.name = name; |
b9e5b4e6 | 1097 | if (flags & MPIC_PRIMARY) |
835c0553 | 1098 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1099 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1100 | |
14cf11af | 1101 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1102 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1103 | mpic->hc_ipi.name = name; |
14cf11af PM |
1104 | #endif /* CONFIG_SMP */ |
1105 | ||
1106 | mpic->flags = flags; | |
1107 | mpic->isu_size = isu_size; | |
14cf11af | 1108 | mpic->irq_count = irq_count; |
14cf11af | 1109 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1110 | |
7df2457d OJ |
1111 | if (flags & MPIC_LARGE_VECTORS) |
1112 | intvec_top = 2047; | |
1113 | else | |
1114 | intvec_top = 255; | |
1115 | ||
1116 | mpic->timer_vecs[0] = intvec_top - 8; | |
1117 | mpic->timer_vecs[1] = intvec_top - 7; | |
1118 | mpic->timer_vecs[2] = intvec_top - 6; | |
1119 | mpic->timer_vecs[3] = intvec_top - 5; | |
1120 | mpic->ipi_vecs[0] = intvec_top - 4; | |
1121 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1122 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1123 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1124 | mpic->spurious_vec = intvec_top; | |
1125 | ||
a959ff56 | 1126 | /* Check for "big-endian" in device-tree */ |
e2eb6392 | 1127 | if (node && of_get_property(node, "big-endian", NULL) != NULL) |
a959ff56 BH |
1128 | mpic->flags |= MPIC_BIG_ENDIAN; |
1129 | ||
7fd72186 BH |
1130 | /* Look for protected sources */ |
1131 | if (node) { | |
d9d1063d JB |
1132 | int psize; |
1133 | unsigned int bits, mapsize; | |
7fd72186 BH |
1134 | const u32 *psrc = |
1135 | of_get_property(node, "protected-sources", &psize); | |
1136 | if (psrc) { | |
1137 | psize /= 4; | |
1138 | bits = intvec_top + 1; | |
1139 | mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); | |
ea96025a | 1140 | mpic->protected = kzalloc(mapsize, GFP_KERNEL); |
7fd72186 | 1141 | BUG_ON(mpic->protected == NULL); |
7fd72186 BH |
1142 | for (i = 0; i < psize; i++) { |
1143 | if (psrc[i] > intvec_top) | |
1144 | continue; | |
1145 | __set_bit(psrc[i], mpic->protected); | |
1146 | } | |
1147 | } | |
1148 | } | |
a959ff56 | 1149 | |
7233593b ZR |
1150 | #ifdef CONFIG_MPIC_WEIRD |
1151 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
1152 | #endif | |
1153 | ||
fbf0274e BH |
1154 | /* default register type */ |
1155 | mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? | |
1156 | mpic_access_mmio_be : mpic_access_mmio_le; | |
1157 | ||
a959ff56 BH |
1158 | /* If no physical address is passed in, a device-node is mandatory */ |
1159 | BUG_ON(paddr == 0 && node == NULL); | |
1160 | ||
1161 | /* If no physical address passed in, check if it's dcr based */ | |
0411a5e2 | 1162 | if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { |
fbf0274e | 1163 | #ifdef CONFIG_PPC_DCR |
0411a5e2 | 1164 | mpic->flags |= MPIC_USES_DCR; |
fbf0274e | 1165 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1166 | #else |
0411a5e2 | 1167 | BUG(); |
fbf0274e | 1168 | #endif /* CONFIG_PPC_DCR */ |
0411a5e2 | 1169 | } |
fbf0274e | 1170 | |
a959ff56 BH |
1171 | /* If the MPIC is not DCR based, and no physical address was passed |
1172 | * in, try to obtain one | |
1173 | */ | |
1174 | if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { | |
d9d1063d | 1175 | const u32 *reg = of_get_property(node, "reg", NULL); |
a959ff56 BH |
1176 | BUG_ON(reg == NULL); |
1177 | paddr = of_translate_address(node, reg); | |
1178 | BUG_ON(paddr == OF_BAD_ADDR); | |
1179 | } | |
1180 | ||
14cf11af | 1181 | /* Map the global registers */ |
5a2642f6 BH |
1182 | mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1183 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
1184 | |
1185 | /* Reset */ | |
dfec2202 MI |
1186 | |
1187 | /* When using a device-node, reset requests are only honored if the MPIC | |
1188 | * is allowed to reset. | |
1189 | */ | |
1190 | if (mpic_reset_prohibited(node)) | |
1191 | mpic->flags |= MPIC_NO_RESET; | |
1192 | ||
1193 | if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { | |
1194 | printk(KERN_DEBUG "mpic: Resetting\n"); | |
7233593b ZR |
1195 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1196 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1197 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1198 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1199 | & MPIC_GREG_GCONF_RESET) |
1200 | mb(); | |
1201 | } | |
1202 | ||
d91e4ea7 KG |
1203 | /* CoreInt */ |
1204 | if (flags & MPIC_ENABLE_COREINT) | |
1205 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1206 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1207 | | MPIC_GREG_GCONF_COREINT); | |
1208 | ||
f365355e OJ |
1209 | if (flags & MPIC_ENABLE_MCK) |
1210 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1211 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1212 | | MPIC_GREG_GCONF_MCK); | |
1213 | ||
14cf11af PM |
1214 | /* Read feature register, calculate num CPUs and, for non-ISU |
1215 | * MPICs, num sources as well. On ISU MPICs, sources are counted | |
1216 | * as ISUs are added | |
1217 | */ | |
d9d1063d JB |
1218 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
1219 | mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) | |
14cf11af | 1220 | >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; |
5073e7ee | 1221 | if (isu_size == 0) { |
475ca391 KG |
1222 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
1223 | mpic->num_sources = mpic->irq_count; | |
1224 | else | |
1225 | mpic->num_sources = | |
1226 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1227 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
5073e7ee | 1228 | } |
14cf11af PM |
1229 | |
1230 | /* Map the per-CPU registers */ | |
1231 | for (i = 0; i < mpic->num_cpus; i++) { | |
5a2642f6 | 1232 | mpic_map(mpic, node, paddr, &mpic->cpuregs[i], |
fbf0274e BH |
1233 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
1234 | 0x1000); | |
14cf11af PM |
1235 | } |
1236 | ||
1237 | /* Initialize main ISU if none provided */ | |
1238 | if (mpic->isu_size == 0) { | |
1239 | mpic->isu_size = mpic->num_sources; | |
5a2642f6 | 1240 | mpic_map(mpic, node, paddr, &mpic->isus[0], |
fbf0274e | 1241 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1242 | } |
1243 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1244 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1245 | ||
31207dab KG |
1246 | mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
1247 | isu_size ? isu_size : mpic->num_sources, | |
1248 | &mpic_host_ops, | |
1249 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); | |
1250 | if (mpic->irqhost == NULL) | |
1251 | return NULL; | |
1252 | ||
1253 | mpic->irqhost->host_data = mpic; | |
1254 | ||
14cf11af | 1255 | /* Display version */ |
d9d1063d | 1256 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1257 | case 1: |
1258 | vers = "1.0"; | |
1259 | break; | |
1260 | case 2: | |
1261 | vers = "1.2"; | |
1262 | break; | |
1263 | case 3: | |
1264 | vers = "1.3"; | |
1265 | break; | |
1266 | default: | |
1267 | vers = "<unknown>"; | |
1268 | break; | |
1269 | } | |
a959ff56 BH |
1270 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1271 | " max %d CPUs\n", | |
1272 | name, vers, (unsigned long long)paddr, mpic->num_cpus); | |
1273 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", | |
1274 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1275 | |
1276 | mpic->next = mpics; | |
1277 | mpics = mpic; | |
1278 | ||
0ebfff14 | 1279 | if (flags & MPIC_PRIMARY) { |
14cf11af | 1280 | mpic_primary = mpic; |
0ebfff14 BH |
1281 | irq_set_default_host(mpic->irqhost); |
1282 | } | |
14cf11af PM |
1283 | |
1284 | return mpic; | |
1285 | } | |
1286 | ||
1287 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1288 | phys_addr_t paddr) |
14cf11af PM |
1289 | { |
1290 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1291 | ||
1292 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1293 | ||
5a2642f6 BH |
1294 | mpic_map(mpic, mpic->irqhost->of_node, |
1295 | paddr, &mpic->isus[isu_num], 0, | |
fbf0274e | 1296 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1297 | |
14cf11af PM |
1298 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1299 | mpic->num_sources = isu_first + mpic->isu_size; | |
1300 | } | |
1301 | ||
0ebfff14 BH |
1302 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1303 | { | |
1304 | mpic->senses = senses; | |
1305 | mpic->senses_count = count; | |
1306 | } | |
1307 | ||
14cf11af PM |
1308 | void __init mpic_init(struct mpic *mpic) |
1309 | { | |
1310 | int i; | |
cc353c30 | 1311 | int cpu; |
14cf11af PM |
1312 | |
1313 | BUG_ON(mpic->num_sources == 0); | |
1314 | ||
1315 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1316 | ||
1317 | /* Set current processor priority to max */ | |
7233593b | 1318 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af PM |
1319 | |
1320 | /* Initialize timers: just disable them all */ | |
1321 | for (i = 0; i < 4; i++) { | |
1322 | mpic_write(mpic->tmregs, | |
7233593b ZR |
1323 | i * MPIC_INFO(TIMER_STRIDE) + |
1324 | MPIC_INFO(TIMER_DESTINATION), 0); | |
14cf11af | 1325 | mpic_write(mpic->tmregs, |
7233593b ZR |
1326 | i * MPIC_INFO(TIMER_STRIDE) + |
1327 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af | 1328 | MPIC_VECPRI_MASK | |
7df2457d | 1329 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1330 | } |
1331 | ||
1332 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1333 | mpic_test_broken_ipi(mpic); | |
1334 | for (i = 0; i < 4; i++) { | |
1335 | mpic_ipi_write(i, | |
1336 | MPIC_VECPRI_MASK | | |
1337 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1338 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1339 | } |
1340 | ||
1341 | /* Initialize interrupt sources */ | |
1342 | if (mpic->irq_count == 0) | |
1343 | mpic->irq_count = mpic->num_sources; | |
1344 | ||
1beb6a7d | 1345 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1346 | DBG("MPIC flags: %x\n", mpic->flags); |
05af7bd2 | 1347 | if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { |
3669e930 | 1348 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1349 | mpic_u3msi_init(mpic); |
1350 | } | |
14cf11af | 1351 | |
38958dd9 OJ |
1352 | mpic_pasemi_msi_init(mpic); |
1353 | ||
d6a2639b | 1354 | cpu = mpic_processor_id(mpic); |
cc353c30 | 1355 | |
dfec2202 MI |
1356 | if (!(mpic->flags & MPIC_NO_RESET)) { |
1357 | for (i = 0; i < mpic->num_sources; i++) { | |
1358 | /* start with vector = source number, and masked */ | |
1359 | u32 vecpri = MPIC_VECPRI_MASK | i | | |
1360 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1361 | |
dfec2202 MI |
1362 | /* check if protected */ |
1363 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1364 | continue; | |
1365 | /* init hw */ | |
1366 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
1367 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); | |
1368 | } | |
14cf11af PM |
1369 | } |
1370 | ||
7df2457d OJ |
1371 | /* Init spurious vector */ |
1372 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1373 | |
7233593b ZR |
1374 | /* Disable 8259 passthrough, if supported */ |
1375 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1376 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1377 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1378 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1379 | |
d87bf3be OJ |
1380 | if (mpic->flags & MPIC_NO_BIAS) |
1381 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1382 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1383 | | MPIC_GREG_GCONF_NO_BIAS); | |
1384 | ||
14cf11af | 1385 | /* Set current processor priority to 0 */ |
7233593b | 1386 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1387 | |
1388 | #ifdef CONFIG_PM | |
1389 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1390 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1391 | GFP_KERNEL); | |
3669e930 JB |
1392 | BUG_ON(mpic->save_data == NULL); |
1393 | #endif | |
14cf11af PM |
1394 | } |
1395 | ||
868ea0c9 MG |
1396 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1397 | { | |
1398 | u32 v; | |
1399 | ||
1400 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1401 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1402 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1403 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1404 | } | |
14cf11af | 1405 | |
868ea0c9 MG |
1406 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1407 | { | |
ba1826e5 | 1408 | unsigned long flags; |
868ea0c9 MG |
1409 | u32 v; |
1410 | ||
203041ad | 1411 | raw_spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1412 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1413 | if (enable) | |
1414 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1415 | else | |
1416 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1417 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
203041ad | 1418 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1419 | } |
14cf11af PM |
1420 | |
1421 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1422 | { | |
d69a78d7 | 1423 | struct mpic *mpic = mpic_find(irq); |
476eb491 | 1424 | unsigned int src = virq_to_hw(irq); |
14cf11af PM |
1425 | unsigned long flags; |
1426 | u32 reg; | |
1427 | ||
06a901c5 SR |
1428 | if (!mpic) |
1429 | return; | |
1430 | ||
203041ad | 1431 | raw_spin_lock_irqsave(&mpic_lock, flags); |
d69a78d7 | 1432 | if (mpic_is_ipi(mpic, irq)) { |
7df2457d | 1433 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1434 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1435 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af PM |
1436 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1437 | } else { | |
7233593b | 1438 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1439 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1440 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1441 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1442 | } | |
203041ad | 1443 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1444 | } |
1445 | ||
14cf11af PM |
1446 | void mpic_setup_this_cpu(void) |
1447 | { | |
1448 | #ifdef CONFIG_SMP | |
1449 | struct mpic *mpic = mpic_primary; | |
1450 | unsigned long flags; | |
1451 | u32 msk = 1 << hard_smp_processor_id(); | |
1452 | unsigned int i; | |
1453 | ||
1454 | BUG_ON(mpic == NULL); | |
1455 | ||
1456 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1457 | ||
203041ad | 1458 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1459 | |
1460 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1461 | * until changed via /proc. That's how it's done on x86. If we want | |
1462 | * it differently, then we should make sure we also change the default | |
a53da52f | 1463 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1464 | */ |
1465 | if (distribute_irqs) { | |
1466 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1467 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1468 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1469 | } |
1470 | ||
1471 | /* Set current processor priority to 0 */ | |
7233593b | 1472 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af | 1473 | |
203041ad | 1474 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1475 | #endif /* CONFIG_SMP */ |
1476 | } | |
1477 | ||
1478 | int mpic_cpu_get_priority(void) | |
1479 | { | |
1480 | struct mpic *mpic = mpic_primary; | |
1481 | ||
7233593b | 1482 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1483 | } |
1484 | ||
1485 | void mpic_cpu_set_priority(int prio) | |
1486 | { | |
1487 | struct mpic *mpic = mpic_primary; | |
1488 | ||
1489 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1490 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1491 | } |
1492 | ||
14cf11af PM |
1493 | void mpic_teardown_this_cpu(int secondary) |
1494 | { | |
1495 | struct mpic *mpic = mpic_primary; | |
1496 | unsigned long flags; | |
1497 | u32 msk = 1 << hard_smp_processor_id(); | |
1498 | unsigned int i; | |
1499 | ||
1500 | BUG_ON(mpic == NULL); | |
1501 | ||
1502 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
203041ad | 1503 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1504 | |
1505 | /* let the mpic know we don't want intrs. */ | |
1506 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1507 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1508 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1509 | |
1510 | /* Set current processor priority to max */ | |
7233593b | 1511 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1512 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1513 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1514 | */ | |
1515 | mpic_eoi(mpic); | |
14cf11af | 1516 | |
203041ad | 1517 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1518 | } |
1519 | ||
1520 | ||
f365355e | 1521 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1522 | { |
0ebfff14 | 1523 | u32 src; |
14cf11af | 1524 | |
f365355e | 1525 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1526 | #ifdef DEBUG_LOW |
f365355e | 1527 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1528 | #endif |
5cddd2e3 JB |
1529 | if (unlikely(src == mpic->spurious_vec)) { |
1530 | if (mpic->flags & MPIC_SPV_EOI) | |
1531 | mpic_eoi(mpic); | |
0ebfff14 | 1532 | return NO_IRQ; |
5cddd2e3 | 1533 | } |
7fd72186 BH |
1534 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
1535 | if (printk_ratelimit()) | |
1536 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1537 | mpic->name, (int)src); | |
1538 | mpic_eoi(mpic); | |
1539 | return NO_IRQ; | |
1540 | } | |
1541 | ||
0ebfff14 | 1542 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1543 | } |
1544 | ||
f365355e OJ |
1545 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1546 | { | |
1547 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1548 | } | |
1549 | ||
35a84c2f | 1550 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1551 | { |
1552 | struct mpic *mpic = mpic_primary; | |
1553 | ||
1554 | BUG_ON(mpic == NULL); | |
1555 | ||
35a84c2f | 1556 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1557 | } |
1558 | ||
d91e4ea7 KG |
1559 | unsigned int mpic_get_coreint_irq(void) |
1560 | { | |
1561 | #ifdef CONFIG_BOOKE | |
1562 | struct mpic *mpic = mpic_primary; | |
1563 | u32 src; | |
1564 | ||
1565 | BUG_ON(mpic == NULL); | |
1566 | ||
1567 | src = mfspr(SPRN_EPR); | |
1568 | ||
1569 | if (unlikely(src == mpic->spurious_vec)) { | |
1570 | if (mpic->flags & MPIC_SPV_EOI) | |
1571 | mpic_eoi(mpic); | |
1572 | return NO_IRQ; | |
1573 | } | |
1574 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
1575 | if (printk_ratelimit()) | |
1576 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1577 | mpic->name, (int)src); | |
1578 | return NO_IRQ; | |
1579 | } | |
1580 | ||
1581 | return irq_linear_revmap(mpic->irqhost, src); | |
1582 | #else | |
1583 | return NO_IRQ; | |
1584 | #endif | |
1585 | } | |
1586 | ||
f365355e OJ |
1587 | unsigned int mpic_get_mcirq(void) |
1588 | { | |
1589 | struct mpic *mpic = mpic_primary; | |
1590 | ||
1591 | BUG_ON(mpic == NULL); | |
1592 | ||
1593 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1594 | } | |
14cf11af PM |
1595 | |
1596 | #ifdef CONFIG_SMP | |
1597 | void mpic_request_ipis(void) | |
1598 | { | |
1599 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1600 | int i; |
14cf11af | 1601 | BUG_ON(mpic == NULL); |
14cf11af | 1602 | |
8354be9c | 1603 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
0ebfff14 BH |
1604 | |
1605 | for (i = 0; i < 4; i++) { | |
1606 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1607 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1608 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1609 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1610 | continue; | |
d16f1b64 | 1611 | } |
78608dd3 | 1612 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1613 | } |
14cf11af | 1614 | } |
a9c59264 | 1615 | |
2ef613cb BH |
1616 | static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask) |
1617 | { | |
1618 | struct mpic *mpic = mpic_primary; | |
1619 | ||
1620 | BUG_ON(mpic == NULL); | |
1621 | ||
1622 | #ifdef DEBUG_IPI | |
1623 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); | |
1624 | #endif | |
1625 | ||
1626 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + | |
1627 | ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), | |
1628 | mpic_physmask(cpumask_bits(cpu_mask)[0])); | |
1629 | } | |
1630 | ||
f1072939 | 1631 | void smp_mpic_message_pass(int cpu, int msg) |
a9c59264 PM |
1632 | { |
1633 | /* make sure we're sending something that translates to an IPI */ | |
1634 | if ((unsigned int)msg > 3) { | |
1635 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1636 | smp_processor_id(), msg); | |
1637 | return; | |
1638 | } | |
f1072939 | 1639 | mpic_send_ipi(msg, cpumask_of(cpu)); |
a9c59264 | 1640 | } |
775aeff4 ME |
1641 | |
1642 | int __init smp_mpic_probe(void) | |
1643 | { | |
1644 | int nr_cpus; | |
1645 | ||
1646 | DBG("smp_mpic_probe()...\n"); | |
1647 | ||
2ef613cb | 1648 | nr_cpus = cpumask_weight(cpu_possible_mask); |
775aeff4 ME |
1649 | |
1650 | DBG("nr_cpus: %d\n", nr_cpus); | |
1651 | ||
1652 | if (nr_cpus > 1) | |
1653 | mpic_request_ipis(); | |
1654 | ||
1655 | return nr_cpus; | |
1656 | } | |
1657 | ||
1658 | void __devinit smp_mpic_setup_cpu(int cpu) | |
1659 | { | |
1660 | mpic_setup_this_cpu(); | |
1661 | } | |
66953ebe MM |
1662 | |
1663 | void mpic_reset_core(int cpu) | |
1664 | { | |
1665 | struct mpic *mpic = mpic_primary; | |
1666 | u32 pir; | |
1667 | int cpuid = get_hard_smp_processor_id(cpu); | |
1668 | ||
1669 | /* Set target bit for core reset */ | |
1670 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1671 | pir |= (1 << cpuid); | |
1672 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1673 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1674 | ||
1675 | /* Restore target bit after reset complete */ | |
1676 | pir &= ~(1 << cpuid); | |
1677 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1678 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1679 | } | |
14cf11af | 1680 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1681 | |
1682 | #ifdef CONFIG_PM | |
1683 | static int mpic_suspend(struct sys_device *dev, pm_message_t state) | |
1684 | { | |
1685 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); | |
1686 | int i; | |
1687 | ||
1688 | for (i = 0; i < mpic->num_sources; i++) { | |
1689 | mpic->save_data[i].vecprio = | |
1690 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1691 | mpic->save_data[i].dest = | |
1692 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1693 | } | |
1694 | ||
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | static int mpic_resume(struct sys_device *dev) | |
1699 | { | |
1700 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); | |
1701 | int i; | |
1702 | ||
1703 | for (i = 0; i < mpic->num_sources; i++) { | |
1704 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1705 | mpic->save_data[i].vecprio); | |
1706 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1707 | mpic->save_data[i].dest); | |
1708 | ||
1709 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
7c9d9360 | 1710 | if (mpic->fixups) { |
3669e930 JB |
1711 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
1712 | ||
1713 | if (fixup->base) { | |
1714 | /* we use the lowest bit in an inverted meaning */ | |
1715 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1716 | continue; | |
1717 | ||
1718 | /* Enable and configure */ | |
1719 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1720 | ||
1721 | writel(mpic->save_data[i].fixup_data & ~1, | |
1722 | fixup->base + 4); | |
1723 | } | |
1724 | } | |
1725 | #endif | |
1726 | } /* end for loop */ | |
1727 | ||
1728 | return 0; | |
1729 | } | |
1730 | #endif | |
1731 | ||
1732 | static struct sysdev_class mpic_sysclass = { | |
1733 | #ifdef CONFIG_PM | |
1734 | .resume = mpic_resume, | |
1735 | .suspend = mpic_suspend, | |
1736 | #endif | |
af5ca3f4 | 1737 | .name = "mpic", |
3669e930 JB |
1738 | }; |
1739 | ||
1740 | static int mpic_init_sys(void) | |
1741 | { | |
1742 | struct mpic *mpic = mpics; | |
1743 | int error, id = 0; | |
1744 | ||
1745 | error = sysdev_class_register(&mpic_sysclass); | |
1746 | ||
1747 | while (mpic && !error) { | |
1748 | mpic->sysdev.cls = &mpic_sysclass; | |
1749 | mpic->sysdev.id = id++; | |
1750 | error = sysdev_register(&mpic->sysdev); | |
1751 | mpic = mpic->next; | |
1752 | } | |
1753 | return error; | |
1754 | } | |
1755 | ||
1756 | device_initcall(mpic_init_sys); |