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Commit | Line | Data |
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38958dd9 OJ |
1 | /* |
2 | * Copyright 2007, Olof Johansson, PA Semi | |
3 | * | |
4 | * Based on arch/powerpc/sysdev/mpic_u3msi.c: | |
5 | * | |
6 | * Copyright 2006, Segher Boessenkool, IBM Corporation. | |
7 | * Copyright 2006-2007, Michael Ellerman, IBM Corporation. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | */ | |
15 | ||
16 | #undef DEBUG | |
17 | ||
18 | #include <linux/irq.h> | |
38958dd9 OJ |
19 | #include <linux/msi.h> |
20 | #include <asm/mpic.h> | |
21 | #include <asm/prom.h> | |
22 | #include <asm/hw_irq.h> | |
23 | #include <asm/ppc-pci.h> | |
25235f71 | 24 | #include <asm/msi_bitmap.h> |
38958dd9 OJ |
25 | |
26 | #include "mpic.h" | |
27 | ||
28 | /* Allocate 16 interrupts per device, to give an alignment of 16, | |
29 | * since that's the size of the grouping w.r.t. affinity. If someone | |
30 | * needs more than 32 MSI's down the road we'll have to rethink this, | |
31 | * but it should be OK for now. | |
32 | */ | |
33 | #define ALLOC_CHUNK 16 | |
34 | ||
35 | #define PASEMI_MSI_ADDR 0xfc080000 | |
36 | ||
37 | /* A bit ugly, can we get this from the pci_dev somehow? */ | |
38 | static struct mpic *msi_mpic; | |
39 | ||
40 | ||
1c9db525 | 41 | static void mpic_pasemi_msi_mask_irq(struct irq_data *data) |
38958dd9 | 42 | { |
1c9db525 | 43 | pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); |
280510f1 | 44 | pci_msi_mask_irq(data); |
835c0553 | 45 | mpic_mask_irq(data); |
38958dd9 OJ |
46 | } |
47 | ||
1c9db525 | 48 | static void mpic_pasemi_msi_unmask_irq(struct irq_data *data) |
38958dd9 | 49 | { |
1c9db525 | 50 | pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); |
835c0553 | 51 | mpic_unmask_irq(data); |
280510f1 | 52 | pci_msi_unmask_irq(data); |
38958dd9 OJ |
53 | } |
54 | ||
55 | static struct irq_chip mpic_pasemi_msi_chip = { | |
835c0553 LB |
56 | .irq_shutdown = mpic_pasemi_msi_mask_irq, |
57 | .irq_mask = mpic_pasemi_msi_mask_irq, | |
58 | .irq_unmask = mpic_pasemi_msi_unmask_irq, | |
59 | .irq_eoi = mpic_end_irq, | |
60 | .irq_set_type = mpic_set_irq_type, | |
61 | .irq_set_affinity = mpic_set_affinity, | |
62 | .name = "PASEMI-MSI", | |
38958dd9 OJ |
63 | }; |
64 | ||
38958dd9 OJ |
65 | static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev) |
66 | { | |
67 | struct msi_desc *entry; | |
68 | ||
69 | pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev); | |
70 | ||
71 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
72 | if (entry->irq == NO_IRQ) | |
73 | continue; | |
74 | ||
ec775d0e | 75 | irq_set_msi_desc(entry->irq, NULL); |
25235f71 ME |
76 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, |
77 | virq_to_hw(entry->irq), ALLOC_CHUNK); | |
38958dd9 OJ |
78 | irq_dispose_mapping(entry->irq); |
79 | } | |
80 | ||
81 | return; | |
82 | } | |
83 | ||
84 | static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
85 | { | |
38958dd9 OJ |
86 | unsigned int virq; |
87 | struct msi_desc *entry; | |
88 | struct msi_msg msg; | |
25235f71 | 89 | int hwirq; |
38958dd9 | 90 | |
6b2fd7ef AG |
91 | if (type == PCI_CAP_ID_MSIX) |
92 | pr_debug("pasemi_msi: MSI-X untested, trying anyway\n"); | |
38958dd9 OJ |
93 | pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n", |
94 | pdev, nvec, type); | |
95 | ||
96 | msg.address_hi = 0; | |
97 | msg.address_lo = PASEMI_MSI_ADDR; | |
98 | ||
99 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
100 | /* Allocate 16 interrupts for now, since that's the grouping for | |
101 | * affinity. This can be changed later if it turns out 32 is too | |
102 | * few MSIs for someone, but restrictions will apply to how the | |
103 | * sources can be changed independently. | |
104 | */ | |
25235f71 ME |
105 | hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, |
106 | ALLOC_CHUNK); | |
107 | if (hwirq < 0) { | |
38958dd9 OJ |
108 | pr_debug("pasemi_msi: failed allocating hwirq\n"); |
109 | return hwirq; | |
110 | } | |
111 | ||
112 | virq = irq_create_mapping(msi_mpic->irqhost, hwirq); | |
113 | if (virq == NO_IRQ) { | |
25235f71 ME |
114 | pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n", |
115 | hwirq); | |
116 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, | |
117 | ALLOC_CHUNK); | |
38958dd9 OJ |
118 | return -ENOSPC; |
119 | } | |
120 | ||
121 | /* Vector on MSI is really an offset, the hardware adds | |
122 | * it to the value written at the magic address. So set | |
123 | * it to 0 to remain sane. | |
124 | */ | |
125 | mpic_set_vector(virq, 0); | |
126 | ||
ec775d0e TG |
127 | irq_set_msi_desc(virq, entry); |
128 | irq_set_chip(virq, &mpic_pasemi_msi_chip); | |
129 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | |
38958dd9 | 130 | |
25235f71 ME |
131 | pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ |
132 | "addr 0x%x\n", virq, hwirq, msg.address_lo); | |
38958dd9 OJ |
133 | |
134 | /* Likewise, the device writes [0...511] into the target | |
135 | * register to generate MSI [512...1023] | |
136 | */ | |
137 | msg.data = hwirq-0x200; | |
83a18912 | 138 | pci_write_msi_msg(virq, &msg); |
38958dd9 OJ |
139 | } |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
144 | int mpic_pasemi_msi_init(struct mpic *mpic) | |
145 | { | |
146 | int rc; | |
147 | ||
148 | if (!mpic->irqhost->of_node || | |
149 | !of_device_is_compatible(mpic->irqhost->of_node, | |
150 | "pasemi,pwrficient-openpic")) | |
151 | return -ENODEV; | |
152 | ||
153 | rc = mpic_msi_init_allocator(mpic); | |
154 | if (rc) { | |
155 | pr_debug("pasemi_msi: Error allocating bitmap!\n"); | |
156 | return rc; | |
157 | } | |
158 | ||
159 | pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n"); | |
160 | ||
161 | msi_mpic = mpic; | |
162 | WARN_ON(ppc_md.setup_msi_irqs); | |
163 | ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs; | |
164 | ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs; | |
38958dd9 OJ |
165 | |
166 | return 0; | |
167 | } |