[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / sysdev / qe_lib / gpio.c

/*
 * QUICC Engine GPIOs
 *
 * Copyright (c) MontaVista Software, Inc. 2008.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <asm/qe.h>

struct qe_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	unsigned long pin_flags[QE_PIO_PINS];
#define QE_PIN_REQUESTED 0

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;

	/* saved_regs used to restore dedicated functions */
	struct qe_pio_regs saved_regs;
};

static inline struct qe_gpio_chip *
to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
{
	return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
}

static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	qe_gc->cpdata = in_be32(&regs->cpdata);
	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	return in_be32(&regs->cpdata) & pin_mask;
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (val)
		qe_gc->cpdata |= pin_mask;
	else
		qe_gc->cpdata &= ~pin_mask;

	out_be32(&regs->cpdata, qe_gc->cpdata);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}

static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	unsigned long flags;

	qe_gpio_set(gc, gpio, val);

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

struct qe_pin {
	/*
	 * The qe_gpio_chip name is unfortunate, we should change that to
	 * something like qe_pio_controller. Someday.
	 */
	struct qe_gpio_chip *controller;
	int num;
};

/**
 * qe_pin_request - Request a QE pin
 * @np:		device node to get a pin from
 * @index:	index of a pin in the device tree
 * Context:	non-atomic
 *
 * This function return qe_pin so that you could use it with the rest of
 * the QE Pin Multiplexing API.
 */
struct qe_pin *qe_pin_request(struct device_node *np, int index)
{
	struct qe_pin *qe_pin;
	struct gpio_chip *gc;
	struct of_mm_gpio_chip *mm_gc;
	struct qe_gpio_chip *qe_gc;
	int err;
	unsigned long flags;

	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	if (!qe_pin) {
		pr_debug("%s: can't allocate memory\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	err = of_get_gpio(np, index);
	if (err < 0)
		goto err0;
	gc = gpio_to_chip(err);
	if (WARN_ON(!gc))
		goto err0;

	if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
		pr_debug("%s: tried to get a non-qe pin\n", __func__);
		err = -EINVAL;
		goto err0;
	}

	mm_gc = to_of_mm_gpio_chip(gc);
	qe_gc = to_qe_gpio_chip(mm_gc);

	spin_lock_irqsave(&qe_gc->lock, flags);

	err -= gc->base;
	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
		qe_pin->controller = qe_gc;
		qe_pin->num = err;
		err = 0;
	} else {
		err = -EBUSY;
	}

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	if (!err)
		return qe_pin;
err0:
	kfree(qe_pin);
	pr_debug("%s failed with status %d\n", __func__, err);
	return ERR_PTR(err);
}
EXPORT_SYMBOL(qe_pin_request);

/**
 * qe_pin_free - Free a pin
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function frees the qe_pin structure and makes a pin available
 * for further qe_pin_request() calls.
 */
void qe_pin_free(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	unsigned long flags;
	const int pin = qe_pin->num;

	spin_lock_irqsave(&qe_gc->lock, flags);
	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	spin_unlock_irqrestore(&qe_gc->lock, flags);

	kfree(qe_pin);
}
EXPORT_SYMBOL(qe_pin_free);

/**
 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function resets a pin to a dedicated peripheral function that
 * has been set up by the firmware.
 */
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	int pin = qe_pin->num;
	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (second_reg) {
		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	} else {
		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	}

	if (sregs->cpdata & mask1)
		qe_gc->cpdata |= mask1;
	else
		qe_gc->cpdata &= ~mask1;

	out_be32(&regs->cpdata, qe_gc->cpdata);
	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_dedicated);

/**
 * qe_pin_set_gpio - Set a pin to the GPIO mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function sets a pin to the GPIO mode.
 */
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	/* Let's make it input by default, GPIO API is able to change that. */
	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_gpio);

static int __init qe_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
		int ret;
		struct qe_gpio_chip *qe_gc;
		struct of_mm_gpio_chip *mm_gc;
		struct gpio_chip *gc;

		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
		if (!qe_gc) {
			ret = -ENOMEM;
			goto err;
		}

		spin_lock_init(&qe_gc->lock);

		mm_gc = &qe_gc->mm_gc;
		gc = &mm_gc->gc;

		mm_gc->save_regs = qe_gpio_save_regs;
		gc->ngpio = QE_PIO_PINS;
		gc->direction_input = qe_gpio_dir_in;
		gc->direction_output = qe_gpio_dir_out;
		gc->get = qe_gpio_get;
		gc->set = qe_gpio_set;

		ret = of_mm_gpiochip_add(np, mm_gc);
		if (ret)
			goto err;
		continue;
err:
		pr_err("%s: registration failed with status %d\n",
		       np->full_name, ret);
		kfree(qe_gc);
		/* try others anyway */
	}
	return 0;
}
arch_initcall(qe_add_gpiochips);
Commit	Line	Data
32def337 AV	1	/*
	2	* QUICC Engine GPIOs
	3	*
	4	* Copyright (c) MontaVista Software, Inc. 2008.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
d14b3dd6	15	#include <linux/init.h>
32def337	16	#include <linux/spinlock.h>
1b9e8904	17	#include <linux/err.h>
32def337 AV	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20	#include <linux/of_gpio.h>
	21	#include <linux/gpio.h>
5a0e3ad6	22	#include <linux/slab.h>
66b15db6	23	#include <linux/export.h>
32def337 AV	24	#include <asm/qe.h>
	25
	26	struct qe_gpio_chip {
	27	struct of_mm_gpio_chip mm_gc;
	28	spinlock_t lock;
	29
1b9e8904 AV	30	unsigned long pin_flags[QE_PIO_PINS];
	31	#define QE_PIN_REQUESTED 0
	32
32def337 AV	33	/* shadowed data register to clear/set bits safely */
32def337 AV	34	u32 cpdata;
1b9e8904 AV	35
	36	/* saved_regs used to restore dedicated functions */
	37	struct qe_pio_regs saved_regs;
32def337 AV	38	};
	39
	40	static inline struct qe_gpio_chip *
	41	to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
	42	{
	43	return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
	44	}
	45
	46	static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
	47	{
	48	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	49	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	50
	51	qe_gc->cpdata = in_be32(&regs->cpdata);
1b9e8904 AV	52	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	53	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	54	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	55	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	56	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	57	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
32def337 AV	58	}
	59
	60	static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	61	{
	62	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	63	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	64	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	65
	66	return in_be32(&regs->cpdata) & pin_mask;
	67	}
	68
	69	static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	70	{
	71	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	72	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	73	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	74	unsigned long flags;
	75	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	76
	77	spin_lock_irqsave(&qe_gc->lock, flags);
	78
	79	if (val)
	80	qe_gc->cpdata \|= pin_mask;
	81	else
	82	qe_gc->cpdata &= ~pin_mask;
	83
	84	out_be32(&regs->cpdata, qe_gc->cpdata);
	85
	86	spin_unlock_irqrestore(&qe_gc->lock, flags);
	87	}
	88
	89	static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	90	{
	91	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	92	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	93	unsigned long flags;
	94
	95	spin_lock_irqsave(&qe_gc->lock, flags);
	96
	97	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
	98
	99	spin_unlock_irqrestore(&qe_gc->lock, flags);
	100
	101	return 0;
	102	}
	103
	104	static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	105	{
	106	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	107	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	108	unsigned long flags;
	109
1dcd8ffc MB	110	qe_gpio_set(gc, gpio, val);
1dcd8ffc MB	111
32def337 AV	112	spin_lock_irqsave(&qe_gc->lock, flags);
	113
	114	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
	115
	116	spin_unlock_irqrestore(&qe_gc->lock, flags);
	117
32def337 AV	118	return 0;
	119	}
	120
1b9e8904 AV	121	struct qe_pin {
	122	/*
	123	* The qe_gpio_chip name is unfortunate, we should change that to
	124	* something like qe_pio_controller. Someday.
	125	*/
	126	struct qe_gpio_chip *controller;
	127	int num;
	128	};
	129
	130	/**
	131	* qe_pin_request - Request a QE pin
	132	* @np: device node to get a pin from
	133	* @index: index of a pin in the device tree
	134	* Context: non-atomic
	135	*
	136	* This function return qe_pin so that you could use it with the rest of
	137	* the QE Pin Multiplexing API.
	138	*/
	139	struct qe_pin qe_pin_request(struct device_node np, int index)
	140	{
	141	struct qe_pin *qe_pin;
a19e3da5	142	struct gpio_chip *gc;
1b9e8904 AV	143	struct of_mm_gpio_chip *mm_gc;
	144	struct qe_gpio_chip *qe_gc;
	145	int err;
1b9e8904 AV	146	unsigned long flags;
	147
	148	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	149	if (!qe_pin) {
	150	pr_debug("%s: can't allocate memory\n", __func__);
	151	return ERR_PTR(-ENOMEM);
	152	}
	153
1a2d397a GL	154	err = of_get_gpio(np, index);
	155	if (err < 0)
	156	goto err0;
	157	gc = gpio_to_chip(err);
	158	if (WARN_ON(!gc))
1b9e8904	159	goto err0;
1b9e8904	160
1a2d397a	161	if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
1b9e8904 AV	162	pr_debug("%s: tried to get a non-qe pin\n", __func__);
1b9e8904 AV	163	err = -EINVAL;
1a2d397a	164	goto err0;
1b9e8904 AV	165	}
1b9e8904 AV	166
a19e3da5	167	mm_gc = to_of_mm_gpio_chip(gc);
1b9e8904 AV	168	qe_gc = to_qe_gpio_chip(mm_gc);
	169
	170	spin_lock_irqsave(&qe_gc->lock, flags);
	171
1a2d397a	172	err -= gc->base;
1b9e8904 AV	173	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
	174	qe_pin->controller = qe_gc;
	175	qe_pin->num = err;
	176	err = 0;
	177	} else {
	178	err = -EBUSY;
	179	}
	180
	181	spin_unlock_irqrestore(&qe_gc->lock, flags);
	182
	183	if (!err)
	184	return qe_pin;
1b9e8904 AV	185	err0:
	186	kfree(qe_pin);
	187	pr_debug("%s failed with status %d\n", __func__, err);
	188	return ERR_PTR(err);
	189	}
	190	EXPORT_SYMBOL(qe_pin_request);
	191
	192	/**
	193	* qe_pin_free - Free a pin
	194	* @qe_pin: pointer to the qe_pin structure
	195	* Context: any
	196	*
	197	* This function frees the qe_pin structure and makes a pin available
	198	* for further qe_pin_request() calls.
	199	*/
	200	void qe_pin_free(struct qe_pin *qe_pin)
	201	{
	202	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	203	unsigned long flags;
	204	const int pin = qe_pin->num;
	205
	206	spin_lock_irqsave(&qe_gc->lock, flags);
	207	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	208	spin_unlock_irqrestore(&qe_gc->lock, flags);
	209
	210	kfree(qe_pin);
	211	}
	212	EXPORT_SYMBOL(qe_pin_free);
	213
	214	/**
	215	* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
	216	* @qe_pin: pointer to the qe_pin structure
	217	* Context: any
	218	*
	219	* This function resets a pin to a dedicated peripheral function that
	220	* has been set up by the firmware.
	221	*/
	222	void qe_pin_set_dedicated(struct qe_pin *qe_pin)
	223	{
	224	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	225	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	226	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	227	int pin = qe_pin->num;
	228	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	229	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	230	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	231	unsigned long flags;
	232
	233	spin_lock_irqsave(&qe_gc->lock, flags);
	234
	235	if (second_reg) {
	236	clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
	237	clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	238	} else {
	239	clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
	240	clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	241	}
	242
	243	if (sregs->cpdata & mask1)
	244	qe_gc->cpdata \|= mask1;
	245	else
	246	qe_gc->cpdata &= ~mask1;
	247
	248	out_be32(&regs->cpdata, qe_gc->cpdata);
249	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
250
251	spin_unlock_irqrestore(&qe_gc->lock, flags);
252	}
253	EXPORT_SYMBOL(qe_pin_set_dedicated);
254
255	/**
256	* qe_pin_set_gpio - Set a pin to the GPIO mode
257	* @qe_pin: pointer to the qe_pin structure
258	* Context: any
259	*
260	* This function sets a pin to the GPIO mode.
261	*/
262	void qe_pin_set_gpio(struct qe_pin *qe_pin)
263	{
264	struct qe_gpio_chip *qe_gc = qe_pin->controller;
265	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
266	unsigned long flags;
267
268	spin_lock_irqsave(&qe_gc->lock, flags);
269
270	/* Let's make it input by default, GPIO API is able to change that. */
271	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
272
273	spin_unlock_irqrestore(&qe_gc->lock, flags);
274	}
275	EXPORT_SYMBOL(qe_pin_set_gpio);
276
d14b3dd6	277	static int __init qe_add_gpiochips(void)
32def337 AV	278	{
	279	struct device_node *np;
	280
	281	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
	282	int ret;
	283	struct qe_gpio_chip *qe_gc;
	284	struct of_mm_gpio_chip *mm_gc;
32def337 AV	285	struct gpio_chip *gc;
	286
	287	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
	288	if (!qe_gc) {
	289	ret = -ENOMEM;
	290	goto err;
	291	}
	292
	293	spin_lock_init(&qe_gc->lock);
	294
	295	mm_gc = &qe_gc->mm_gc;
a19e3da5	296	gc = &mm_gc->gc;
32def337 AV	297
32def337 AV	298	mm_gc->save_regs = qe_gpio_save_regs;
32def337 AV	299	gc->ngpio = QE_PIO_PINS;
	300	gc->direction_input = qe_gpio_dir_in;
	301	gc->direction_output = qe_gpio_dir_out;
	302	gc->get = qe_gpio_get;
	303	gc->set = qe_gpio_set;
	304
	305	ret = of_mm_gpiochip_add(np, mm_gc);
	306	if (ret)
	307	goto err;
	308	continue;
	309	err:
	310	pr_err("%s: registration failed with status %d\n",
	311	np->full_name, ret);
	312	kfree(qe_gc);
	313	/* try others anyway */
	314	}
d14b3dd6	315	return 0;
32def337	316	}
d14b3dd6	317	arch_initcall(qe_add_gpiochips);