[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / sysdev / qe_lib / gpio.c

/*
 * QUICC Engine GPIOs
 *
 * Copyright (c) MontaVista Software, Inc. 2008.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <asm/qe.h>

struct qe_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	unsigned long pin_flags[QE_PIO_PINS];
#define QE_PIN_REQUESTED 0

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;

	/* saved_regs used to restore dedicated functions */
	struct qe_pio_regs saved_regs;
};

static inline struct qe_gpio_chip *
to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
{
	return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
}

static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	qe_gc->cpdata = in_be32(&regs->cpdata);
	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	return in_be32(&regs->cpdata) & pin_mask;
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (val)
		qe_gc->cpdata |= pin_mask;
	else
		qe_gc->cpdata &= ~pin_mask;

	out_be32(&regs->cpdata, qe_gc->cpdata);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}

static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	unsigned long flags;

	qe_gpio_set(gc, gpio, val);

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

struct qe_pin {
	/*
	 * The qe_gpio_chip name is unfortunate, we should change that to
	 * something like qe_pio_controller. Someday.
	 */
	struct qe_gpio_chip *controller;
	int num;
};

/**
 * qe_pin_request - Request a QE pin
 * @np:		device node to get a pin from
 * @index:	index of a pin in the device tree
 * Context:	non-atomic
 *
 * This function return qe_pin so that you could use it with the rest of
 * the QE Pin Multiplexing API.
 */
struct qe_pin *qe_pin_request(struct device_node *np, int index)
{
	struct qe_pin *qe_pin;
	struct device_node *gc;
	struct of_gpio_chip *of_gc = NULL;
	struct of_mm_gpio_chip *mm_gc;
	struct qe_gpio_chip *qe_gc;
	int err;
	int size;
	const void *gpio_spec;
	const u32 *gpio_cells;
	unsigned long flags;

	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	if (!qe_pin) {
		pr_debug("%s: can't allocate memory\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
					  &gc, &gpio_spec);
	if (err) {
		pr_debug("%s: can't parse gpios property\n", __func__);
		goto err0;
	}

	if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
		pr_debug("%s: tried to get a non-qe pin\n", __func__);
		err = -EINVAL;
		goto err1;
	}

	of_gc = gc->data;
	if (!of_gc) {
		pr_debug("%s: gpio controller %s isn't registered\n",
			 np->full_name, gc->full_name);
		err = -ENODEV;
		goto err1;
	}

	gpio_cells = of_get_property(gc, "#gpio-cells", &size);
	if (!gpio_cells || size != sizeof(*gpio_cells) ||
			*gpio_cells != of_gc->gpio_cells) {
		pr_debug("%s: wrong #gpio-cells for %s\n",
			 np->full_name, gc->full_name);
		err = -EINVAL;
		goto err1;
	}

	err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
	if (err < 0)
		goto err1;

	mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
	qe_gc = to_qe_gpio_chip(mm_gc);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
		qe_pin->controller = qe_gc;
		qe_pin->num = err;
		err = 0;
	} else {
		err = -EBUSY;
	}

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	if (!err)
		return qe_pin;
err1:
	of_node_put(gc);
err0:
	kfree(qe_pin);
	pr_debug("%s failed with status %d\n", __func__, err);
	return ERR_PTR(err);
}
EXPORT_SYMBOL(qe_pin_request);

/**
 * qe_pin_free - Free a pin
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function frees the qe_pin structure and makes a pin available
 * for further qe_pin_request() calls.
 */
void qe_pin_free(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	unsigned long flags;
	const int pin = qe_pin->num;

	spin_lock_irqsave(&qe_gc->lock, flags);
	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	spin_unlock_irqrestore(&qe_gc->lock, flags);

	kfree(qe_pin);
}
EXPORT_SYMBOL(qe_pin_free);

/**
 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function resets a pin to a dedicated peripheral function that
 * has been set up by the firmware.
 */
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	int pin = qe_pin->num;
	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (second_reg) {
		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	} else {
		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	}

	if (sregs->cpdata & mask1)
		qe_gc->cpdata |= mask1;
	else
		qe_gc->cpdata &= ~mask1;

	out_be32(&regs->cpdata, qe_gc->cpdata);
	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_dedicated);

/**
 * qe_pin_set_gpio - Set a pin to the GPIO mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function sets a pin to the GPIO mode.
 */
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	/* Let's make it input by default, GPIO API is able to change that. */
	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_gpio);

static int __init qe_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
		int ret;
		struct qe_gpio_chip *qe_gc;
		struct of_mm_gpio_chip *mm_gc;
		struct of_gpio_chip *of_gc;
		struct gpio_chip *gc;

		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
		if (!qe_gc) {
			ret = -ENOMEM;
			goto err;
		}

		spin_lock_init(&qe_gc->lock);

		mm_gc = &qe_gc->mm_gc;
		of_gc = &mm_gc->of_gc;
		gc = &of_gc->gc;

		mm_gc->save_regs = qe_gpio_save_regs;
		of_gc->gpio_cells = 2;
		gc->ngpio = QE_PIO_PINS;
		gc->direction_input = qe_gpio_dir_in;
		gc->direction_output = qe_gpio_dir_out;
		gc->get = qe_gpio_get;
		gc->set = qe_gpio_set;

		ret = of_mm_gpiochip_add(np, mm_gc);
		if (ret)
			goto err;
		continue;
err:
		pr_err("%s: registration failed with status %d\n",
		       np->full_name, ret);
		kfree(qe_gc);
		/* try others anyway */
	}
	return 0;
}
arch_initcall(qe_add_gpiochips);
Commit	Line	Data
32def337 AV	1	/*
	2	* QUICC Engine GPIOs
	3	*
	4	* Copyright (c) MontaVista Software, Inc. 2008.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
d14b3dd6	15	#include <linux/init.h>
32def337	16	#include <linux/spinlock.h>
1b9e8904	17	#include <linux/err.h>
32def337 AV	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20	#include <linux/of_gpio.h>
	21	#include <linux/gpio.h>
	22	#include <asm/qe.h>
	23
	24	struct qe_gpio_chip {
	25	struct of_mm_gpio_chip mm_gc;
	26	spinlock_t lock;
	27
1b9e8904 AV	28	unsigned long pin_flags[QE_PIO_PINS];
	29	#define QE_PIN_REQUESTED 0
	30
32def337 AV	31	/* shadowed data register to clear/set bits safely */
32def337 AV	32	u32 cpdata;
1b9e8904 AV	33
	34	/* saved_regs used to restore dedicated functions */
	35	struct qe_pio_regs saved_regs;
32def337 AV	36	};
	37
	38	static inline struct qe_gpio_chip *
	39	to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
	40	{
	41	return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
	42	}
	43
	44	static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
	45	{
	46	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	47	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	48
	49	qe_gc->cpdata = in_be32(&regs->cpdata);
1b9e8904 AV	50	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	51	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	52	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	53	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	54	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	55	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
32def337 AV	56	}
	57
	58	static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	59	{
	60	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	61	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	62	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	63
	64	return in_be32(&regs->cpdata) & pin_mask;
	65	}
	66
	67	static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	68	{
	69	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	70	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	71	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	72	unsigned long flags;
	73	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	74
	75	spin_lock_irqsave(&qe_gc->lock, flags);
	76
	77	if (val)
	78	qe_gc->cpdata \|= pin_mask;
	79	else
	80	qe_gc->cpdata &= ~pin_mask;
	81
	82	out_be32(&regs->cpdata, qe_gc->cpdata);
	83
	84	spin_unlock_irqrestore(&qe_gc->lock, flags);
	85	}
	86
	87	static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	88	{
	89	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	90	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	91	unsigned long flags;
	92
	93	spin_lock_irqsave(&qe_gc->lock, flags);
	94
	95	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
	96
	97	spin_unlock_irqrestore(&qe_gc->lock, flags);
	98
	99	return 0;
	100	}
	101
	102	static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	103	{
	104	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	105	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	106	unsigned long flags;
	107
1dcd8ffc MB	108	qe_gpio_set(gc, gpio, val);
1dcd8ffc MB	109
32def337 AV	110	spin_lock_irqsave(&qe_gc->lock, flags);
	111
	112	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
	113
	114	spin_unlock_irqrestore(&qe_gc->lock, flags);
	115
32def337 AV	116	return 0;
	117	}
	118
1b9e8904 AV	119	struct qe_pin {
	120	/*
	121	* The qe_gpio_chip name is unfortunate, we should change that to
	122	* something like qe_pio_controller. Someday.
	123	*/
	124	struct qe_gpio_chip *controller;
	125	int num;
	126	};
	127
	128	/**
	129	* qe_pin_request - Request a QE pin
	130	* @np: device node to get a pin from
	131	* @index: index of a pin in the device tree
	132	* Context: non-atomic
	133	*
	134	* This function return qe_pin so that you could use it with the rest of
	135	* the QE Pin Multiplexing API.
	136	*/
	137	struct qe_pin qe_pin_request(struct device_node np, int index)
	138	{
	139	struct qe_pin *qe_pin;
	140	struct device_node *gc;
	141	struct of_gpio_chip *of_gc = NULL;
	142	struct of_mm_gpio_chip *mm_gc;
	143	struct qe_gpio_chip *qe_gc;
	144	int err;
	145	int size;
	146	const void *gpio_spec;
	147	const u32 *gpio_cells;
	148	unsigned long flags;
	149
	150	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	151	if (!qe_pin) {
	152	pr_debug("%s: can't allocate memory\n", __func__);
	153	return ERR_PTR(-ENOMEM);
	154	}
	155
	156	err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
	157	&gc, &gpio_spec);
	158	if (err) {
	159	pr_debug("%s: can't parse gpios property\n", __func__);
	160	goto err0;
	161	}
	162
	163	if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
	164	pr_debug("%s: tried to get a non-qe pin\n", __func__);
	165	err = -EINVAL;
	166	goto err1;
	167	}
	168
	169	of_gc = gc->data;
	170	if (!of_gc) {
	171	pr_debug("%s: gpio controller %s isn't registered\n",
	172	np->full_name, gc->full_name);
	173	err = -ENODEV;
	174	goto err1;
	175	}
	176
	177	gpio_cells = of_get_property(gc, "#gpio-cells", &size);
	178	if (!gpio_cells \|\| size != sizeof(*gpio_cells) \|\|
	179	*gpio_cells != of_gc->gpio_cells) {
	180	pr_debug("%s: wrong #gpio-cells for %s\n",
	181	np->full_name, gc->full_name);
	182	err = -EINVAL;
183	goto err1;
184	}
185
186	err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
187	if (err < 0)
188	goto err1;
189
190	mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
191	qe_gc = to_qe_gpio_chip(mm_gc);
192
193	spin_lock_irqsave(&qe_gc->lock, flags);
194
195	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
196	qe_pin->controller = qe_gc;
197	qe_pin->num = err;
198	err = 0;
199	} else {
200	err = -EBUSY;
201	}
202
203	spin_unlock_irqrestore(&qe_gc->lock, flags);
204
205	if (!err)
206	return qe_pin;
207	err1:
208	of_node_put(gc);
209	err0:
210	kfree(qe_pin);
211	pr_debug("%s failed with status %d\n", __func__, err);
212	return ERR_PTR(err);
213	}
214	EXPORT_SYMBOL(qe_pin_request);
215
216	/**
217	* qe_pin_free - Free a pin
218	* @qe_pin: pointer to the qe_pin structure
219	* Context: any
220	*
221	* This function frees the qe_pin structure and makes a pin available
222	* for further qe_pin_request() calls.
223	*/
224	void qe_pin_free(struct qe_pin *qe_pin)
225	{
226	struct qe_gpio_chip *qe_gc = qe_pin->controller;
227	unsigned long flags;
228	const int pin = qe_pin->num;
229
230	spin_lock_irqsave(&qe_gc->lock, flags);
231	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
232	spin_unlock_irqrestore(&qe_gc->lock, flags);
233
234	kfree(qe_pin);
235	}
236	EXPORT_SYMBOL(qe_pin_free);
237
238	/**
239	* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
240	* @qe_pin: pointer to the qe_pin structure
241	* Context: any
242	*
243	* This function resets a pin to a dedicated peripheral function that
244	* has been set up by the firmware.
245	*/
246	void qe_pin_set_dedicated(struct qe_pin *qe_pin)
247	{
248	struct qe_gpio_chip *qe_gc = qe_pin->controller;
249	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
250	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
251	int pin = qe_pin->num;
252	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
253	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
254	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
255	unsigned long flags;
256
257	spin_lock_irqsave(&qe_gc->lock, flags);
258
259	if (second_reg) {
260	clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
261	clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
262	} else {
263	clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
264	clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
265	}
266
267	if (sregs->cpdata & mask1)
268	qe_gc->cpdata \|= mask1;
269	else
270	qe_gc->cpdata &= ~mask1;
271
272	out_be32(&regs->cpdata, qe_gc->cpdata);
273	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
274
275	spin_unlock_irqrestore(&qe_gc->lock, flags);
276	}
277	EXPORT_SYMBOL(qe_pin_set_dedicated);
278
279	/**
280	* qe_pin_set_gpio - Set a pin to the GPIO mode
281	* @qe_pin: pointer to the qe_pin structure
282	* Context: any
283	*
284	* This function sets a pin to the GPIO mode.
285	*/
286	void qe_pin_set_gpio(struct qe_pin *qe_pin)
287	{
288	struct qe_gpio_chip *qe_gc = qe_pin->controller;
289	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
290	unsigned long flags;
291
292	spin_lock_irqsave(&qe_gc->lock, flags);
293
294	/* Let's make it input by default, GPIO API is able to change that. */
295	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
296
297	spin_unlock_irqrestore(&qe_gc->lock, flags);
298	}
299	EXPORT_SYMBOL(qe_pin_set_gpio);
300
d14b3dd6	301	static int __init qe_add_gpiochips(void)
32def337 AV	302	{
	303	struct device_node *np;
	304
	305	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
	306	int ret;
	307	struct qe_gpio_chip *qe_gc;
	308	struct of_mm_gpio_chip *mm_gc;
	309	struct of_gpio_chip *of_gc;
	310	struct gpio_chip *gc;
	311
	312	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
	313	if (!qe_gc) {
	314	ret = -ENOMEM;
	315	goto err;
	316	}
	317
	318	spin_lock_init(&qe_gc->lock);
	319
	320	mm_gc = &qe_gc->mm_gc;
	321	of_gc = &mm_gc->of_gc;
	322	gc = &of_gc->gc;
	323
	324	mm_gc->save_regs = qe_gpio_save_regs;
	325	of_gc->gpio_cells = 2;
	326	gc->ngpio = QE_PIO_PINS;
	327	gc->direction_input = qe_gpio_dir_in;
	328	gc->direction_output = qe_gpio_dir_out;
	329	gc->get = qe_gpio_get;
	330	gc->set = qe_gpio_set;
	331
	332	ret = of_mm_gpiochip_add(np, mm_gc);
	333	if (ret)
	334	goto err;
	335	continue;
	336	err:
	337	pr_err("%s: registration failed with status %d\n",
	338	np->full_name, ret);
	339	kfree(qe_gc);
	340	/* try others anyway */
	341	}
d14b3dd6	342	return 0;
32def337	343	}
d14b3dd6	344	arch_initcall(qe_add_gpiochips);