[mirror_ubuntu-artful-kernel.git] / arch / powerpc / sysdev / qe_lib / qe_ic.c

/*
 * arch/powerpc/sysdev/qe_lib/qe_ic.c
 *
 * Copyright (C) 2006 Freescale Semicondutor, Inc.  All rights reserved.
 *
 * Author: Li Yang <leoli@freescale.com>
 * Based on code from Shlomi Gridish <gridish@freescale.com>
 *
 * QUICC ENGINE Interrupt Controller
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/stddef.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/device.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/qe_ic.h>

#include "qe_ic.h"

static DEFINE_RAW_SPINLOCK(qe_ic_lock);

static struct qe_ic_info qe_ic_info[] = {
	[1] = {
	       .mask = 0x00008000,
	       .mask_reg = QEIC_CIMR,
	       .pri_code = 0,
	       .pri_reg = QEIC_CIPWCC,
	       },
	[2] = {
	       .mask = 0x00004000,
	       .mask_reg = QEIC_CIMR,
	       .pri_code = 1,
	       .pri_reg = QEIC_CIPWCC,
	       },
	[3] = {
	       .mask = 0x00002000,
	       .mask_reg = QEIC_CIMR,
	       .pri_code = 2,
	       .pri_reg = QEIC_CIPWCC,
	       },
	[10] = {
		.mask = 0x00000040,
		.mask_reg = QEIC_CIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPZCC,
		},
	[11] = {
		.mask = 0x00000020,
		.mask_reg = QEIC_CIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPZCC,
		},
	[12] = {
		.mask = 0x00000010,
		.mask_reg = QEIC_CIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPZCC,
		},
	[13] = {
		.mask = 0x00000008,
		.mask_reg = QEIC_CIMR,
		.pri_code = 4,
		.pri_reg = QEIC_CIPZCC,
		},
	[14] = {
		.mask = 0x00000004,
		.mask_reg = QEIC_CIMR,
		.pri_code = 5,
		.pri_reg = QEIC_CIPZCC,
		},
	[15] = {
		.mask = 0x00000002,
		.mask_reg = QEIC_CIMR,
		.pri_code = 6,
		.pri_reg = QEIC_CIPZCC,
		},
	[20] = {
		.mask = 0x10000000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPRTA,
		},
	[25] = {
		.mask = 0x00800000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 0,
		.pri_reg = QEIC_CIPRTB,
		},
	[26] = {
		.mask = 0x00400000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPRTB,
		},
	[27] = {
		.mask = 0x00200000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPRTB,
		},
	[28] = {
		.mask = 0x00100000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPRTB,
		},
	[32] = {
		.mask = 0x80000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 0,
		.pri_reg = QEIC_CIPXCC,
		},
	[33] = {
		.mask = 0x40000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPXCC,
		},
	[34] = {
		.mask = 0x20000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPXCC,
		},
	[35] = {
		.mask = 0x10000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPXCC,
		},
	[36] = {
		.mask = 0x08000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 4,
		.pri_reg = QEIC_CIPXCC,
		},
	[40] = {
		.mask = 0x00800000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 0,
		.pri_reg = QEIC_CIPYCC,
		},
	[41] = {
		.mask = 0x00400000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPYCC,
		},
	[42] = {
		.mask = 0x00200000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPYCC,
		},
	[43] = {
		.mask = 0x00100000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPYCC,
		},
};

static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
			       u32 value)
{
	out_be32(base + (reg >> 2), value);
}

static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
{
	return irq_get_chip_data(virq);
}

static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
{
	return irq_data_get_irq_chip_data(d);
}

static void qe_ic_unmask_irq(struct irq_data *d)
{
	struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
	unsigned int src = irqd_to_hwirq(d);
	unsigned long flags;
	u32 temp;

	raw_spin_lock_irqsave(&qe_ic_lock, flags);

	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
		    temp | qe_ic_info[src].mask);

	raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
}

static void qe_ic_mask_irq(struct irq_data *d)
{
	struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
	unsigned int src = irqd_to_hwirq(d);
	unsigned long flags;
	u32 temp;

	raw_spin_lock_irqsave(&qe_ic_lock, flags);

	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
		    temp & ~qe_ic_info[src].mask);

	/* Flush the above write before enabling interrupts; otherwise,
	 * spurious interrupts will sometimes happen.  To be 100% sure
	 * that the write has reached the device before interrupts are
	 * enabled, the mask register would have to be read back; however,
	 * this is not required for correctness, only to avoid wasting
	 * time on a large number of spurious interrupts.  In testing,
	 * a sync reduced the observed spurious interrupts to zero.
	 */
	mb();

	raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
}

static struct irq_chip qe_ic_irq_chip = {
	.name = "QEIC",
	.irq_unmask = qe_ic_unmask_irq,
	.irq_mask = qe_ic_mask_irq,
	.irq_mask_ack = qe_ic_mask_irq,
};

static int qe_ic_host_match(struct irq_domain *h, struct device_node *node)
{
	/* Exact match, unless qe_ic node is NULL */
	return h->of_node == NULL || h->of_node == node;
}

static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	struct qe_ic *qe_ic = h->host_data;
	struct irq_chip *chip;

	if (qe_ic_info[hw].mask == 0) {
		printk(KERN_ERR "Can't map reserved IRQ\n");
		return -EINVAL;
	}
	/* Default chip */
	chip = &qe_ic->hc_irq;

	irq_set_chip_data(virq, qe_ic);
	irq_set_status_flags(virq, IRQ_LEVEL);

	irq_set_chip_and_handler(virq, chip, handle_level_irq);

	return 0;
}

static int qe_ic_host_xlate(struct irq_domain *h, struct device_node *ct,
			    const u32 * intspec, unsigned int intsize,
			    irq_hw_number_t * out_hwirq,
			    unsigned int *out_flags)
{
	*out_hwirq = intspec[0];
	if (intsize > 1)
		*out_flags = intspec[1];
	else
		*out_flags = IRQ_TYPE_NONE;
	return 0;
}

static struct irq_domain_ops qe_ic_host_ops = {
	.match = qe_ic_host_match,
	.map = qe_ic_host_map,
	.xlate = qe_ic_host_xlate,
};

/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
	int irq;

	BUG_ON(qe_ic == NULL);

	/* get the interrupt source vector. */
	irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;

	if (irq == 0)
		return NO_IRQ;

	return irq_linear_revmap(qe_ic->irqhost, irq);
}

/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
	int irq;

	BUG_ON(qe_ic == NULL);

	/* get the interrupt source vector. */
	irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;

	if (irq == 0)
		return NO_IRQ;

	return irq_linear_revmap(qe_ic->irqhost, irq);
}

void __init qe_ic_init(struct device_node *node, unsigned int flags,
		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
		void (*high_handler)(unsigned int irq, struct irq_desc *desc))
{
	struct qe_ic *qe_ic;
	struct resource res;
	u32 temp = 0, ret, high_active = 0;

	ret = of_address_to_resource(node, 0, &res);
	if (ret)
		return;

	qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
	if (qe_ic == NULL)
		return;

	qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
					       &qe_ic_host_ops, qe_ic);
	if (qe_ic->irqhost == NULL) {
		kfree(qe_ic);
		return;
	}

	qe_ic->regs = ioremap(res.start, resource_size(&res));

	qe_ic->hc_irq = qe_ic_irq_chip;

	qe_ic->virq_high = irq_of_parse_and_map(node, 0);
	qe_ic->virq_low = irq_of_parse_and_map(node, 1);

	if (qe_ic->virq_low == NO_IRQ) {
		printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
		kfree(qe_ic);
		return;
	}

	/* default priority scheme is grouped. If spread mode is    */
	/* required, configure cicr accordingly.                    */
	if (flags & QE_IC_SPREADMODE_GRP_W)
		temp |= CICR_GWCC;
	if (flags & QE_IC_SPREADMODE_GRP_X)
		temp |= CICR_GXCC;
	if (flags & QE_IC_SPREADMODE_GRP_Y)
		temp |= CICR_GYCC;
	if (flags & QE_IC_SPREADMODE_GRP_Z)
		temp |= CICR_GZCC;
	if (flags & QE_IC_SPREADMODE_GRP_RISCA)
		temp |= CICR_GRTA;
	if (flags & QE_IC_SPREADMODE_GRP_RISCB)
		temp |= CICR_GRTB;

	/* choose destination signal for highest priority interrupt */
	if (flags & QE_IC_HIGH_SIGNAL) {
		temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
		high_active = 1;
	}

	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);

	irq_set_handler_data(qe_ic->virq_low, qe_ic);
	irq_set_chained_handler(qe_ic->virq_low, low_handler);

	if (qe_ic->virq_high != NO_IRQ &&
			qe_ic->virq_high != qe_ic->virq_low) {
		irq_set_handler_data(qe_ic->virq_high, qe_ic);
		irq_set_chained_handler(qe_ic->virq_high, high_handler);
	}
}

void qe_ic_set_highest_priority(unsigned int virq, int high)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	u32 temp = 0;

	temp = qe_ic_read(qe_ic->regs, QEIC_CICR);

	temp &= ~CICR_HP_MASK;
	temp |= src << CICR_HP_SHIFT;

	temp &= ~CICR_HPIT_MASK;
	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;

	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
}

/* Set Priority level within its group, from 1 to 8 */
int qe_ic_set_priority(unsigned int virq, unsigned int priority)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	u32 temp;

	if (priority > 8 || priority == 0)
		return -EINVAL;
	if (src > 127)
		return -EINVAL;
	if (qe_ic_info[src].pri_reg == 0)
		return -EINVAL;

	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);

	if (priority < 4) {
		temp &= ~(0x7 << (32 - priority * 3));
		temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
	} else {
		temp &= ~(0x7 << (24 - priority * 3));
		temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
	}

	qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);

	return 0;
}

/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	u32 temp, control_reg = QEIC_CICNR, shift = 0;

	if (priority > 2 || priority == 0)
		return -EINVAL;

	switch (qe_ic_info[src].pri_reg) {
	case QEIC_CIPZCC:
		shift = CICNR_ZCC1T_SHIFT;
		break;
	case QEIC_CIPWCC:
		shift = CICNR_WCC1T_SHIFT;
		break;
	case QEIC_CIPYCC:
		shift = CICNR_YCC1T_SHIFT;
		break;
	case QEIC_CIPXCC:
		shift = CICNR_XCC1T_SHIFT;
		break;
	case QEIC_CIPRTA:
		shift = CRICR_RTA1T_SHIFT;
		control_reg = QEIC_CRICR;
		break;
	case QEIC_CIPRTB:
		shift = CRICR_RTB1T_SHIFT;
		control_reg = QEIC_CRICR;
		break;
	default:
		return -EINVAL;
	}

	shift += (2 - priority) * 2;
	temp = qe_ic_read(qe_ic->regs, control_reg);
	temp &= ~(SIGNAL_MASK << shift);
	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
	qe_ic_write(qe_ic->regs, control_reg, temp);

	return 0;
}

static struct bus_type qe_ic_subsys = {
	.name = "qe_ic",
	.dev_name = "qe_ic",
};

static struct device device_qe_ic = {
	.id = 0,
	.bus = &qe_ic_subsys,
};

static int __init init_qe_ic_sysfs(void)
{
	int rc;

	printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");

	rc = subsys_system_register(&qe_ic_subsys, NULL);
	if (rc) {
		printk(KERN_ERR "Failed registering qe_ic sys class\n");
		return -ENODEV;
	}
	rc = device_register(&device_qe_ic);
	if (rc) {
		printk(KERN_ERR "Failed registering qe_ic sys device\n");
		return -ENODEV;
	}
	return 0;
}

subsys_initcall(init_qe_ic_sysfs);
Commit	Line	Data
98658538 LY	1	/*
	2	* arch/powerpc/sysdev/qe_lib/qe_ic.c
	3	*
	4	* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
	5	*
	6	* Author: Li Yang <leoli@freescale.com>
	7	* Based on code from Shlomi Gridish <gridish@freescale.com>
	8	*
	9	* QUICC ENGINE Interrupt Controller
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/errno.h>
	20	#include <linux/reboot.h>
	21	#include <linux/slab.h>
	22	#include <linux/stddef.h>
	23	#include <linux/sched.h>
	24	#include <linux/signal.h>
98658538 LY	25	#include <linux/device.h>
	26	#include <linux/bootmem.h>
	27	#include <linux/spinlock.h>
	28	#include <asm/irq.h>
	29	#include <asm/io.h>
	30	#include <asm/prom.h>
	31	#include <asm/qe_ic.h>
	32
	33	#include "qe_ic.h"
	34
43a5a01b	35	static DEFINE_RAW_SPINLOCK(qe_ic_lock);
98658538 LY	36
	37	static struct qe_ic_info qe_ic_info[] = {
	38	[1] = {
	39	.mask = 0x00008000,
	40	.mask_reg = QEIC_CIMR,
	41	.pri_code = 0,
	42	.pri_reg = QEIC_CIPWCC,
	43	},
	44	[2] = {
	45	.mask = 0x00004000,
	46	.mask_reg = QEIC_CIMR,
	47	.pri_code = 1,
	48	.pri_reg = QEIC_CIPWCC,
	49	},
	50	[3] = {
	51	.mask = 0x00002000,
	52	.mask_reg = QEIC_CIMR,
	53	.pri_code = 2,
	54	.pri_reg = QEIC_CIPWCC,
	55	},
	56	[10] = {
	57	.mask = 0x00000040,
	58	.mask_reg = QEIC_CIMR,
	59	.pri_code = 1,
	60	.pri_reg = QEIC_CIPZCC,
	61	},
	62	[11] = {
	63	.mask = 0x00000020,
	64	.mask_reg = QEIC_CIMR,
	65	.pri_code = 2,
	66	.pri_reg = QEIC_CIPZCC,
	67	},
	68	[12] = {
	69	.mask = 0x00000010,
	70	.mask_reg = QEIC_CIMR,
	71	.pri_code = 3,
	72	.pri_reg = QEIC_CIPZCC,
	73	},
	74	[13] = {
	75	.mask = 0x00000008,
	76	.mask_reg = QEIC_CIMR,
	77	.pri_code = 4,
	78	.pri_reg = QEIC_CIPZCC,
	79	},
	80	[14] = {
	81	.mask = 0x00000004,
	82	.mask_reg = QEIC_CIMR,
	83	.pri_code = 5,
	84	.pri_reg = QEIC_CIPZCC,
	85	},
	86	[15] = {
	87	.mask = 0x00000002,
	88	.mask_reg = QEIC_CIMR,
	89	.pri_code = 6,
	90	.pri_reg = QEIC_CIPZCC,
	91	},
	92	[20] = {
	93	.mask = 0x10000000,
	94	.mask_reg = QEIC_CRIMR,
	95	.pri_code = 3,
	96	.pri_reg = QEIC_CIPRTA,
	97	},
	98	[25] = {
	99	.mask = 0x00800000,
100	.mask_reg = QEIC_CRIMR,
101	.pri_code = 0,
102	.pri_reg = QEIC_CIPRTB,
103	},
104	[26] = {
105	.mask = 0x00400000,
106	.mask_reg = QEIC_CRIMR,
107	.pri_code = 1,
108	.pri_reg = QEIC_CIPRTB,
109	},
110	[27] = {
111	.mask = 0x00200000,
112	.mask_reg = QEIC_CRIMR,
113	.pri_code = 2,
114	.pri_reg = QEIC_CIPRTB,
115	},
116	[28] = {
117	.mask = 0x00100000,
118	.mask_reg = QEIC_CRIMR,
119	.pri_code = 3,
120	.pri_reg = QEIC_CIPRTB,
121	},
122	[32] = {
123	.mask = 0x80000000,
124	.mask_reg = QEIC_CIMR,
125	.pri_code = 0,
126	.pri_reg = QEIC_CIPXCC,
127	},
128	[33] = {
129	.mask = 0x40000000,
130	.mask_reg = QEIC_CIMR,
131	.pri_code = 1,
132	.pri_reg = QEIC_CIPXCC,
133	},
134	[34] = {
135	.mask = 0x20000000,
136	.mask_reg = QEIC_CIMR,
137	.pri_code = 2,
138	.pri_reg = QEIC_CIPXCC,
139	},
140	[35] = {
141	.mask = 0x10000000,
142	.mask_reg = QEIC_CIMR,
143	.pri_code = 3,
144	.pri_reg = QEIC_CIPXCC,
145	},
146	[36] = {
147	.mask = 0x08000000,
148	.mask_reg = QEIC_CIMR,
149	.pri_code = 4,
150	.pri_reg = QEIC_CIPXCC,
151	},
152	[40] = {
153	.mask = 0x00800000,
154	.mask_reg = QEIC_CIMR,
155	.pri_code = 0,
156	.pri_reg = QEIC_CIPYCC,
157	},
158	[41] = {
159	.mask = 0x00400000,
160	.mask_reg = QEIC_CIMR,
161	.pri_code = 1,
162	.pri_reg = QEIC_CIPYCC,
163	},
164	[42] = {
165	.mask = 0x00200000,
166	.mask_reg = QEIC_CIMR,
167	.pri_code = 2,
168	.pri_reg = QEIC_CIPYCC,
169	},
170	[43] = {
171	.mask = 0x00100000,
172	.mask_reg = QEIC_CIMR,
173	.pri_code = 3,
174	.pri_reg = QEIC_CIPYCC,
175	},
176	};
177
178	static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
179	{
180	return in_be32(base + (reg >> 2));
181	}
182
183	static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
184	u32 value)
185	{
186	out_be32(base + (reg >> 2), value);
187	}
188
189	static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
190	{
ec775d0e	191	return irq_get_chip_data(virq);
3a0adfab LB	192	}
	193
	194	static inline struct qe_ic qe_ic_from_irq_data(struct irq_data d)
	195	{
	196	return irq_data_get_irq_chip_data(d);
98658538 LY	197	}
98658538 LY	198
3a0adfab	199	static void qe_ic_unmask_irq(struct irq_data *d)
98658538	200	{
3a0adfab	201	struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
476eb491	202	unsigned int src = irqd_to_hwirq(d);
98658538 LY	203	unsigned long flags;
	204	u32 temp;
	205
43a5a01b	206	raw_spin_lock_irqsave(&qe_ic_lock, flags);
98658538 LY	207
	208	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
	209	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
	210	temp \| qe_ic_info[src].mask);
	211
43a5a01b	212	raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
98658538 LY	213	}
98658538 LY	214
3a0adfab	215	static void qe_ic_mask_irq(struct irq_data *d)
98658538	216	{
3a0adfab	217	struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
476eb491	218	unsigned int src = irqd_to_hwirq(d);
98658538 LY	219	unsigned long flags;
	220	u32 temp;
	221
43a5a01b	222	raw_spin_lock_irqsave(&qe_ic_lock, flags);
98658538 LY	223
	224	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
	225	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
	226	temp & ~qe_ic_info[src].mask);
	227
2c1d2f34 SW	228	/* Flush the above write before enabling interrupts; otherwise,
	229	* spurious interrupts will sometimes happen. To be 100% sure
	230	* that the write has reached the device before interrupts are
	231	* enabled, the mask register would have to be read back; however,
	232	* this is not required for correctness, only to avoid wasting
	233	* time on a large number of spurious interrupts. In testing,
	234	* a sync reduced the observed spurious interrupts to zero.
	235	*/
	236	mb();
98658538	237
43a5a01b	238	raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
98658538 LY	239	}
	240
	241	static struct irq_chip qe_ic_irq_chip = {
fc380c0c	242	.name = "QEIC",
3a0adfab LB	243	.irq_unmask = qe_ic_unmask_irq,
	244	.irq_mask = qe_ic_mask_irq,
	245	.irq_mask_ack = qe_ic_mask_irq,
98658538 LY	246	};
98658538 LY	247
bae1d8f1	248	static int qe_ic_host_match(struct irq_domain h, struct device_node node)
98658538	249	{
98658538	250	/* Exact match, unless qe_ic node is NULL */
52964f87	251	return h->of_node == NULL \|\| h->of_node == node;
98658538 LY	252	}
98658538 LY	253
bae1d8f1	254	static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
98658538 LY	255	irq_hw_number_t hw)
	256	{
	257	struct qe_ic *qe_ic = h->host_data;
	258	struct irq_chip *chip;
	259
	260	if (qe_ic_info[hw].mask == 0) {
8354be9c	261	printk(KERN_ERR "Can't map reserved IRQ\n");
98658538 LY	262	return -EINVAL;
	263	}
	264	/* Default chip */
	265	chip = &qe_ic->hc_irq;
	266
ec775d0e	267	irq_set_chip_data(virq, qe_ic);
98488db9	268	irq_set_status_flags(virq, IRQ_LEVEL);
98658538	269
ec775d0e	270	irq_set_chip_and_handler(virq, chip, handle_level_irq);
98658538 LY	271
	272	return 0;
	273	}
	274
bae1d8f1	275	static int qe_ic_host_xlate(struct irq_domain h, struct device_node ct,
40d50cf7	276	const u32 * intspec, unsigned int intsize,
98658538 LY	277	irq_hw_number_t * out_hwirq,
	278	unsigned int *out_flags)
	279	{
	280	*out_hwirq = intspec[0];
	281	if (intsize > 1)
	282	*out_flags = intspec[1];
	283	else
	284	*out_flags = IRQ_TYPE_NONE;
	285	return 0;
	286	}
	287
bae1d8f1	288	static struct irq_domain_ops qe_ic_host_ops = {
98658538 LY	289	.match = qe_ic_host_match,
	290	.map = qe_ic_host_map,
	291	.xlate = qe_ic_host_xlate,
	292	};
	293
	294	/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
35a84c2f	295	unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
98658538 LY	296	{
	297	int irq;
	298
	299	BUG_ON(qe_ic == NULL);
	300
	301	/* get the interrupt source vector. */
	302	irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
	303
	304	if (irq == 0)
	305	return NO_IRQ;
	306
	307	return irq_linear_revmap(qe_ic->irqhost, irq);
	308	}
	309
	310	/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
35a84c2f	311	unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
98658538 LY	312	{
	313	int irq;
	314
	315	BUG_ON(qe_ic == NULL);
	316
	317	/* get the interrupt source vector. */
	318	irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
	319
	320	if (irq == 0)
	321	return NO_IRQ;
	322
	323	return irq_linear_revmap(qe_ic->irqhost, irq);
	324	}
	325
cccd2102 AV	326	void __init qe_ic_init(struct device_node *node, unsigned int flags,
	327	void (low_handler)(unsigned int irq, struct irq_desc desc),
	328	void (high_handler)(unsigned int irq, struct irq_desc desc))
98658538 LY	329	{
	330	struct qe_ic *qe_ic;
	331	struct resource res;
	332	u32 temp = 0, ret, high_active = 0;
	333
2272a55f ME	334	ret = of_address_to_resource(node, 0, &res);
	335	if (ret)
	336	return;
	337
ea96025a	338	qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
98658538 LY	339	if (qe_ic == NULL)
	340	return;
	341
a8db8cf0 GL	342	qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
a8db8cf0 GL	343	&qe_ic_host_ops, qe_ic);
3475dd8a JL	344	if (qe_ic->irqhost == NULL) {
3475dd8a JL	345	kfree(qe_ic);
98658538	346	return;
3475dd8a	347	}
98658538	348
28f65c11	349	qe_ic->regs = ioremap(res.start, resource_size(&res));
98658538	350
98658538 LY	351	qe_ic->hc_irq = qe_ic_irq_chip;
	352
	353	qe_ic->virq_high = irq_of_parse_and_map(node, 0);
	354	qe_ic->virq_low = irq_of_parse_and_map(node, 1);
	355
	356	if (qe_ic->virq_low == NO_IRQ) {
	357	printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
3475dd8a	358	kfree(qe_ic);
98658538 LY	359	return;
	360	}
	361
	362	/* default priority scheme is grouped. If spread mode is */
	363	/* required, configure cicr accordingly. */
	364	if (flags & QE_IC_SPREADMODE_GRP_W)
	365	temp \|= CICR_GWCC;
	366	if (flags & QE_IC_SPREADMODE_GRP_X)
	367	temp \|= CICR_GXCC;
	368	if (flags & QE_IC_SPREADMODE_GRP_Y)
	369	temp \|= CICR_GYCC;
	370	if (flags & QE_IC_SPREADMODE_GRP_Z)
	371	temp \|= CICR_GZCC;
	372	if (flags & QE_IC_SPREADMODE_GRP_RISCA)
	373	temp \|= CICR_GRTA;
	374	if (flags & QE_IC_SPREADMODE_GRP_RISCB)
	375	temp \|= CICR_GRTB;
	376
	377	/* choose destination signal for highest priority interrupt */
	378	if (flags & QE_IC_HIGH_SIGNAL) {
	379	temp \|= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
	380	high_active = 1;
	381	}
	382
	383	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
	384
ec775d0e TG	385	irq_set_handler_data(qe_ic->virq_low, qe_ic);
ec775d0e TG	386	irq_set_chained_handler(qe_ic->virq_low, low_handler);
98658538	387
cccd2102 AV	388	if (qe_ic->virq_high != NO_IRQ &&
cccd2102 AV	389	qe_ic->virq_high != qe_ic->virq_low) {
ec775d0e TG	390	irq_set_handler_data(qe_ic->virq_high, qe_ic);
ec775d0e TG	391	irq_set_chained_handler(qe_ic->virq_high, high_handler);
98658538	392	}
98658538 LY	393	}
	394
	395	void qe_ic_set_highest_priority(unsigned int virq, int high)
	396	{
	397	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	398	unsigned int src = virq_to_hw(virq);
	399	u32 temp = 0;
	400
	401	temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
	402
	403	temp &= ~CICR_HP_MASK;
	404	temp \|= src << CICR_HP_SHIFT;
	405
	406	temp &= ~CICR_HPIT_MASK;
	407	temp \|= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
	408
	409	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
	410	}
	411
	412	/* Set Priority level within its group, from 1 to 8 */
	413	int qe_ic_set_priority(unsigned int virq, unsigned int priority)
	414	{
	415	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	416	unsigned int src = virq_to_hw(virq);
	417	u32 temp;
	418
	419	if (priority > 8 \|\| priority == 0)
	420	return -EINVAL;
	421	if (src > 127)
	422	return -EINVAL;
	423	if (qe_ic_info[src].pri_reg == 0)
	424	return -EINVAL;
	425
	426	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
	427
	428	if (priority < 4) {
	429	temp &= ~(0x7 << (32 - priority * 3));
	430	temp \|= qe_ic_info[src].pri_code << (32 - priority * 3);
	431	} else {
	432	temp &= ~(0x7 << (24 - priority * 3));
	433	temp \|= qe_ic_info[src].pri_code << (24 - priority * 3);
	434	}
	435
	436	qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
	437
	438	return 0;
	439	}
	440
	441	/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
	442	int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
	443	{
	444	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	445	unsigned int src = virq_to_hw(virq);
	446	u32 temp, control_reg = QEIC_CICNR, shift = 0;
	447
	448	if (priority > 2 \|\| priority == 0)
	449	return -EINVAL;
	450
	451	switch (qe_ic_info[src].pri_reg) {
	452	case QEIC_CIPZCC:
	453	shift = CICNR_ZCC1T_SHIFT;
	454	break;
	455	case QEIC_CIPWCC:
	456	shift = CICNR_WCC1T_SHIFT;
457	break;
458	case QEIC_CIPYCC:
459	shift = CICNR_YCC1T_SHIFT;
460	break;
461	case QEIC_CIPXCC:
462	shift = CICNR_XCC1T_SHIFT;
463	break;
464	case QEIC_CIPRTA:
465	shift = CRICR_RTA1T_SHIFT;
466	control_reg = QEIC_CRICR;
467	break;
468	case QEIC_CIPRTB:
469	shift = CRICR_RTB1T_SHIFT;
470	control_reg = QEIC_CRICR;
471	break;
472	default:
473	return -EINVAL;
474	}
475
476	shift += (2 - priority) * 2;
477	temp = qe_ic_read(qe_ic->regs, control_reg);
478	temp &= ~(SIGNAL_MASK << shift);
479	temp \|= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
480	qe_ic_write(qe_ic->regs, control_reg, temp);
481
482	return 0;
483	}
484
cfde779f	485	static struct bus_type qe_ic_subsys = {
af5ca3f4	486	.name = "qe_ic",
cfde779f	487	.dev_name = "qe_ic",
98658538 LY	488	};
98658538 LY	489
cfde779f	490	static struct device device_qe_ic = {
98658538	491	.id = 0,
cfde779f	492	.bus = &qe_ic_subsys,
98658538 LY	493	};
	494
	495	static int __init init_qe_ic_sysfs(void)
	496	{
	497	int rc;
	498
	499	printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
	500
cfde779f	501	rc = subsys_system_register(&qe_ic_subsys, NULL);
98658538 LY	502	if (rc) {
	503	printk(KERN_ERR "Failed registering qe_ic sys class\n");
	504	return -ENODEV;
	505	}
cfde779f	506	rc = device_register(&device_qe_ic);
98658538 LY	507	if (rc) {
	508	printk(KERN_ERR "Failed registering qe_ic sys device\n");
	509	return -ENODEV;
	510	}
	511	return 0;
	512	}
	513
	514	subsys_initcall(init_qe_ic_sysfs);