[mirror_ubuntu-kernels.git] / arch / powerpc / sysdev / simple_gpio.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Simple Memory-Mapped GPIOs
 *
 * Copyright (c) MontaVista Software, Inc. 2008.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <asm/prom.h>
#include "simple_gpio.h"

struct u8_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	/* shadowed data register to clear/set bits safely */
	u8 data;
};

static u8 u8_pin2mask(unsigned int pin)
{
	return 1 << (8 - 1 - pin);
}

static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	return !!(in_8(mm_gc->regs) & u8_pin2mask(gpio));
}

static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct u8_gpio_chip *u8_gc = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&u8_gc->lock, flags);

	if (val)
		u8_gc->data |= u8_pin2mask(gpio);
	else
		u8_gc->data &= ~u8_pin2mask(gpio);

	out_8(mm_gc->regs, u8_gc->data);

	spin_unlock_irqrestore(&u8_gc->lock, flags);
}

static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	return 0;
}

static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	u8_gpio_set(gc, gpio, val);
	return 0;
}

static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct u8_gpio_chip *u8_gc =
		container_of(mm_gc, struct u8_gpio_chip, mm_gc);

	u8_gc->data = in_8(mm_gc->regs);
}

static int __init u8_simple_gpiochip_add(struct device_node *np)
{
	int ret;
	struct u8_gpio_chip *u8_gc;
	struct of_mm_gpio_chip *mm_gc;
	struct gpio_chip *gc;

	u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
	if (!u8_gc)
		return -ENOMEM;

	spin_lock_init(&u8_gc->lock);

	mm_gc = &u8_gc->mm_gc;
	gc = &mm_gc->gc;

	mm_gc->save_regs = u8_gpio_save_regs;
	gc->ngpio = 8;
	gc->direction_input = u8_gpio_dir_in;
	gc->direction_output = u8_gpio_dir_out;
	gc->get = u8_gpio_get;
	gc->set = u8_gpio_set;

	ret = of_mm_gpiochip_add_data(np, mm_gc, u8_gc);
	if (ret)
		goto err;
	return 0;
err:
	kfree(u8_gc);
	return ret;
}

void __init simple_gpiochip_init(const char *compatible)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, compatible) {
		int ret;
		struct resource r;

		ret = of_address_to_resource(np, 0, &r);
		if (ret)
			goto err;

		switch (resource_size(&r)) {
		case 1:
			ret = u8_simple_gpiochip_add(np);
			if (ret)
				goto err;
			break;
		default:
			/*
			 * Whenever you need support for GPIO bank width > 1,
			 * please just turn u8_ code into huge macros, and
			 * construct needed uX_ code with it.
			 */
			ret = -ENOSYS;
			goto err;
		}
		continue;
err:
		pr_err("%pOF: registration failed, status %d\n", np, ret);
	}
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
3d64de9c AV	2	/*
	3	* Simple Memory-Mapped GPIOs
	4	*
	5	* Copyright (c) MontaVista Software, Inc. 2008.
	6	*
	7	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
3d64de9c AV	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/kernel.h>
3d64de9c AV	12	#include <linux/spinlock.h>
	13	#include <linux/types.h>
	14	#include <linux/ioport.h>
	15	#include <linux/io.h>
	16	#include <linux/of.h>
	17	#include <linux/of_gpio.h>
937daafc	18	#include <linux/gpio/driver.h>
5a0e3ad6	19	#include <linux/slab.h>
3d64de9c AV	20	#include <asm/prom.h>
	21	#include "simple_gpio.h"
	22
	23	struct u8_gpio_chip {
	24	struct of_mm_gpio_chip mm_gc;
	25	spinlock_t lock;
	26
	27	/* shadowed data register to clear/set bits safely */
	28	u8 data;
	29	};
	30
3d64de9c AV	31	static u8 u8_pin2mask(unsigned int pin)
	32	{
	33	return 1 << (8 - 1 - pin);
	34	}
	35
	36	static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	37	{
	38	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	39
a4ce4b8d	40	return !!(in_8(mm_gc->regs) & u8_pin2mask(gpio));
3d64de9c AV	41	}
	42
	43	static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	44	{
	45	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
937daafc	46	struct u8_gpio_chip *u8_gc = gpiochip_get_data(gc);
3d64de9c AV	47	unsigned long flags;
	48
	49	spin_lock_irqsave(&u8_gc->lock, flags);
	50
	51	if (val)
	52	u8_gc->data \|= u8_pin2mask(gpio);
	53	else
	54	u8_gc->data &= ~u8_pin2mask(gpio);
	55
	56	out_8(mm_gc->regs, u8_gc->data);
	57
	58	spin_unlock_irqrestore(&u8_gc->lock, flags);
	59	}
	60
	61	static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	62	{
	63	return 0;
	64	}
	65
	66	static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	67	{
	68	u8_gpio_set(gc, gpio, val);
	69	return 0;
	70	}
	71
	72	static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
	73	{
6f553912 CL	74	struct u8_gpio_chip *u8_gc =
6f553912 CL	75	container_of(mm_gc, struct u8_gpio_chip, mm_gc);
3d64de9c AV	76
	77	u8_gc->data = in_8(mm_gc->regs);
	78	}
	79
	80	static int __init u8_simple_gpiochip_add(struct device_node *np)
	81	{
	82	int ret;
	83	struct u8_gpio_chip *u8_gc;
	84	struct of_mm_gpio_chip *mm_gc;
3d64de9c AV	85	struct gpio_chip *gc;
	86
	87	u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
	88	if (!u8_gc)
	89	return -ENOMEM;
	90
	91	spin_lock_init(&u8_gc->lock);
	92
	93	mm_gc = &u8_gc->mm_gc;
a19e3da5	94	gc = &mm_gc->gc;
3d64de9c AV	95
3d64de9c AV	96	mm_gc->save_regs = u8_gpio_save_regs;
3d64de9c AV	97	gc->ngpio = 8;
	98	gc->direction_input = u8_gpio_dir_in;
	99	gc->direction_output = u8_gpio_dir_out;
	100	gc->get = u8_gpio_get;
	101	gc->set = u8_gpio_set;
	102
937daafc	103	ret = of_mm_gpiochip_add_data(np, mm_gc, u8_gc);
3d64de9c AV	104	if (ret)
	105	goto err;
	106	return 0;
	107	err:
	108	kfree(u8_gc);
	109	return ret;
	110	}
	111
	112	void __init simple_gpiochip_init(const char *compatible)
	113	{
	114	struct device_node *np;
	115
	116	for_each_compatible_node(np, NULL, compatible) {
	117	int ret;
	118	struct resource r;
	119
	120	ret = of_address_to_resource(np, 0, &r);
	121	if (ret)
	122	goto err;
	123
	124	switch (resource_size(&r)) {
	125	case 1:
	126	ret = u8_simple_gpiochip_add(np);
	127	if (ret)
	128	goto err;
	129	break;
	130	default:
	131	/*
	132	* Whenever you need support for GPIO bank width > 1,
	133	* please just turn u8_ code into huge macros, and
	134	* construct needed uX_ code with it.
	135	*/
	136	ret = -ENOSYS;
	137	goto err;
	138	}
	139	continue;
	140	err:
b7c670d6	141	pr_err("%pOF: registration failed, status %d\n", np, ret);
3d64de9c AV	142	}
3d64de9c AV	143	}