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2b9d7467 ZR |
1 | /* |
2 | * Common routines for Tundra Semiconductor TSI108 host bridge. | |
3 | * | |
4 | * 2004-2005 (c) Tundra Semiconductor Corp. | |
5 | * Author: Alex Bounine (alexandreb@tundra.com) | |
5873c9bd ZR |
6 | * Author: Roy Zang (tie-fei.zang@freescale.com) |
7 | * Add pci interrupt router host | |
2b9d7467 ZR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the Free | |
11 | * Software Foundation; either version 2 of the License, or (at your option) | |
12 | * any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
21 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/interrupt.h> | |
30 | ||
2b9d7467 ZR |
31 | #include <asm/byteorder.h> |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
34 | #include <asm/uaccess.h> | |
35 | #include <asm/machdep.h> | |
36 | #include <asm/pci-bridge.h> | |
37 | #include <asm/tsi108.h> | |
08390db0 | 38 | #include <asm/tsi108_pci.h> |
2b9d7467 ZR |
39 | #include <asm/tsi108_irq.h> |
40 | #include <asm/prom.h> | |
41 | ||
42 | #undef DEBUG | |
43 | #ifdef DEBUG | |
44 | #define DBG(x...) printk(x) | |
45 | #else | |
46 | #define DBG(x...) | |
47 | #endif | |
48 | ||
49 | #define tsi_mk_config_addr(bus, devfunc, offset) \ | |
50 | ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base) | |
51 | ||
52 | u32 tsi108_pci_cfg_base; | |
05ad6a91 | 53 | static u32 tsi108_pci_cfg_phys; |
2b9d7467 | 54 | u32 tsi108_csr_vir_base; |
5873c9bd ZR |
55 | static struct device_node *pci_irq_node; |
56 | static struct irq_host *pci_irq_host; | |
2b9d7467 ZR |
57 | |
58 | extern u32 get_vir_csrbase(void); | |
59 | extern u32 tsi108_read_reg(u32 reg_offset); | |
60 | extern void tsi108_write_reg(u32 reg_offset, u32 val); | |
61 | ||
62 | int | |
63 | tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc, | |
64 | int offset, int len, u32 val) | |
65 | { | |
66 | volatile unsigned char *cfg_addr; | |
7d52c7b0 | 67 | struct pci_controller *hose = bus->sysdata; |
2b9d7467 ZR |
68 | |
69 | if (ppc_md.pci_exclude_device) | |
7d52c7b0 | 70 | if (ppc_md.pci_exclude_device(hose, bus->number, devfunc)) |
2b9d7467 ZR |
71 | return PCIBIOS_DEVICE_NOT_FOUND; |
72 | ||
73 | cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number, | |
74 | devfunc, offset) | | |
75 | (offset & 0x03)); | |
76 | ||
77 | #ifdef DEBUG | |
78 | printk("PCI CFG write : "); | |
79 | printk("%d:0x%x:0x%x ", bus->number, devfunc, offset); | |
80 | printk("%d ADDR=0x%08x ", len, (uint) cfg_addr); | |
81 | printk("data = 0x%08x\n", val); | |
82 | #endif | |
83 | ||
84 | switch (len) { | |
85 | case 1: | |
86 | out_8((u8 *) cfg_addr, val); | |
87 | break; | |
88 | case 2: | |
89 | out_le16((u16 *) cfg_addr, val); | |
90 | break; | |
91 | default: | |
92 | out_le32((u32 *) cfg_addr, val); | |
93 | break; | |
94 | } | |
95 | ||
96 | return PCIBIOS_SUCCESSFUL; | |
97 | } | |
98 | ||
99 | void tsi108_clear_pci_error(u32 pci_cfg_base) | |
100 | { | |
101 | u32 err_stat, err_addr, pci_stat; | |
102 | ||
103 | /* | |
104 | * Quietly clear PB and PCI error flags set as result | |
105 | * of PCI/X configuration read requests. | |
106 | */ | |
107 | ||
108 | /* Read PB Error Log Registers */ | |
109 | ||
110 | err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS); | |
111 | err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR); | |
112 | ||
113 | if (err_stat & TSI108_PB_ERRCS_ES) { | |
114 | /* Clear error flag */ | |
115 | tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS, | |
116 | TSI108_PB_ERRCS_ES); | |
117 | ||
118 | /* Clear read error reported in PB_ISR */ | |
119 | tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR, | |
120 | TSI108_PB_ISR_PBS_RD_ERR); | |
121 | ||
122 | /* Clear PCI/X bus cfg errors if applicable */ | |
123 | if ((err_addr & 0xFF000000) == pci_cfg_base) { | |
124 | pci_stat = | |
125 | tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR); | |
126 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR, | |
127 | pci_stat); | |
128 | } | |
129 | } | |
130 | ||
131 | return; | |
132 | } | |
133 | ||
134 | #define __tsi108_read_pci_config(x, addr, op) \ | |
135 | __asm__ __volatile__( \ | |
136 | " "op" %0,0,%1\n" \ | |
137 | "1: eieio\n" \ | |
138 | "2:\n" \ | |
139 | ".section .fixup,\"ax\"\n" \ | |
140 | "3: li %0,-1\n" \ | |
141 | " b 2b\n" \ | |
142 | ".section __ex_table,\"a\"\n" \ | |
143 | " .align 2\n" \ | |
144 | " .long 1b,3b\n" \ | |
145 | ".text" \ | |
146 | : "=r"(x) : "r"(addr)) | |
147 | ||
148 | int | |
149 | tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
150 | int len, u32 * val) | |
151 | { | |
152 | volatile unsigned char *cfg_addr; | |
7d52c7b0 | 153 | struct pci_controller *hose = bus->sysdata; |
2b9d7467 ZR |
154 | u32 temp; |
155 | ||
156 | if (ppc_md.pci_exclude_device) | |
7d52c7b0 | 157 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
2b9d7467 ZR |
158 | return PCIBIOS_DEVICE_NOT_FOUND; |
159 | ||
160 | cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number, | |
161 | devfn, | |
162 | offset) | (offset & | |
163 | 0x03)); | |
164 | ||
165 | switch (len) { | |
166 | case 1: | |
167 | __tsi108_read_pci_config(temp, cfg_addr, "lbzx"); | |
168 | break; | |
169 | case 2: | |
170 | __tsi108_read_pci_config(temp, cfg_addr, "lhbrx"); | |
171 | break; | |
172 | default: | |
173 | __tsi108_read_pci_config(temp, cfg_addr, "lwbrx"); | |
174 | break; | |
175 | } | |
176 | ||
177 | *val = temp; | |
178 | ||
179 | #ifdef DEBUG | |
180 | if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) { | |
181 | printk("PCI CFG read : "); | |
182 | printk("%d:0x%x:0x%x ", bus->number, devfn, offset); | |
183 | printk("%d ADDR=0x%08x ", len, (uint) cfg_addr); | |
184 | printk("data = 0x%x\n", *val); | |
185 | } | |
186 | #endif | |
187 | return PCIBIOS_SUCCESSFUL; | |
188 | } | |
189 | ||
190 | void tsi108_clear_pci_cfg_error(void) | |
191 | { | |
05ad6a91 | 192 | tsi108_clear_pci_error(tsi108_pci_cfg_phys); |
2b9d7467 ZR |
193 | } |
194 | ||
195 | static struct pci_ops tsi108_direct_pci_ops = { | |
196 | tsi108_direct_read_config, | |
197 | tsi108_direct_write_config | |
198 | }; | |
199 | ||
05ad6a91 | 200 | int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary) |
2b9d7467 ZR |
201 | { |
202 | int len; | |
203 | struct pci_controller *hose; | |
204 | struct resource rsrc; | |
88c80594 | 205 | const int *bus_range; |
05ad6a91 | 206 | int has_address = 0; |
2b9d7467 ZR |
207 | |
208 | /* PCI Config mapping */ | |
05ad6a91 JB |
209 | tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE); |
210 | tsi108_pci_cfg_phys = cfg_phys; | |
2b9d7467 ZR |
211 | DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__, |
212 | tsi108_pci_cfg_base); | |
213 | ||
214 | /* Fetch host bridge registers address */ | |
215 | has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); | |
216 | ||
217 | /* Get bus range if any */ | |
e2eb6392 | 218 | bus_range = of_get_property(dev, "bus-range", &len); |
2b9d7467 ZR |
219 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
220 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
221 | " bus 0\n", dev->full_name); | |
222 | } | |
223 | ||
224 | hose = pcibios_alloc_controller(); | |
225 | ||
226 | if (!hose) { | |
227 | printk("PCI Host bridge init failed\n"); | |
228 | return -ENOMEM; | |
229 | } | |
230 | hose->arch_data = dev; | |
2b9d7467 ZR |
231 | |
232 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
233 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
234 | ||
235 | (hose)->ops = &tsi108_direct_pci_ops; | |
236 | ||
c4342ff9 | 237 | printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " |
2b9d7467 ZR |
238 | "Firmware bus number: %d->%d\n", |
239 | rsrc.start, hose->first_busno, hose->last_busno); | |
240 | ||
241 | /* Interpret the "ranges" property */ | |
242 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
243 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Low level utility functions | |
249 | */ | |
250 | ||
251 | static void tsi108_pci_int_mask(u_int irq) | |
252 | { | |
253 | u_int irp_cfg; | |
254 | int int_line = (irq - IRQ_PCI_INTAD_BASE); | |
255 | ||
256 | irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); | |
257 | mb(); | |
258 | irp_cfg |= (1 << int_line); /* INTx_DIR = output */ | |
259 | irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */ | |
260 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg); | |
261 | mb(); | |
262 | irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); | |
263 | } | |
264 | ||
265 | static void tsi108_pci_int_unmask(u_int irq) | |
266 | { | |
267 | u_int irp_cfg; | |
268 | int int_line = (irq - IRQ_PCI_INTAD_BASE); | |
269 | ||
270 | irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); | |
271 | mb(); | |
272 | irp_cfg &= ~(1 << int_line); | |
273 | irp_cfg |= (3 << (8 + (int_line * 2))); | |
274 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg); | |
275 | mb(); | |
276 | } | |
277 | ||
278 | static void init_pci_source(void) | |
279 | { | |
280 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, | |
281 | 0x0000ff00); | |
282 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, | |
283 | TSI108_PCI_IRP_ENABLE_P_INT); | |
284 | mb(); | |
285 | } | |
286 | ||
c4342ff9 | 287 | static inline unsigned int get_pci_source(void) |
2b9d7467 ZR |
288 | { |
289 | u_int temp = 0; | |
290 | int irq = -1; | |
291 | int i; | |
292 | u_int pci_irp_stat; | |
293 | static int mask = 0; | |
294 | ||
295 | /* Read PCI/X block interrupt status register */ | |
296 | pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT); | |
297 | mb(); | |
298 | ||
299 | if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) { | |
300 | /* Process Interrupt from PCI bus INTA# - INTD# lines */ | |
301 | temp = | |
302 | tsi108_read_reg(TSI108_PCI_OFFSET + | |
303 | TSI108_PCI_IRP_INTAD) & 0xf; | |
304 | mb(); | |
305 | for (i = 0; i < 4; i++, mask++) { | |
306 | if (temp & (1 << mask % 4)) { | |
307 | irq = IRQ_PCI_INTA + mask % 4; | |
308 | mask++; | |
309 | break; | |
310 | } | |
311 | } | |
312 | ||
313 | /* Disable interrupts from PCI block */ | |
314 | temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); | |
315 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, | |
316 | temp & ~TSI108_PCI_IRP_ENABLE_P_INT); | |
317 | mb(); | |
318 | (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); | |
319 | mb(); | |
320 | } | |
321 | #ifdef DEBUG | |
322 | else { | |
323 | printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n"); | |
324 | pci_irp_stat = | |
325 | tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT); | |
326 | temp = | |
327 | tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD); | |
328 | mb(); | |
329 | printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp); | |
330 | temp = | |
331 | tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); | |
332 | mb(); | |
333 | printk("cfg_ctl=0x%08x ", temp); | |
334 | temp = | |
335 | tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); | |
336 | mb(); | |
337 | printk("irp_enable=0x%08x\n", temp); | |
338 | } | |
339 | #endif /* end of DEBUG */ | |
340 | ||
341 | return irq; | |
342 | } | |
343 | ||
344 | ||
345 | /* | |
346 | * Linux descriptor level callbacks | |
347 | */ | |
348 | ||
349 | static void tsi108_pci_irq_enable(u_int irq) | |
350 | { | |
351 | tsi108_pci_int_unmask(irq); | |
352 | } | |
353 | ||
354 | static void tsi108_pci_irq_disable(u_int irq) | |
355 | { | |
356 | tsi108_pci_int_mask(irq); | |
357 | } | |
358 | ||
359 | static void tsi108_pci_irq_ack(u_int irq) | |
360 | { | |
361 | tsi108_pci_int_mask(irq); | |
362 | } | |
363 | ||
364 | static void tsi108_pci_irq_end(u_int irq) | |
365 | { | |
366 | tsi108_pci_int_unmask(irq); | |
367 | ||
368 | /* Enable interrupts from PCI block */ | |
369 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, | |
370 | tsi108_read_reg(TSI108_PCI_OFFSET + | |
371 | TSI108_PCI_IRP_ENABLE) | | |
372 | TSI108_PCI_IRP_ENABLE_P_INT); | |
373 | mb(); | |
374 | } | |
375 | ||
376 | /* | |
377 | * Interrupt controller descriptor for cascaded PCI interrupt controller. | |
378 | */ | |
379 | ||
c4342ff9 | 380 | static struct irq_chip tsi108_pci_irq = { |
2b9d7467 | 381 | .typename = "tsi108_PCI_int", |
c4342ff9 | 382 | .mask = tsi108_pci_irq_disable, |
2b9d7467 ZR |
383 | .ack = tsi108_pci_irq_ack, |
384 | .end = tsi108_pci_irq_end, | |
c4342ff9 | 385 | .unmask = tsi108_pci_irq_enable, |
2b9d7467 ZR |
386 | }; |
387 | ||
5873c9bd ZR |
388 | static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct, |
389 | u32 *intspec, unsigned int intsize, | |
390 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
391 | { | |
392 | *out_hwirq = intspec[0]; | |
393 | *out_flags = IRQ_TYPE_LEVEL_HIGH; | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static int pci_irq_host_map(struct irq_host *h, unsigned int virq, | |
398 | irq_hw_number_t hw) | |
399 | { unsigned int irq; | |
400 | DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw); | |
401 | if ((virq >= 1) && (virq <= 4)){ | |
402 | irq = virq + IRQ_PCI_INTAD_BASE - 1; | |
403 | get_irq_desc(irq)->status |= IRQ_LEVEL; | |
404 | set_irq_chip(irq, &tsi108_pci_irq); | |
405 | } | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static int pci_irq_host_match(struct irq_host *h, struct device_node *node) | |
410 | { | |
411 | return pci_irq_node == node; | |
412 | } | |
413 | ||
414 | static struct irq_host_ops pci_irq_host_ops = { | |
415 | .match = pci_irq_host_match, | |
416 | .map = pci_irq_host_map, | |
417 | .xlate = pci_irq_host_xlate, | |
418 | }; | |
419 | ||
2b9d7467 ZR |
420 | /* |
421 | * Exported functions | |
422 | */ | |
423 | ||
424 | /* | |
425 | * The Tsi108 PCI interrupts initialization routine. | |
426 | * | |
427 | * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block | |
428 | * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the | |
429 | * PCI block has to be treated as a cascaded interrupt controller connected | |
430 | * to the MPIC. | |
431 | */ | |
432 | ||
5873c9bd | 433 | void __init tsi108_pci_int_init(struct device_node *node) |
2b9d7467 | 434 | { |
2b9d7467 ZR |
435 | DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); |
436 | ||
5873c9bd ZR |
437 | pci_irq_node = of_node_get(node); |
438 | pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0); | |
439 | if (pci_irq_host == NULL) { | |
440 | printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n"); | |
441 | return; | |
2b9d7467 ZR |
442 | } |
443 | ||
444 | init_pci_source(); | |
445 | } | |
446 | ||
35a84c2f | 447 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) |
2b9d7467 | 448 | { |
c4342ff9 ZR |
449 | unsigned int cascade_irq = get_pci_source(); |
450 | if (cascade_irq != NO_IRQ) | |
49f19ce4 | 451 | generic_handle_irq(cascade_irq); |
c4342ff9 | 452 | desc->chip->eoi(irq); |
2b9d7467 | 453 | } |