[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / sysdev / tsi108_pci.c

/*
 * Common routines for Tundra Semiconductor TSI108 host bridge.
 *
 * 2004-2005 (c) Tundra Semiconductor Corp.
 * Author: Alex Bounine (alexandreb@tundra.com)
 * Author: Roy Zang (tie-fei.zang@freescale.com)
 * 	   Add pci interrupt router host
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/tsi108.h>
#include <asm/tsi108_pci.h>
#include <asm/tsi108_irq.h>
#include <asm/prom.h>

#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define tsi_mk_config_addr(bus, devfunc, offset) \
	((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)

u32 tsi108_pci_cfg_base;
u32 tsi108_csr_vir_base;
static struct device_node *pci_irq_node;
static struct irq_host *pci_irq_host;

extern u32 get_vir_csrbase(void);
extern u32 tsi108_read_reg(u32 reg_offset);
extern void tsi108_write_reg(u32 reg_offset, u32 val);

int
tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
			   int offset, int len, u32 val)
{
	volatile unsigned char *cfg_addr;

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(bus->number, devfunc))
			return PCIBIOS_DEVICE_NOT_FOUND;

	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
							devfunc, offset) |
							(offset & 0x03));

#ifdef DEBUG
	printk("PCI CFG write : ");
	printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
	printk("data = 0x%08x\n", val);
#endif

	switch (len) {
	case 1:
		out_8((u8 *) cfg_addr, val);
		break;
	case 2:
		out_le16((u16 *) cfg_addr, val);
		break;
	default:
		out_le32((u32 *) cfg_addr, val);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

void tsi108_clear_pci_error(u32 pci_cfg_base)
{
	u32 err_stat, err_addr, pci_stat;

	/*
	 * Quietly clear PB and PCI error flags set as result
	 * of PCI/X configuration read requests.
	 */

	/* Read PB Error Log Registers */

	err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
	err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);

	if (err_stat & TSI108_PB_ERRCS_ES) {
		/* Clear error flag */
		tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
				 TSI108_PB_ERRCS_ES);

		/* Clear read error reported in PB_ISR */
		tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
				 TSI108_PB_ISR_PBS_RD_ERR);

		/* Clear PCI/X bus cfg errors if applicable */
		if ((err_addr & 0xFF000000) == pci_cfg_base) {
			pci_stat =
			    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
			tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
					 pci_stat);
		}
	}

	return;
}

#define __tsi108_read_pci_config(x, addr, op)		\
	__asm__ __volatile__(				\
		"	"op" %0,0,%1\n"		\
		"1:	eieio\n"			\
		"2:\n"					\
		".section .fixup,\"ax\"\n"		\
		"3:	li %0,-1\n"			\
		"	b 2b\n"				\
		".section __ex_table,\"a\"\n"		\
		"	.align 2\n"			\
		"	.long 1b,3b\n"			\
		".text"					\
		: "=r"(x) : "r"(addr))

int
tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
			  int len, u32 * val)
{
	volatile unsigned char *cfg_addr;
	u32 temp;

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(bus->number, devfn))
			return PCIBIOS_DEVICE_NOT_FOUND;

	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
							devfn,
							offset) | (offset &
								   0x03));

	switch (len) {
	case 1:
		__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
		break;
	case 2:
		__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
		break;
	default:
		__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
		break;
	}

	*val = temp;

#ifdef DEBUG
	if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
		printk("PCI CFG read : ");
		printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
		printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
		printk("data = 0x%x\n", *val);
	}
#endif
	return PCIBIOS_SUCCESSFUL;
}

void tsi108_clear_pci_cfg_error(void)
{
	tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
}

static struct pci_ops tsi108_direct_pci_ops = {
	tsi108_direct_read_config,
	tsi108_direct_write_config
};

int __init tsi108_setup_pci(struct device_node *dev)
{
	int len;
	struct pci_controller *hose;
	struct resource rsrc;
	const int *bus_range;
	int primary = 0, has_address = 0;

	/* PCI Config mapping */
	tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
			TSI108_PCI_CFG_SIZE);
	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
	    tsi108_pci_cfg_base);

	/* Fetch host bridge registers address */
	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);

	/* Get bus range if any */
	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		printk(KERN_WARNING "Can't get bus-range for %s, assume"
		       " bus 0\n", dev->full_name);
	}

	hose = pcibios_alloc_controller();

	if (!hose) {
		printk("PCI Host bridge init failed\n");
		return -ENOMEM;
	}
	hose->arch_data = dev;
	hose->set_cfg_type = 1;

	hose->first_busno = bus_range ? bus_range[0] : 0;
	hose->last_busno = bus_range ? bus_range[1] : 0xff;

	(hose)->ops = &tsi108_direct_pci_ops;

	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
	       "Firmware bus number: %d->%d\n",
	       rsrc.start, hose->first_busno, hose->last_busno);

	/* Interpret the "ranges" property */
	/* This also maps the I/O region and sets isa_io/mem_base */
	pci_process_bridge_OF_ranges(hose, dev, primary);
	return 0;
}

/*
 * Low level utility functions
 */

static void tsi108_pci_int_mask(u_int irq)
{
	u_int irp_cfg;
	int int_line = (irq - IRQ_PCI_INTAD_BASE);

	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	mb();
	irp_cfg |= (1 << int_line);	/* INTx_DIR = output */
	irp_cfg &= ~(3 << (8 + (int_line * 2)));	/* INTx_TYPE = unused */
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	mb();
	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
}

static void tsi108_pci_int_unmask(u_int irq)
{
	u_int irp_cfg;
	int int_line = (irq - IRQ_PCI_INTAD_BASE);

	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	mb();
	irp_cfg &= ~(1 << int_line);
	irp_cfg |= (3 << (8 + (int_line * 2)));
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	mb();
}

static void init_pci_source(void)
{
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
			0x0000ff00);
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
			TSI108_PCI_IRP_ENABLE_P_INT);
	mb();
}

static inline unsigned int get_pci_source(void)
{
	u_int temp = 0;
	int irq = -1;
	int i;
	u_int pci_irp_stat;
	static int mask = 0;

	/* Read PCI/X block interrupt status register */
	pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
	mb();

	if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
		/* Process Interrupt from PCI bus INTA# - INTD# lines */
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET +
				    TSI108_PCI_IRP_INTAD) & 0xf;
		mb();
		for (i = 0; i < 4; i++, mask++) {
			if (temp & (1 << mask % 4)) {
				irq = IRQ_PCI_INTA + mask % 4;
				mask++;
				break;
			}
		}

		/* Disable interrupts from PCI block */
		temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
		tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
				temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
		mb();
		(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
		mb();
	}
#ifdef DEBUG
	else {
		printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
		pci_irp_stat =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
		mb();
		printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
		mb();
		printk("cfg_ctl=0x%08x ", temp);
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
		mb();
		printk("irp_enable=0x%08x\n", temp);
	}
#endif	/* end of DEBUG */

	return irq;
}


/*
 * Linux descriptor level callbacks
 */

static void tsi108_pci_irq_enable(u_int irq)
{
	tsi108_pci_int_unmask(irq);
}

static void tsi108_pci_irq_disable(u_int irq)
{
	tsi108_pci_int_mask(irq);
}

static void tsi108_pci_irq_ack(u_int irq)
{
	tsi108_pci_int_mask(irq);
}

static void tsi108_pci_irq_end(u_int irq)
{
	tsi108_pci_int_unmask(irq);

	/* Enable interrupts from PCI block */
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
			 tsi108_read_reg(TSI108_PCI_OFFSET +
					 TSI108_PCI_IRP_ENABLE) |
			 TSI108_PCI_IRP_ENABLE_P_INT);
	mb();
}

/*
 * Interrupt controller descriptor for cascaded PCI interrupt controller.
 */

static struct irq_chip tsi108_pci_irq = {
	.typename = "tsi108_PCI_int",
	.mask = tsi108_pci_irq_disable,
	.ack = tsi108_pci_irq_ack,
	.end = tsi108_pci_irq_end,
	.unmask = tsi108_pci_irq_enable,
};

static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
			    u32 *intspec, unsigned int intsize,
			    irq_hw_number_t *out_hwirq, unsigned int *out_flags)
{
	*out_hwirq = intspec[0];
	*out_flags = IRQ_TYPE_LEVEL_HIGH;
	return 0;
}

static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
			  irq_hw_number_t hw)
{	unsigned int irq;
	DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw);
	if ((virq >= 1) && (virq <= 4)){
		irq = virq + IRQ_PCI_INTAD_BASE - 1;
		get_irq_desc(irq)->status |= IRQ_LEVEL;
		set_irq_chip(irq, &tsi108_pci_irq);
	}
	return 0;
}

static int pci_irq_host_match(struct irq_host *h, struct device_node *node)
{
	return pci_irq_node == node;
}

static struct irq_host_ops pci_irq_host_ops = {
	.match = pci_irq_host_match,
	.map = pci_irq_host_map,
	.xlate = pci_irq_host_xlate,
};

/*
 * Exported functions
 */

/*
 * The Tsi108 PCI interrupts initialization routine.
 *
 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
 * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
 * PCI block has to be treated as a cascaded interrupt controller connected
 * to the MPIC.
 */

void __init tsi108_pci_int_init(struct device_node *node)
{
	DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");

	pci_irq_node = of_node_get(node);
	pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0);
	if (pci_irq_host == NULL) {
		printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n");
		return;
	}

	init_pci_source();
}

void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
{
	unsigned int cascade_irq = get_pci_source();
	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);
	desc->chip->eoi(irq);
}
Commit	Line	Data
2b9d7467 ZR	1	/*
	2	* Common routines for Tundra Semiconductor TSI108 host bridge.
	3	*
	4	* 2004-2005 (c) Tundra Semiconductor Corp.
	5	* Author: Alex Bounine (alexandreb@tundra.com)
5873c9bd ZR	6	* Author: Roy Zang (tie-fei.zang@freescale.com)
5873c9bd ZR	7	* Add pci interrupt router host
2b9d7467 ZR	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the Free
	11	* Software Foundation; either version 2 of the License, or (at your option)
	12	* any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program; if not, write to the Free Software Foundation, Inc., 59
	21	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/init.h>
	26	#include <linux/pci.h>
	27	#include <linux/slab.h>
	28	#include <linux/irq.h>
	29	#include <linux/interrupt.h>
	30
2b9d7467 ZR	31	#include <asm/byteorder.h>
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34	#include <asm/uaccess.h>
	35	#include <asm/machdep.h>
	36	#include <asm/pci-bridge.h>
	37	#include <asm/tsi108.h>
08390db0	38	#include <asm/tsi108_pci.h>
2b9d7467 ZR	39	#include <asm/tsi108_irq.h>
	40	#include <asm/prom.h>
	41
	42	#undef DEBUG
	43	#ifdef DEBUG
	44	#define DBG(x...) printk(x)
	45	#else
	46	#define DBG(x...)
	47	#endif
	48
	49	#define tsi_mk_config_addr(bus, devfunc, offset) \
	50	((((bus)<<16) \| ((devfunc)<<8) \| (offset & 0xfc)) + tsi108_pci_cfg_base)
	51
	52	u32 tsi108_pci_cfg_base;
	53	u32 tsi108_csr_vir_base;
5873c9bd ZR	54	static struct device_node *pci_irq_node;
5873c9bd ZR	55	static struct irq_host *pci_irq_host;
2b9d7467 ZR	56
	57	extern u32 get_vir_csrbase(void);
	58	extern u32 tsi108_read_reg(u32 reg_offset);
	59	extern void tsi108_write_reg(u32 reg_offset, u32 val);
	60
	61	int
	62	tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
	63	int offset, int len, u32 val)
	64	{
	65	volatile unsigned char *cfg_addr;
	66
	67	if (ppc_md.pci_exclude_device)
	68	if (ppc_md.pci_exclude_device(bus->number, devfunc))
	69	return PCIBIOS_DEVICE_NOT_FOUND;
	70
	71	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
	72	devfunc, offset) \|
	73	(offset & 0x03));
	74
	75	#ifdef DEBUG
	76	printk("PCI CFG write : ");
	77	printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
	78	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
	79	printk("data = 0x%08x\n", val);
	80	#endif
	81
	82	switch (len) {
	83	case 1:
	84	out_8((u8 *) cfg_addr, val);
	85	break;
	86	case 2:
	87	out_le16((u16 *) cfg_addr, val);
	88	break;
	89	default:
	90	out_le32((u32 *) cfg_addr, val);
	91	break;
	92	}
	93
	94	return PCIBIOS_SUCCESSFUL;
	95	}
	96
	97	void tsi108_clear_pci_error(u32 pci_cfg_base)
	98	{
	99	u32 err_stat, err_addr, pci_stat;
	100
	101	/*
	102	* Quietly clear PB and PCI error flags set as result
	103	* of PCI/X configuration read requests.
	104	*/
	105
	106	/* Read PB Error Log Registers */
	107
	108	err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
	109	err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
	110
	111	if (err_stat & TSI108_PB_ERRCS_ES) {
	112	/* Clear error flag */
	113	tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
	114	TSI108_PB_ERRCS_ES);
	115
	116	/* Clear read error reported in PB_ISR */
	117	tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
	118	TSI108_PB_ISR_PBS_RD_ERR);
	119
120	/* Clear PCI/X bus cfg errors if applicable */
121	if ((err_addr & 0xFF000000) == pci_cfg_base) {
122	pci_stat =
123	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
124	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
125	pci_stat);
126	}
127	}
128
129	return;
130	}
131
132	#define __tsi108_read_pci_config(x, addr, op) \
133	__asm__ __volatile__( \
134	" "op" %0,0,%1\n" \
135	"1: eieio\n" \
136	"2:\n" \
137	".section .fixup,\"ax\"\n" \
138	"3: li %0,-1\n" \
139	" b 2b\n" \
140	".section __ex_table,\"a\"\n" \
141	" .align 2\n" \
142	" .long 1b,3b\n" \
143	".text" \
144	: "=r"(x) : "r"(addr))
145
146	int
147	tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
148	int len, u32 * val)
149	{
150	volatile unsigned char *cfg_addr;
151	u32 temp;
152
153	if (ppc_md.pci_exclude_device)
154	if (ppc_md.pci_exclude_device(bus->number, devfn))
155	return PCIBIOS_DEVICE_NOT_FOUND;
156
157	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
158	devfn,
159	offset) \| (offset &
160	0x03));
161
162	switch (len) {
163	case 1:
164	__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
165	break;
166	case 2:
167	__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
168	break;
169	default:
170	__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
171	break;
172	}
173
174	*val = temp;
175
176	#ifdef DEBUG
177	if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
178	printk("PCI CFG read : ");
179	printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
180	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
181	printk("data = 0x%x\n", *val);
182	}
183	#endif
184	return PCIBIOS_SUCCESSFUL;
185	}
186
187	void tsi108_clear_pci_cfg_error(void)
188	{
189	tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
190	}
191
192	static struct pci_ops tsi108_direct_pci_ops = {
193	tsi108_direct_read_config,
194	tsi108_direct_write_config
195	};
196
197	int __init tsi108_setup_pci(struct device_node *dev)
198	{
199	int len;
200	struct pci_controller *hose;
201	struct resource rsrc;
88c80594	202	const int *bus_range;
2b9d7467 ZR	203	int primary = 0, has_address = 0;
	204
	205	/* PCI Config mapping */
	206	tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
	207	TSI108_PCI_CFG_SIZE);
	208	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
	209	tsi108_pci_cfg_base);
	210
	211	/* Fetch host bridge registers address */
	212	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
	213
	214	/* Get bus range if any */
e2eb6392	215	bus_range = of_get_property(dev, "bus-range", &len);
2b9d7467 ZR	216	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	217	printk(KERN_WARNING "Can't get bus-range for %s, assume"
	218	" bus 0\n", dev->full_name);
	219	}
	220
	221	hose = pcibios_alloc_controller();
	222
	223	if (!hose) {
	224	printk("PCI Host bridge init failed\n");
	225	return -ENOMEM;
	226	}
	227	hose->arch_data = dev;
	228	hose->set_cfg_type = 1;
	229
	230	hose->first_busno = bus_range ? bus_range[0] : 0;
	231	hose->last_busno = bus_range ? bus_range[1] : 0xff;
	232
	233	(hose)->ops = &tsi108_direct_pci_ops;
	234
c4342ff9	235	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
2b9d7467 ZR	236	"Firmware bus number: %d->%d\n",
	237	rsrc.start, hose->first_busno, hose->last_busno);
	238
	239	/* Interpret the "ranges" property */
	240	/* This also maps the I/O region and sets isa_io/mem_base */
	241	pci_process_bridge_OF_ranges(hose, dev, primary);
	242	return 0;
	243	}
	244
	245	/*
	246	* Low level utility functions
	247	*/
	248
	249	static void tsi108_pci_int_mask(u_int irq)
	250	{
	251	u_int irp_cfg;
	252	int int_line = (irq - IRQ_PCI_INTAD_BASE);
	253
	254	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	255	mb();
	256	irp_cfg \|= (1 << int_line); /* INTx_DIR = output */
	257	irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
	258	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	259	mb();
	260	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	261	}
	262
	263	static void tsi108_pci_int_unmask(u_int irq)
	264	{
	265	u_int irp_cfg;
	266	int int_line = (irq - IRQ_PCI_INTAD_BASE);
	267
	268	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	269	mb();
	270	irp_cfg &= ~(1 << int_line);
	271	irp_cfg \|= (3 << (8 + (int_line * 2)));
	272	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	273	mb();
	274	}
	275
	276	static void init_pci_source(void)
	277	{
	278	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
	279	0x0000ff00);
	280	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
	281	TSI108_PCI_IRP_ENABLE_P_INT);
	282	mb();
	283	}
	284
c4342ff9	285	static inline unsigned int get_pci_source(void)
2b9d7467 ZR	286	{
	287	u_int temp = 0;
	288	int irq = -1;
	289	int i;
	290	u_int pci_irp_stat;
	291	static int mask = 0;
	292
	293	/* Read PCI/X block interrupt status register */
	294	pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
	295	mb();
	296
	297	if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
	298	/* Process Interrupt from PCI bus INTA# - INTD# lines */
	299	temp =
	300	tsi108_read_reg(TSI108_PCI_OFFSET +
	301	TSI108_PCI_IRP_INTAD) & 0xf;
	302	mb();
	303	for (i = 0; i < 4; i++, mask++) {
	304	if (temp & (1 << mask % 4)) {
	305	irq = IRQ_PCI_INTA + mask % 4;
	306	mask++;
	307	break;
	308	}
	309	}
	310
	311	/* Disable interrupts from PCI block */
	312	temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
	313	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
	314	temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
	315	mb();
	316	(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
	317	mb();
	318	}
	319	#ifdef DEBUG
	320	else {
	321	printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
	322	pci_irp_stat =
	323	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
	324	temp =
	325	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
	326	mb();
	327	printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
	328	temp =
	329	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	330	mb();
	331	printk("cfg_ctl=0x%08x ", temp);
	332	temp =
	333	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
	334	mb();
	335	printk("irp_enable=0x%08x\n", temp);
	336	}
	337	#endif /* end of DEBUG */
	338
	339	return irq;
	340	}
	341
	342
	343	/*
	344	* Linux descriptor level callbacks
	345	*/
	346
	347	static void tsi108_pci_irq_enable(u_int irq)
	348	{
	349	tsi108_pci_int_unmask(irq);
350	}
351
352	static void tsi108_pci_irq_disable(u_int irq)
353	{
354	tsi108_pci_int_mask(irq);
355	}
356
357	static void tsi108_pci_irq_ack(u_int irq)
358	{
359	tsi108_pci_int_mask(irq);
360	}
361
362	static void tsi108_pci_irq_end(u_int irq)
363	{
364	tsi108_pci_int_unmask(irq);
365
366	/* Enable interrupts from PCI block */
367	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
368	tsi108_read_reg(TSI108_PCI_OFFSET +
369	TSI108_PCI_IRP_ENABLE) \|
370	TSI108_PCI_IRP_ENABLE_P_INT);
371	mb();
372	}
373
374	/*
375	* Interrupt controller descriptor for cascaded PCI interrupt controller.
376	*/
377
c4342ff9	378	static struct irq_chip tsi108_pci_irq = {
2b9d7467	379	.typename = "tsi108_PCI_int",
c4342ff9	380	.mask = tsi108_pci_irq_disable,
2b9d7467 ZR	381	.ack = tsi108_pci_irq_ack,
2b9d7467 ZR	382	.end = tsi108_pci_irq_end,
c4342ff9	383	.unmask = tsi108_pci_irq_enable,
2b9d7467 ZR	384	};
2b9d7467 ZR	385
5873c9bd ZR	386	static int pci_irq_host_xlate(struct irq_host h, struct device_node ct,
	387	u32 *intspec, unsigned int intsize,
	388	irq_hw_number_t out_hwirq, unsigned int out_flags)
	389	{
	390	*out_hwirq = intspec[0];
	391	*out_flags = IRQ_TYPE_LEVEL_HIGH;
	392	return 0;
	393	}
	394
	395	static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
	396	irq_hw_number_t hw)
	397	{ unsigned int irq;
	398	DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw);
	399	if ((virq >= 1) && (virq <= 4)){
	400	irq = virq + IRQ_PCI_INTAD_BASE - 1;
	401	get_irq_desc(irq)->status \|= IRQ_LEVEL;
	402	set_irq_chip(irq, &tsi108_pci_irq);
	403	}
	404	return 0;
	405	}
	406
	407	static int pci_irq_host_match(struct irq_host h, struct device_node node)
	408	{
	409	return pci_irq_node == node;
	410	}
	411
	412	static struct irq_host_ops pci_irq_host_ops = {
	413	.match = pci_irq_host_match,
	414	.map = pci_irq_host_map,
	415	.xlate = pci_irq_host_xlate,
	416	};
	417
2b9d7467 ZR	418	/*
	419	* Exported functions
	420	*/
	421
	422	/*
	423	* The Tsi108 PCI interrupts initialization routine.
	424	*
	425	* The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
	426	* to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
	427	* PCI block has to be treated as a cascaded interrupt controller connected
	428	* to the MPIC.
	429	*/
	430
5873c9bd	431	void __init tsi108_pci_int_init(struct device_node *node)
2b9d7467	432	{
2b9d7467 ZR	433	DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
2b9d7467 ZR	434
5873c9bd ZR	435	pci_irq_node = of_node_get(node);
	436	pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0);
	437	if (pci_irq_host == NULL) {
	438	printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n");
	439	return;
2b9d7467 ZR	440	}
	441
	442	init_pci_source();
	443	}
	444
35a84c2f	445	void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
2b9d7467	446	{
c4342ff9 ZR	447	unsigned int cascade_irq = get_pci_source();
c4342ff9 ZR	448	if (cascade_irq != NO_IRQ)
49f19ce4	449	generic_handle_irq(cascade_irq);
c4342ff9	450	desc->chip->eoi(irq);
2b9d7467	451	}