[mirror_ubuntu-kernels.git] / arch / powerpc / sysdev / xive / xive-internal.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2016,2017 IBM Corporation.
 */
#ifndef __XIVE_INTERNAL_H
#define __XIVE_INTERNAL_H

/* Each CPU carry one of these with various per-CPU state */
struct xive_cpu {
#ifdef CONFIG_SMP
	/* HW irq number and data of IPI */
	u32 hw_ipi;
	struct xive_irq_data ipi_data;
#endif /* CONFIG_SMP */

	int chip_id;

	/* Queue datas. Only one is populated */
#define XIVE_MAX_QUEUES	8
	struct xive_q queue[XIVE_MAX_QUEUES];

	/*
	 * Pending mask. Each bit corresponds to a priority that
	 * potentially has pending interrupts.
	 */
	u8 pending_prio;

	/* Cache of HW CPPR */
	u8 cppr;
};

/* Backend ops */
struct xive_ops {
	int	(*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data);
	int 	(*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
	int	(*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
	void	(*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
	void	(*setup_cpu)(unsigned int cpu, struct xive_cpu *xc);
	void	(*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc);
	bool	(*match)(struct device_node *np);
	void	(*shutdown)(void);

	void	(*update_pending)(struct xive_cpu *xc);
	void	(*eoi)(u32 hw_irq);
	void	(*sync_source)(u32 hw_irq);
	u64	(*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
#ifdef CONFIG_SMP
	int	(*get_ipi)(unsigned int cpu, struct xive_cpu *xc);
	void	(*put_ipi)(unsigned int cpu, struct xive_cpu *xc);
#endif
	const char *name;
};

bool xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
		    u8 max_prio);
__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift);

static inline u32 xive_alloc_order(u32 queue_shift)
{
	return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
}

extern bool xive_cmdline_disabled;

#endif /*  __XIVE_INTERNAL_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
243e2511 BH	2	/*
243e2511 BH	3	* Copyright 2016,2017 IBM Corporation.
243e2511 BH	4	*/
	5	#ifndef __XIVE_INTERNAL_H
	6	#define __XIVE_INTERNAL_H
	7
	8	/* Each CPU carry one of these with various per-CPU state */
	9	struct xive_cpu {
	10	#ifdef CONFIG_SMP
	11	/* HW irq number and data of IPI */
	12	u32 hw_ipi;
	13	struct xive_irq_data ipi_data;
	14	#endif /* CONFIG_SMP */
	15
	16	int chip_id;
	17
	18	/* Queue datas. Only one is populated */
	19	#define XIVE_MAX_QUEUES 8
	20	struct xive_q queue[XIVE_MAX_QUEUES];
	21
	22	/*
	23	* Pending mask. Each bit corresponds to a priority that
	24	* potentially has pending interrupts.
	25	*/
	26	u8 pending_prio;
	27
	28	/* Cache of HW CPPR */
	29	u8 cppr;
	30	};
	31
	32	/* Backend ops */
	33	struct xive_ops {
	34	int (populate_irq_data)(u32 hw_irq, struct xive_irq_data data);
	35	int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
	36	int (setup_queue)(unsigned int cpu, struct xive_cpu xc, u8 prio);
	37	void (cleanup_queue)(unsigned int cpu, struct xive_cpu xc, u8 prio);
	38	void (setup_cpu)(unsigned int cpu, struct xive_cpu xc);
	39	void (teardown_cpu)(unsigned int cpu, struct xive_cpu xc);
	40	bool (match)(struct device_node np);
	41	void (*shutdown)(void);
	42
	43	void (update_pending)(struct xive_cpu xc);
	44	void (*eoi)(u32 hw_irq);
	45	void (*sync_source)(u32 hw_irq);
bed81ee1	46	u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
243e2511 BH	47	#ifdef CONFIG_SMP
	48	int (get_ipi)(unsigned int cpu, struct xive_cpu xc);
	49	void (put_ipi)(unsigned int cpu, struct xive_cpu xc);
	50	#endif
	51	const char *name;
	52	};
	53
	54	bool xive_core_init(const struct xive_ops ops, void __iomem area, u32 offset,
	55	u8 max_prio);
994ea2f4 CLG	56	__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift);
	57
	58	static inline u32 xive_alloc_order(u32 queue_shift)
	59	{
	60	return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
	61	}
243e2511 BH	62
	63	extern bool xive_cmdline_disabled;
	64
	65	#endif /* __XIVE_INTERNAL_H */