]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/powerpc/xmon/ppc-opc.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'ext4_for_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...
[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / xmon / ppc-opc.c
CommitLineData
1da177e4 1/* ppc-opc.c -- PowerPC opcode list
08d96e0b 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
1da177e4
LT		 3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
897f112b
ME		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
1da177e4 21
66768eb2 22#include <linux/stddef.h>
3839a594 23#include <linux/kernel.h>
50af5ead 24#include <linux/bug.h>
1da177e4
LT		 25#include "nonstdio.h"
26#include "ppc.h"
27
28#define ATTRIBUTE_UNUSED
29#define _(x) x
30
31/* This file holds the PowerPC opcode table. The opcode table
32 includes almost all of the extended instruction mnemonics. This
33 permits the disassembler to use them, and simplifies the assembler
34 logic, at the cost of increasing the table size. The table is
35 strictly constant data, so the compiler should be able to put it in
36 the .text section.
37
38 This file also holds the operand table. All knowledge about
39 inserting operands into instructions and vice-versa is kept in this
40 file. */
41\f
42/* Local insertion and extraction functions. */
43
08d96e0b
BS		 44static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_arx (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_ary (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bat (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bba (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_bdm (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_bdp (unsigned long, ppc_cpu_t, int *);
56static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
57static long extract_bo (unsigned long, ppc_cpu_t, int *);
58static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
59static long extract_boe (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
61static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
62static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
63static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
64static long extract_dxd (unsigned long, ppc_cpu_t, int *);
65static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
66static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
67static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
68static long extract_fxm (unsigned long, ppc_cpu_t, int *);
69static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
70static long extract_li20 (unsigned long, ppc_cpu_t, int *);
71static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
72static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_mbe (unsigned long, ppc_cpu_t, int *);
74static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
76static long extract_nb (unsigned long, ppc_cpu_t, int *);
77static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
78static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_nsi (unsigned long, ppc_cpu_t, int *);
80static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
81static long extract_oimm (unsigned long, ppc_cpu_t, int *);
82static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
83static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
85static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
86static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
87static long extract_rbs (unsigned long, ppc_cpu_t, int *);
88static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
89static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
90static long extract_rx (unsigned long, ppc_cpu_t, int *);
91static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
92static long extract_ry (unsigned long, ppc_cpu_t, int *);
93static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
94static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
95static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
96static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
97static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
98static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
99static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
100static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
101static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
102static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
103static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
104static long extract_spr (unsigned long, ppc_cpu_t, int *);
105static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
106static long extract_sprg (unsigned long, ppc_cpu_t, int *);
107static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
108static long extract_tbr (unsigned long, ppc_cpu_t, int *);
109static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
110static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
111static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
112static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
113static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
114static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
115static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
116static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
117static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
118static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
119static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
120static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
121static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
122static long extract_dm (unsigned long, ppc_cpu_t, int *);
123static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
124static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
125static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
126static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
127static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
128static long extract_vleui (unsigned long, ppc_cpu_t, int *);
129static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
130static long extract_vleil (unsigned long, ppc_cpu_t, int *);
1da177e4
LT		 131\f
132/* The operands table.
133
cc7639ce 134 The fields are bitm, shift, insert, extract, flags.
1da177e4
LT		 135
136 We used to put parens around the various additions, like the one
137 for BA just below. However, that caused trouble with feeble
138 compilers with a limit on depth of a parenthesized expression, like
139 (reportedly) the compiler in Microsoft Developer Studio 5. So we
140 omit the parens, since the macros are never used in a context where
141 the addition will be ambiguous. */
142
143const struct powerpc_operand powerpc_operands[] =
144{
145 /* The zero index is used to indicate the end of the list of
146 operands. */
147#define UNUSED 0
66768eb2 148 { 0, 0, NULL, NULL, 0 },
1da177e4
LT		 149
150 /* The BA field in an XL form instruction. */
151#define BA UNUSED + 1
cc7639ce
BS		 152 /* The BI field in a B form or XL form instruction. */
153#define BI BA
154#define BI_MASK (0x1f << 16)
08d96e0b 155 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
1da177e4
LT		 156
157 /* The BA field in an XL form instruction when it must be the same
158 as the BT field in the same instruction. */
159#define BAT BA + 1
cc7639ce 160 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
1da177e4
LT		 161
162 /* The BB field in an XL form instruction. */
163#define BB BAT + 1
164#define BB_MASK (0x1f << 11)
08d96e0b 165 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
1da177e4
LT		 166
167 /* The BB field in an XL form instruction when it must be the same
168 as the BA field in the same instruction. */
169#define BBA BB + 1
08d96e0b
BS		 170 /* The VB field in a VX form instruction when it must be the same
171 as the VA field in the same instruction. */
172#define VBA BBA
cc7639ce 173 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
1da177e4
LT		 174
175 /* The BD field in a B form instruction. The lower two bits are
176 forced to zero. */
177#define BD BBA + 1
cc7639ce 178 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1da177e4
LT		 179
180 /* The BD field in a B form instruction when absolute addressing is
181 used. */
182#define BDA BD + 1
cc7639ce 183 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1da177e4
LT		 184
185 /* The BD field in a B form instruction when the - modifier is used.
186 This sets the y bit of the BO field appropriately. */
187#define BDM BDA + 1
cc7639ce 188 { 0xfffc, 0, insert_bdm, extract_bdm,
08d96e0b 189 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1da177e4
LT		 190
191 /* The BD field in a B form instruction when the - modifier is used
192 and absolute address is used. */
193#define BDMA BDM + 1
cc7639ce 194 { 0xfffc, 0, insert_bdm, extract_bdm,
08d96e0b 195 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1da177e4
LT		 196
197 /* The BD field in a B form instruction when the + modifier is used.
198 This sets the y bit of the BO field appropriately. */
199#define BDP BDMA + 1
cc7639ce 200 { 0xfffc, 0, insert_bdp, extract_bdp,
08d96e0b 201 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1da177e4
LT		 202
203 /* The BD field in a B form instruction when the + modifier is used
204 and absolute addressing is used. */
205#define BDPA BDP + 1
cc7639ce 206 { 0xfffc, 0, insert_bdp, extract_bdp,
08d96e0b 207 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1da177e4
LT		 208
209 /* The BF field in an X or XL form instruction. */
210#define BF BDPA + 1
cc7639ce
BS		 211 /* The CRFD field in an X form instruction. */
212#define CRFD BF
08d96e0b
BS		 213 /* The CRD field in an XL form instruction. */
214#define CRD BF
215 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
cc7639ce
BS		 216
217 /* The BF field in an X or XL form instruction. */
218#define BFF BF + 1
219 { 0x7, 23, NULL, NULL, 0 },
1da177e4
LT		 220
221 /* An optional BF field. This is used for comparison instructions,
222 in which an omitted BF field is taken as zero. */
cc7639ce 223#define OBF BFF + 1
08d96e0b 224 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
1da177e4
LT		 225
226 /* The BFA field in an X or XL form instruction. */
227#define BFA OBF + 1
08d96e0b 228 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
1da177e4
LT		 229
230 /* The BO field in a B form instruction. Certain values are
231 illegal. */
cc7639ce 232#define BO BFA + 1
1da177e4 233#define BO_MASK (0x1f << 21)
cc7639ce 234 { 0x1f, 21, insert_bo, extract_bo, 0 },
1da177e4
LT		 235
236 /* The BO field in a B form instruction when the + or - modifier is
237 used. This is like the BO field, but it must be even. */
238#define BOE BO + 1
cc7639ce 239 { 0x1e, 21, insert_boe, extract_boe, 0 },
1da177e4 240
08d96e0b
BS		 241 /* The RM field in an X form instruction. */
242#define RM BOE + 1
243 { 0x3, 11, NULL, NULL, 0 },
244
245#define BH RM + 1
cc7639ce 246 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
897f112b 247
1da177e4 248 /* The BT field in an X or XL form instruction. */
897f112b 249#define BT BH + 1
08d96e0b
BS		 250 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
251
252 /* The BI16 field in a BD8 form instruction. */
253#define BI16 BT + 1
254 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
255
256 /* The BI32 field in a BD15 form instruction. */
257#define BI32 BI16 + 1
258 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
259
260 /* The BO32 field in a BD15 form instruction. */
261#define BO32 BI32 + 1
262 { 0x3, 20, NULL, NULL, 0 },
263
264 /* The B8 field in a BD8 form instruction. */
265#define B8 BO32 + 1
266 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
267
268 /* The B15 field in a BD15 form instruction. The lowest bit is
269 forced to zero. */
270#define B15 B8 + 1
271 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
272
273 /* The B24 field in a BD24 form instruction. The lowest bit is
274 forced to zero. */
275#define B24 B15 + 1
276 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1da177e4
LT		 277
278 /* The condition register number portion of the BI field in a B form
279 or XL form instruction. This is used for the extended
280 conditional branch mnemonics, which set the lower two bits of the
281 BI field. This field is optional. */
08d96e0b
BS		 282#define CR B24 + 1
283 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
1da177e4
LT		 284
285 /* The CRB field in an X form instruction. */
286#define CRB CR + 1
cc7639ce
BS		 287 /* The MB field in an M form instruction. */
288#define MB CRB
289#define MB_MASK (0x1f << 6)
290 { 0x1f, 6, NULL, NULL, 0 },
1da177e4 291
08d96e0b
BS		 292 /* The CRD32 field in an XL form instruction. */
293#define CRD32 CRB + 1
294 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
1da177e4
LT		 295
296 /* The CRFS field in an X form instruction. */
08d96e0b
BS		 297#define CRFS CRD32 + 1
298 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
299
300#define CRS CRFS + 1
301 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
1da177e4
LT		 302
303 /* The CT field in an X form instruction. */
08d96e0b 304#define CT CRS + 1
cc7639ce
BS		 305 /* The MO field in an mbar instruction. */
306#define MO CT
307 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
1da177e4
LT		 308
309 /* The D field in a D form instruction. This is a displacement off
310 a register, and implies that the next operand is a register in
311 parentheses. */
312#define D CT + 1
cc7639ce 313 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
1da177e4 314
08d96e0b
BS		 315 /* The D8 field in a D form instruction. This is a displacement off
316 a register, and implies that the next operand is a register in
317 parentheses. */
318#define D8 D + 1
319 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
1da177e4 320
08d96e0b
BS		 321 /* The DCMX field in an X form instruction. */
322#define DCMX D8 + 1
323 { 0x7f, 16, NULL, NULL, 0 },
1da177e4 324
08d96e0b
BS		 325 /* The split DCMX field in an X form instruction. */
326#define DCMXS DCMX + 1
327 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
1da177e4
LT		 328
329 /* The DQ field in a DQ form instruction. This is like D, but the
330 lower four bits are forced to zero. */
08d96e0b 331#define DQ DCMXS + 1
cc7639ce
BS		 332 { 0xfff0, 0, NULL, NULL,
333 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
1da177e4
LT		 334
335 /* The DS field in a DS form instruction. This is like D, but the
336 lower two bits are forced to zero. */
337#define DS DQ + 1
cc7639ce
BS		 338 { 0xfffc, 0, NULL, NULL,
339 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
1da177e4 340
08d96e0b
BS		 341 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
342 unsigned imediate */
343#define DUIS DS + 1
344#define BHRBE DUIS
345 { 0x3ff, 11, NULL, NULL, 0 },
346
347 /* The split D field in a DX form instruction. */
348#define DXD DUIS + 1
349 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
350 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
351
352 /* The split ND field in a DX form instruction.
353 This is the same as the DX field, only negated. */
354#define NDXD DXD + 1
355 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
356 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
1da177e4
LT		 357
358 /* The E field in a wrteei instruction. */
08d96e0b
BS		 359 /* And the W bit in the pair singles instructions. */
360 /* And the ST field in a VX form instruction. */
361#define E NDXD + 1
362#define PSW E
363#define ST E
cc7639ce 364 { 0x1, 15, NULL, NULL, 0 },
1da177e4
LT		 365
366 /* The FL1 field in a POWER SC form instruction. */
367#define FL1 E + 1
cc7639ce
BS		 368 /* The U field in an X form instruction. */
369#define U FL1
370 { 0xf, 12, NULL, NULL, 0 },
1da177e4
LT		 371
372 /* The FL2 field in a POWER SC form instruction. */
373#define FL2 FL1 + 1
cc7639ce 374 { 0x7, 2, NULL, NULL, 0 },
1da177e4
LT		 375
376 /* The FLM field in an XFL form instruction. */
377#define FLM FL2 + 1
cc7639ce 378 { 0xff, 17, NULL, NULL, 0 },
1da177e4
LT		 379
380 /* The FRA field in an X or A form instruction. */
381#define FRA FLM + 1
382#define FRA_MASK (0x1f << 16)
cc7639ce 383 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
1da177e4 384
08d96e0b
BS		 385 /* The FRAp field of DFP instructions. */
386#define FRAp FRA + 1
387 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
1da177e4
LT		 388
389 /* The FRB field in an X or A form instruction. */
08d96e0b 390#define FRB FRAp + 1
1da177e4 391#define FRB_MASK (0x1f << 11)
cc7639ce 392 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
1da177e4 393
08d96e0b
BS		 394 /* The FRBp field of DFP instructions. */
395#define FRBp FRB + 1
396 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
1da177e4
LT		 397
398 /* The FRC field in an A form instruction. */
08d96e0b 399#define FRC FRBp + 1
1da177e4 400#define FRC_MASK (0x1f << 6)
cc7639ce 401 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
1da177e4
LT		 402
403 /* The FRS field in an X form instruction or the FRT field in a D, X
404 or A form instruction. */
405#define FRS FRC + 1
406#define FRT FRS
cc7639ce 407 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
1da177e4 408
08d96e0b
BS		 409 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
410 instructions. */
411#define FRSp FRS + 1
412#define FRTp FRSp
413 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
1da177e4
LT		 414
415 /* The FXM field in an XFX instruction. */
08d96e0b 416#define FXM FRSp + 1
cc7639ce 417 { 0xff, 12, insert_fxm, extract_fxm, 0 },
1da177e4
LT		 418
419 /* Power4 version for mfcr. */
420#define FXM4 FXM + 1
08d96e0b
BS		 421 { 0xff, 12, insert_fxm, extract_fxm,
422 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
423 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
424 { -1, -1, NULL, NULL, 0},
425
426 /* The IMM20 field in an LI instruction. */
427#define IMM20 FXM4 + 2
428 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
1da177e4
LT		 429
430 /* The L field in a D or X form instruction. */
08d96e0b
BS		 431#define L IMM20 + 1
432 { 0x1, 21, NULL, NULL, 0 },
433
434 /* The optional L field in tlbie and tlbiel instructions. */
435#define LOPT L + 1
436 /* The R field in a HTM X form instruction. */
437#define HTM_R LOPT
cc7639ce 438 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
1da177e4 439
08d96e0b
BS		 440 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
441#define L32OPT LOPT + 1
442 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
443
444 /* The L field in dcbf instruction. */
445#define L2OPT L32OPT + 1
446 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
1da177e4 447
897f112b 448 /* The LEV field in a POWER SVC form instruction. */
08d96e0b 449#define SVC_LEV L2OPT + 1
cc7639ce 450 { 0x7f, 5, NULL, NULL, 0 },
1da177e4 451
897f112b
ME		 452 /* The LEV field in an SC form instruction. */
453#define LEV SVC_LEV + 1
cc7639ce 454 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
897f112b 455
1da177e4
LT		 456 /* The LI field in an I form instruction. The lower two bits are
457 forced to zero. */
458#define LI LEV + 1
cc7639ce 459 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1da177e4
LT		 460
461 /* The LI field in an I form instruction when used as an absolute
462 address. */
463#define LIA LI + 1
cc7639ce 464 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1da177e4 465
08d96e0b 466 /* The LS or WC field in an X (sync or wait) form instruction. */
1da177e4 467#define LS LIA + 1
08d96e0b
BS		 468#define WC LS
469 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
1da177e4
LT		 470
471 /* The ME field in an M form instruction. */
cc7639ce 472#define ME LS + 1
1da177e4 473#define ME_MASK (0x1f << 1)
cc7639ce 474 { 0x1f, 1, NULL, NULL, 0 },
1da177e4
LT		 475
476 /* The MB and ME fields in an M form instruction expressed a single
477 operand which is a bitmask indicating which bits to select. This
478 is a two operand form using PPC_OPERAND_NEXT. See the
479 description in opcode/ppc.h for what this means. */
480#define MBE ME + 1
cc7639ce
BS		 481 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
482 { -1, 0, insert_mbe, extract_mbe, 0 },
1da177e4
LT		 483
484 /* The MB or ME field in an MD or MDS form instruction. The high
485 bit is wrapped to the low end. */
486#define MB6 MBE + 2
487#define ME6 MB6
488#define MB6_MASK (0x3f << 5)
cc7639ce 489 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
1da177e4
LT		 490
491 /* The NB field in an X form instruction. The value 32 is stored as
492 0. */
cc7639ce
BS		 493#define NB MB6 + 1
494 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
1da177e4 495
08d96e0b
BS		 496 /* The NBI field in an lswi instruction, which has special value
497 restrictions. The value 32 is stored as 0. */
498#define NBI NB + 1
499 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
1da177e4
LT		 500
501 /* The NSI field in a D form instruction. This is the same as the
502 SI field, only negated. */
08d96e0b
BS		 503#define NSI NBI + 1
504 { 0xffff, 0, insert_nsi, extract_nsi,
505 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
506
507 /* The NSI field in a D form instruction when we accept a wide range
508 of positive values. */
509#define NSISIGNOPT NSI + 1
cc7639ce 510 { 0xffff, 0, insert_nsi, extract_nsi,
08d96e0b 511 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
1da177e4
LT		 512
513 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
08d96e0b 514#define RA NSISIGNOPT + 1
1da177e4 515#define RA_MASK (0x1f << 16)
cc7639ce 516 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
1da177e4 517
897f112b
ME		 518 /* As above, but 0 in the RA field means zero, not r0. */
519#define RA0 RA + 1
cc7639ce 520 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
897f112b 521
08d96e0b 522 /* The RA field in the DQ form lq or an lswx instruction, which have special
1da177e4 523 value restrictions. */
897f112b 524#define RAQ RA0 + 1
08d96e0b 525#define RAX RAQ
cc7639ce 526 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
1da177e4
LT		 527
528 /* The RA field in a D or X form instruction which is an updating
529 load, which means that the RA field may not be zero and may not
530 equal the RT field. */
531#define RAL RAQ + 1
cc7639ce 532 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
1da177e4
LT		 533
534 /* The RA field in an lmw instruction, which has special value
535 restrictions. */
536#define RAM RAL + 1
cc7639ce 537 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
1da177e4
LT		 538
539 /* The RA field in a D or X form instruction which is an updating
540 store or an updating floating point load, which means that the RA
541 field may not be zero. */
542#define RAS RAM + 1
cc7639ce 543 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
897f112b 544
08d96e0b
BS		 545 /* The RA field of the tlbwe, dccci and iccci instructions,
546 which are optional. */
897f112b 547#define RAOPT RAS + 1
cc7639ce 548 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1da177e4
LT		 549
550 /* The RB field in an X, XO, M, or MDS form instruction. */
897f112b 551#define RB RAOPT + 1
1da177e4 552#define RB_MASK (0x1f << 11)
cc7639ce 553 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
1da177e4
LT		 554
555 /* The RB field in an X form instruction when it must be the same as
556 the RS field in the instruction. This is used for extended
557 mnemonics like mr. */
558#define RBS RB + 1
cc7639ce 559 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
1da177e4 560
08d96e0b
BS		 561 /* The RB field in an lswx instruction, which has special value
562 restrictions. */
563#define RBX RBS + 1
564 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
565
566 /* The RB field of the dccci and iccci instructions, which are optional. */
567#define RBOPT RBX + 1
568 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
569
570 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
571#define RC RBOPT + 1
572 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
1da177e4
LT		 573
574 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
575 instruction or the RT field in a D, DS, X, XFX or XO form
576 instruction. */
08d96e0b 577#define RS RC + 1
1da177e4
LT		 578#define RT RS
579#define RT_MASK (0x1f << 21)
08d96e0b 580#define RD RS
cc7639ce 581 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
1da177e4 582
08d96e0b
BS		 583 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
584 which have special value restrictions. */
1da177e4 585#define RSQ RS + 1
cc7639ce 586#define RTQ RSQ
08d96e0b 587 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
897f112b
ME		 588
589 /* The RS field of the tlbwe instruction, which is optional. */
cc7639ce 590#define RSO RSQ + 1
897f112b 591#define RTO RSO
cc7639ce 592 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1da177e4 593
08d96e0b
BS		 594 /* The RX field of the SE_RR form instruction. */
595#define RX RSO + 1
596 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
597
598 /* The ARX field of the SE_RR form instruction. */
599#define ARX RX + 1
600 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
601
602 /* The RY field of the SE_RR form instruction. */
603#define RY ARX + 1
604#define RZ RY
605 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
606
607 /* The ARY field of the SE_RR form instruction. */
608#define ARY RY + 1
609 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
610
611 /* The SCLSCI8 field in a D form instruction. */
612#define SCLSCI8 ARY + 1
613 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
614
615 /* The SCLSCI8N field in a D form instruction. This is the same as the
616 SCLSCI8 field, only negated. */
617#define SCLSCI8N SCLSCI8 + 1
618 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
619 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
620
621 /* The SD field of the SD4 form instruction. */
622#define SE_SD SCLSCI8N + 1
623 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
624
625 /* The SD field of the SD4 form instruction, for halfword. */
626#define SE_SDH SE_SD + 1
627 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
628
629 /* The SD field of the SD4 form instruction, for word. */
630#define SE_SDW SE_SDH + 1
631 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
1da177e4
LT		 632
633 /* The SH field in an X or M form instruction. */
08d96e0b 634#define SH SE_SDW + 1
1da177e4 635#define SH_MASK (0x1f << 11)
cc7639ce
BS		 636 /* The other UIMM field in a EVX form instruction. */
637#define EVUIMM SH
08d96e0b
BS		 638 /* The FC field in an atomic X form instruction. */
639#define FC SH
cc7639ce 640 { 0x1f, 11, NULL, NULL, 0 },
1da177e4 641
08d96e0b
BS		 642 /* The SI field in a HTM X form instruction. */
643#define HTM_SI SH + 1
644 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
1da177e4
LT		 645
646 /* The SH field in an MD form instruction. This is split. */
08d96e0b 647#define SH6 HTM_SI + 1
1da177e4 648#define SH6_MASK ((0x1f << 11) | (1 << 1))
08d96e0b 649 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
1da177e4 650
897f112b
ME		 651 /* The SH field of the tlbwe instruction, which is optional. */
652#define SHO SH6 + 1
cc7639ce 653 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
897f112b 654
1da177e4 655 /* The SI field in a D form instruction. */
897f112b 656#define SI SHO + 1
cc7639ce 657 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
1da177e4
LT		 658
659 /* The SI field in a D form instruction when we accept a wide range
660 of positive values. */
661#define SISIGNOPT SI + 1
cc7639ce 662 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
1da177e4 663
08d96e0b
BS		 664 /* The SI8 field in a D form instruction. */
665#define SI8 SISIGNOPT + 1
666 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
1da177e4
LT		 667
668 /* The SPR field in an XFX form instruction. This is flipped--the
669 lower 5 bits are stored in the upper 5 and vice- versa. */
08d96e0b 670#define SPR SI8 + 1
1da177e4 671#define PMR SPR
08d96e0b 672#define TMR SPR
1da177e4 673#define SPR_MASK (0x3ff << 11)
cc7639ce 674 { 0x3ff, 11, insert_spr, extract_spr, 0 },
1da177e4
LT		 675
676 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
677#define SPRBAT SPR + 1
678#define SPRBAT_MASK (0x3 << 17)
cc7639ce 679 { 0x3, 17, NULL, NULL, 0 },
1da177e4
LT		 680
681 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
682#define SPRG SPRBAT + 1
cc7639ce 683 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
1da177e4
LT		 684
685 /* The SR field in an X form instruction. */
686#define SR SPRG + 1
08d96e0b
BS		 687 /* The 4-bit UIMM field in a VX form instruction. */
688#define UIMM4 SR
cc7639ce 689 { 0xf, 16, NULL, NULL, 0 },
1da177e4
LT		 690
691 /* The STRM field in an X AltiVec form instruction. */
692#define STRM SR + 1
08d96e0b
BS		 693 /* The T field in a tlbilx form instruction. */
694#define T STRM
695 /* The L field in wclr instructions. */
696#define L2 STRM
cc7639ce 697 { 0x3, 21, NULL, NULL, 0 },
1da177e4 698
08d96e0b
BS		 699 /* The ESYNC field in an X (sync) form instruction. */
700#define ESYNC STRM + 1
701 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
1da177e4
LT		 702
703 /* The SV field in a POWER SC form instruction. */
08d96e0b 704#define SV ESYNC + 1
cc7639ce 705 { 0x3fff, 2, NULL, NULL, 0 },
1da177e4
LT		 706
707 /* The TBR field in an XFX form instruction. This is like the SPR
708 field, but it is optional. */
709#define TBR SV + 1
08d96e0b
BS		 710 { 0x3ff, 11, insert_tbr, extract_tbr,
711 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
712 /* If the TBR operand is ommitted, use the value 268. */
713 { -1, 268, NULL, NULL, 0},
1da177e4
LT		 714
715 /* The TO field in a D or X form instruction. */
08d96e0b
BS		 716#define TO TBR + 2
717#define DUI TO
1da177e4 718#define TO_MASK (0x1f << 21)
cc7639ce 719 { 0x1f, 21, NULL, NULL, 0 },
1da177e4
LT		 720
721 /* The UI field in a D form instruction. */
cc7639ce
BS		 722#define UI TO + 1
723 { 0xffff, 0, NULL, NULL, 0 },
1da177e4 724
08d96e0b
BS		 725#define UISIGNOPT UI + 1
726 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
727
728 /* The IMM field in an SE_IM5 instruction. */
729#define UI5 UISIGNOPT + 1
730 { 0x1f, 4, NULL, NULL, 0 },
731
732 /* The OIMM field in an SE_OIM5 instruction. */
733#define OIMM5 UI5 + 1
734 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
735
736 /* The UI7 field in an SE_LI instruction. */
737#define UI7 OIMM5 + 1
738 { 0x7f, 4, NULL, NULL, 0 },
1da177e4
LT		 739
740 /* The VA field in a VA, VX or VXR form instruction. */
08d96e0b 741#define VA UI7 + 1
cc7639ce 742 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
1da177e4
LT		 743
744 /* The VB field in a VA, VX or VXR form instruction. */
745#define VB VA + 1
cc7639ce 746 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
1da177e4
LT		 747
748 /* The VC field in a VA form instruction. */
749#define VC VB + 1
cc7639ce 750 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
1da177e4
LT		 751
752 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
753#define VD VC + 1
754#define VS VD
cc7639ce 755 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
1da177e4 756
08d96e0b 757 /* The SIMM field in a VX form instruction, and TE in Z form. */
1da177e4 758#define SIMM VD + 1
08d96e0b 759#define TE SIMM
cc7639ce 760 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
1da177e4
LT		 761
762 /* The UIMM field in a VX form instruction. */
763#define UIMM SIMM + 1
08d96e0b 764#define DCTL UIMM
cc7639ce 765 { 0x1f, 16, NULL, NULL, 0 },
1da177e4 766
08d96e0b
BS		 767 /* The 3-bit UIMM field in a VX form instruction. */
768#define UIMM3 UIMM + 1
769 { 0x7, 16, NULL, NULL, 0 },
1da177e4 770
08d96e0b
BS		 771 /* The 6-bit UIM field in a X form instruction. */
772#define UIM6 UIMM3 + 1
773 { 0x3f, 16, NULL, NULL, 0 },
774
775 /* The SIX field in a VX form instruction. */
776#define SIX UIM6 + 1
777 { 0xf, 11, NULL, NULL, 0 },
778
779 /* The PS field in a VX form instruction. */
780#define PS SIX + 1
781 { 0x1, 9, NULL, NULL, 0 },
782
1da177e4 783 /* The SHB field in a VA form instruction. */
08d96e0b 784#define SHB PS + 1
cc7639ce 785 { 0xf, 6, NULL, NULL, 0 },
1da177e4
LT		 786
787 /* The other UIMM field in a half word EVX form instruction. */
cc7639ce
BS		 788#define EVUIMM_2 SHB + 1
789 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
1da177e4
LT		 790
791 /* The other UIMM field in a word EVX form instruction. */
792#define EVUIMM_4 EVUIMM_2 + 1
cc7639ce 793 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
1da177e4
LT		 794
795 /* The other UIMM field in a double EVX form instruction. */
796#define EVUIMM_8 EVUIMM_4 + 1
cc7639ce 797 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
1da177e4 798
08d96e0b 799 /* The WS or DRM field in an X form instruction. */
1da177e4 800#define WS EVUIMM_8 + 1
08d96e0b 801#define DRM WS
cc7639ce 802 { 0x7, 11, NULL, NULL, 0 },
897f112b 803
08d96e0b
BS		 804 /* PowerPC paired singles extensions. */
805 /* W bit in the pair singles instructions for x type instructions. */
806#define PSWM WS + 1
807 /* The BO16 field in a BD8 form instruction. */
808#define BO16 PSWM
809 { 0x1, 10, 0, 0, 0 },
810
811 /* IDX bits for quantization in the pair singles instructions. */
812#define PSQ PSWM + 1
813 { 0x7, 12, 0, 0, 0 },
814
815 /* IDX bits for quantization in the pair singles x-type instructions. */
816#define PSQM PSQ + 1
817 { 0x7, 7, 0, 0, 0 },
818
819 /* Smaller D field for quantization in the pair singles instructions. */
820#define PSD PSQM + 1
821 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
822
823 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
824#define A_L PSD + 1
cc7639ce 825#define W A_L
08d96e0b 826#define X_R A_L
cc7639ce 827 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
897f112b 828
08d96e0b 829 /* The RMC or CY field in a Z23 form instruction. */
cc7639ce 830#define RMC A_L + 1
08d96e0b 831#define CY RMC
cc7639ce 832 { 0x3, 9, NULL, NULL, 0 },
897f112b 833
897f112b 834#define R RMC + 1
cc7639ce 835 { 0x1, 16, NULL, NULL, 0 },
897f112b 836
08d96e0b
BS		 837#define RIC R + 1
838 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
897f112b 839
08d96e0b
BS		 840#define PRS RIC + 1
841 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
897f112b 842
08d96e0b 843#define SP PRS + 1
cc7639ce 844 { 0x3, 19, NULL, NULL, 0 },
897f112b
ME		 845
846#define S SP + 1
cc7639ce 847 { 0x1, 20, NULL, NULL, 0 },
897f112b 848
08d96e0b
BS		 849 /* The S field in a XL form instruction. */
850#define SXL S + 1
851 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
852 /* If the SXL operand is ommitted, use the value 1. */
853 { -1, 1, NULL, NULL, 0},
897f112b 854
897f112b 855 /* SH field starting at bit position 16. */
08d96e0b 856#define SH16 SXL + 2
cc7639ce
BS		 857 /* The DCM and DGM fields in a Z form instruction. */
858#define DCM SH16
859#define DGM DCM
860 { 0x3f, 10, NULL, NULL, 0 },
897f112b
ME		 861
862 /* The EH field in larx instruction. */
cc7639ce
BS		 863#define EH SH16 + 1
864 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
865
866 /* The L field in an mtfsf or XFL form instruction. */
08d96e0b 867 /* The A field in a HTM X form instruction. */
cc7639ce 868#define XFL_L EH + 1
08d96e0b 869#define HTM_A XFL_L
cc7639ce 870 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
08d96e0b
BS		 871
872 /* Xilinx APU related masks and macros */
873#define FCRT XFL_L + 1
874#define FCRT_MASK (0x1f << 21)
875 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
876
877 /* Xilinx FSL related masks and macros */
878#define FSL FCRT + 1
879#define FSL_MASK (0x1f << 11)
880 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
881
882 /* Xilinx UDI related masks and macros */
883#define URT FSL + 1
884 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
885
886#define URA URT + 1
887 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
888
889#define URB URA + 1
890 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
891
892#define URC URB + 1
893 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
894
895 /* The VLESIMM field in a D form instruction. */
896#define VLESIMM URC + 1
897 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
898 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
899
900 /* The VLENSIMM field in a D form instruction. */
901#define VLENSIMM VLESIMM + 1
902 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
903 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
904
905 /* The VLEUIMM field in a D form instruction. */
906#define VLEUIMM VLENSIMM + 1
907 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
908
909 /* The VLEUIMML field in a D form instruction. */
910#define VLEUIMML VLEUIMM + 1
911 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
912
913 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
914#define XS6 VLEUIMML + 1
915#define XT6 XS6
916 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
917
918 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
919#define XSQ6 XT6 + 1
920#define XTQ6 XSQ6
921 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
922
923 /* The XA field in an XX3 form instruction. This is split. */
924#define XA6 XTQ6 + 1
925 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
926
927 /* The XB field in an XX2 or XX3 form instruction. This is split. */
928#define XB6 XA6 + 1
929 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
930
931 /* The XB field in an XX3 form instruction when it must be the same as
932 the XA field in the instruction. This is used in extended mnemonics
933 like xvmovdp. This is split. */
934#define XB6S XB6 + 1
935 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
936
937 /* The XC field in an XX4 form instruction. This is split. */
938#define XC6 XB6S + 1
939 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
940
941 /* The DM or SHW field in an XX3 form instruction. */
942#define DM XC6 + 1
943#define SHW DM
944 { 0x3, 8, NULL, NULL, 0 },
945
946 /* The DM field in an extended mnemonic XX3 form instruction. */
947#define DMEX DM + 1
948 { 0x3, 8, insert_dm, extract_dm, 0 },
949
950 /* The UIM field in an XX2 form instruction. */
951#define UIM DMEX + 1
952 /* The 2-bit UIMM field in a VX form instruction. */
953#define UIMM2 UIM
954 /* The 2-bit L field in a darn instruction. */
955#define LRAND UIM
956 { 0x3, 16, NULL, NULL, 0 },
957
958#define ERAT_T UIM + 1
959 { 0x7, 21, NULL, NULL, 0 },
960
961#define IH ERAT_T + 1
962 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
963
964 /* The 8-bit IMM8 field in a XX1 form instruction. */
965#define IMM8 IH + 1
966 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
1da177e4
LT		 967};
968
cc7639ce
BS		 969const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
970 / sizeof (powerpc_operands[0]));
971
1da177e4
LT		 972/* The functions used to insert and extract complicated operands. */
973
08d96e0b
BS		 974/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
975
976static unsigned long
977insert_arx (unsigned long insn,
978 long value,
979 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
980 const char **errmsg ATTRIBUTE_UNUSED)
981{
982 if (value >= 8 && value < 24)
983 return insn | ((value - 8) & 0xf);
984 else
985 {
986 *errmsg = _("invalid register");
987 return 0;
988 }
989}
990
991static long
992extract_arx (unsigned long insn,
993 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
994 int *invalid ATTRIBUTE_UNUSED)
995{
996 return (insn & 0xf) + 8;
997}
998
999static unsigned long
1000insert_ary (unsigned long insn,
1001 long value,
1002 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1003 const char **errmsg ATTRIBUTE_UNUSED)
1004{
1005 if (value >= 8 && value < 24)
1006 return insn | (((value - 8) & 0xf) << 4);
1007 else
1008 {
1009 *errmsg = _("invalid register");
1010 return 0;
1011 }
1012}
1013
1014static long
1015extract_ary (unsigned long insn,
1016 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1017 int *invalid ATTRIBUTE_UNUSED)
1018{
1019 return ((insn >> 4) & 0xf) + 8;
1020}
1021
1022static unsigned long
1023insert_rx (unsigned long insn,
1024 long value,
1025 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1026 const char **errmsg)
1027{
1028 if (value >= 0 && value < 8)
1029 return insn | value;
1030 else if (value >= 24 && value <= 31)
1031 return insn | (value - 16);
1032 else
1033 {
1034 *errmsg = _("invalid register");
1035 return 0;
1036 }
1037}
1038
1039static long
1040extract_rx (unsigned long insn,
1041 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1042 int *invalid ATTRIBUTE_UNUSED)
1043{
1044 int value = insn & 0xf;
1045 if (value >= 0 && value < 8)
1046 return value;
1047 else
1048 return value + 16;
1049}
1050
1051static unsigned long
1052insert_ry (unsigned long insn,
1053 long value,
1054 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1055 const char **errmsg)
1056{
1057 if (value >= 0 && value < 8)
1058 return insn | (value << 4);
1059 else if (value >= 24 && value <= 31)
1060 return insn | ((value - 16) << 4);
1061 else
1062 {
1063 *errmsg = _("invalid register");
1064 return 0;
1065 }
1066}
1067
1068static long
1069extract_ry (unsigned long insn,
1070 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1071 int *invalid ATTRIBUTE_UNUSED)
1072{
1073 int value = (insn >> 4) & 0xf;
1074 if (value >= 0 && value < 8)
1075 return value;
1076 else
1077 return value + 16;
1078}
1079
1da177e4
LT		 1080/* The BA field in an XL form instruction when it must be the same as
1081 the BT field in the same instruction. This operand is marked FAKE.
1082 The insertion function just copies the BT field into the BA field,
1083 and the extraction function just checks that the fields are the
1084 same. */
1085
1da177e4
LT		 1086static unsigned long
1087insert_bat (unsigned long insn,
1088 long value ATTRIBUTE_UNUSED,
08d96e0b 1089 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1090 const char **errmsg ATTRIBUTE_UNUSED)
1091{
1092 return insn | (((insn >> 21) & 0x1f) << 16);
1093}
1094
1095static long
1096extract_bat (unsigned long insn,
08d96e0b 1097 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1098 int *invalid)
1099{
1100 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
1101 *invalid = 1;
1102 return 0;
1103}
1104
1105/* The BB field in an XL form instruction when it must be the same as
1106 the BA field in the same instruction. This operand is marked FAKE.
1107 The insertion function just copies the BA field into the BB field,
1108 and the extraction function just checks that the fields are the
1109 same. */
1110
1da177e4
LT		 1111static unsigned long
1112insert_bba (unsigned long insn,
1113 long value ATTRIBUTE_UNUSED,
08d96e0b 1114 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1115 const char **errmsg ATTRIBUTE_UNUSED)
1116{
1117 return insn | (((insn >> 16) & 0x1f) << 11);
1118}
1119
1120static long
1121extract_bba (unsigned long insn,
08d96e0b 1122 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1123 int *invalid)
1124{
1125 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1126 *invalid = 1;
1127 return 0;
1128}
1129
1da177e4
LT		 1130/* The BD field in a B form instruction when the - modifier is used.
1131 This modifier means that the branch is not expected to be taken.
1132 For chips built to versions of the architecture prior to version 2
1133 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1134 if the offset is negative. When extracting, we require that the y
1135 bit be 1 and that the offset be positive, since if the y bit is 0
1136 we just want to print the normal form of the instruction.
1137 Power4 compatible targets use two bits, "a", and "t", instead of
1138 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1139 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1140 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
cc7639ce
BS		 1141 for branch on CTR. We only handle the taken/not-taken hint here.
1142 Note that we don't relax the conditions tested here when
1143 disassembling with -Many because insns using extract_bdm and
1144 extract_bdp always occur in pairs. One or the other will always
1145 be valid. */
1da177e4 1146
08d96e0b 1147#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1da177e4 1148
1da177e4
LT		 1149static unsigned long
1150insert_bdm (unsigned long insn,
1151 long value,
08d96e0b 1152 ppc_cpu_t dialect,
1da177e4
LT		 1153 const char **errmsg ATTRIBUTE_UNUSED)
1154{
08d96e0b 1155 if ((dialect & ISA_V2) == 0)
1da177e4
LT		 1156 {
1157 if ((value & 0x8000) != 0)
1158 insn |= 1 << 21;
1159 }
1160 else
1161 {
1162 if ((insn & (0x14 << 21)) == (0x04 << 21))
1163 insn |= 0x02 << 21;
1164 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1165 insn |= 0x08 << 21;
1166 }
1167 return insn | (value & 0xfffc);
1168}
1169
1170static long
1171extract_bdm (unsigned long insn,
08d96e0b 1172 ppc_cpu_t dialect,
1da177e4
LT		 1173 int *invalid)
1174{
08d96e0b 1175 if ((dialect & ISA_V2) == 0)
1da177e4
LT		 1176 {
1177 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1178 *invalid = 1;
1179 }
1180 else
1181 {
1182 if ((insn & (0x17 << 21)) != (0x06 << 21)
1183 && (insn & (0x1d << 21)) != (0x18 << 21))
1184 *invalid = 1;
1185 }
1186
1187 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1188}
1189
1190/* The BD field in a B form instruction when the + modifier is used.
1191 This is like BDM, above, except that the branch is expected to be
1192 taken. */
1193
1da177e4
LT		 1194static unsigned long
1195insert_bdp (unsigned long insn,
1196 long value,
08d96e0b 1197 ppc_cpu_t dialect,
1da177e4
LT		 1198 const char **errmsg ATTRIBUTE_UNUSED)
1199{
08d96e0b 1200 if ((dialect & ISA_V2) == 0)
1da177e4
LT		 1201 {
1202 if ((value & 0x8000) == 0)
1203 insn |= 1 << 21;
1204 }
1205 else
1206 {
1207 if ((insn & (0x14 << 21)) == (0x04 << 21))
1208 insn |= 0x03 << 21;
1209 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1210 insn |= 0x09 << 21;
1211 }
1212 return insn | (value & 0xfffc);
1213}
1214
1215static long
1216extract_bdp (unsigned long insn,
08d96e0b 1217 ppc_cpu_t dialect,
1da177e4
LT		 1218 int *invalid)
1219{
08d96e0b 1220 if ((dialect & ISA_V2) == 0)
1da177e4
LT		 1221 {
1222 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1223 *invalid = 1;
1224 }
1225 else
1226 {
1227 if ((insn & (0x17 << 21)) != (0x07 << 21)
1228 && (insn & (0x1d << 21)) != (0x19 << 21))
1229 *invalid = 1;
1230 }
1231
1232 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1233}
1234
08d96e0b
BS		 1235static inline int
1236valid_bo_pre_v2 (long value)
1da177e4 1237{
08d96e0b
BS		 1238 /* Certain encodings have bits that are required to be zero.
1239 These are (z must be zero, y may be anything):
1240 0000y
1241 0001y
1242 001zy
1243 0100y
1244 0101y
1245 011zy
1246 1z00y
1247 1z01y
1248 1z1zz
1249 */
1250 if ((value & 0x14) == 0)
1251 return 1;
1252 else if ((value & 0x14) == 0x4)
1253 return (value & 0x2) == 0;
1254 else if ((value & 0x14) == 0x10)
1255 return (value & 0x8) == 0;
1256 else
1257 return value == 0x14;
1258}
cc7639ce 1259
08d96e0b
BS		 1260static inline int
1261valid_bo_post_v2 (long value)
1262{
cc7639ce
BS		 1263 /* Certain encodings have bits that are required to be zero.
1264 These are (z must be zero, a & t may be anything):
1265 0000z
1266 0001z
08d96e0b 1267 001at
cc7639ce
BS		 1268 0100z
1269 0101z
cc7639ce
BS		 1270 011at
1271 1a00t
1272 1a01t
1273 1z1zz
1274 */
1275 if ((value & 0x14) == 0)
1276 return (value & 0x1) == 0;
1277 else if ((value & 0x14) == 0x14)
1278 return value == 0x14;
1da177e4 1279 else
cc7639ce 1280 return 1;
1da177e4
LT		 1281}
1282
1da177e4
LT		 1283/* Check for legal values of a BO field. */
1284
1285static int
08d96e0b 1286valid_bo (long value, ppc_cpu_t dialect, int extract)
1da177e4 1287{
08d96e0b
BS		 1288 int valid_y = valid_bo_pre_v2 (value);
1289 int valid_at = valid_bo_post_v2 (value);
1290
1291 /* When disassembling with -Many, accept either encoding on the
1292 second pass through opcodes. */
1293 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1294 return valid_y || valid_at;
1295 if ((dialect & ISA_V2) == 0)
1296 return valid_y;
1da177e4 1297 else
08d96e0b 1298 return valid_at;
1da177e4
LT		 1299}
1300
1301/* The BO field in a B form instruction. Warn about attempts to set
1302 the field to an illegal value. */
1303
1304static unsigned long
1305insert_bo (unsigned long insn,
1306 long value,
08d96e0b 1307 ppc_cpu_t dialect,
1da177e4
LT		 1308 const char **errmsg)
1309{
cc7639ce 1310 if (!valid_bo (value, dialect, 0))
1da177e4 1311 *errmsg = _("invalid conditional option");
08d96e0b
BS		 1312 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1313 *errmsg = _("invalid counter access");
1da177e4
LT		 1314 return insn | ((value & 0x1f) << 21);
1315}
1316
1317static long
1318extract_bo (unsigned long insn,
08d96e0b 1319 ppc_cpu_t dialect,
1da177e4
LT		 1320 int *invalid)
1321{
1322 long value;
1323
1324 value = (insn >> 21) & 0x1f;
cc7639ce 1325 if (!valid_bo (value, dialect, 1))
1da177e4
LT		 1326 *invalid = 1;
1327 return value;
1328}
1329
1330/* The BO field in a B form instruction when the + or - modifier is
1331 used. This is like the BO field, but it must be even. When
1332 extracting it, we force it to be even. */
1333
1334static unsigned long
1335insert_boe (unsigned long insn,
1336 long value,
08d96e0b 1337 ppc_cpu_t dialect,
1da177e4
LT		 1338 const char **errmsg)
1339{
cc7639ce 1340 if (!valid_bo (value, dialect, 0))
1da177e4 1341 *errmsg = _("invalid conditional option");
08d96e0b
BS		 1342 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1343 *errmsg = _("invalid counter access");
1da177e4
LT		 1344 else if ((value & 1) != 0)
1345 *errmsg = _("attempt to set y bit when using + or - modifier");
1346
1347 return insn | ((value & 0x1f) << 21);
1348}
1349
1350static long
1351extract_boe (unsigned long insn,
08d96e0b 1352 ppc_cpu_t dialect,
1da177e4
LT		 1353 int *invalid)
1354{
1355 long value;
1356
1357 value = (insn >> 21) & 0x1f;
cc7639ce 1358 if (!valid_bo (value, dialect, 1))
1da177e4
LT		 1359 *invalid = 1;
1360 return value & 0x1e;
1361}
1362
08d96e0b
BS		 1363/* The DCMX field in a X form instruction when the field is split
1364 into separate DC, DM and DX fields. */
1da177e4
LT		 1365
1366static unsigned long
08d96e0b 1367insert_dcmxs (unsigned long insn,
1da177e4 1368 long value,
08d96e0b
BS		 1369 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1370 const char **errmsg ATTRIBUTE_UNUSED)
1da177e4 1371{
08d96e0b 1372 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1da177e4
LT		 1373}
1374
1375static long
08d96e0b
BS		 1376extract_dcmxs (unsigned long insn,
1377 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1378 int *invalid ATTRIBUTE_UNUSED)
1379{
08d96e0b 1380 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1da177e4
LT		 1381}
1382
08d96e0b
BS		 1383/* The D field in a DX form instruction when the field is split
1384 into separate D0, D1 and D2 fields. */
1da177e4
LT		 1385
1386static unsigned long
08d96e0b 1387insert_dxd (unsigned long insn,
1da177e4 1388 long value,
08d96e0b
BS		 1389 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1390 const char **errmsg ATTRIBUTE_UNUSED)
1da177e4 1391{
08d96e0b 1392 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1da177e4
LT		 1393}
1394
1395static long
08d96e0b
BS		 1396extract_dxd (unsigned long insn,
1397 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1398 int *invalid ATTRIBUTE_UNUSED)
1399{
08d96e0b
BS		 1400 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1401 return (dxd ^ 0x8000) - 0x8000;
1da177e4
LT		 1402}
1403
1da177e4 1404static unsigned long
08d96e0b 1405insert_dxdn (unsigned long insn,
1da177e4 1406 long value,
08d96e0b
BS		 1407 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1408 const char **errmsg ATTRIBUTE_UNUSED)
1da177e4 1409{
08d96e0b 1410 return insert_dxd (insn, -value, dialect, errmsg);
1da177e4
LT		 1411}
1412
1da177e4 1413static long
08d96e0b
BS		 1414extract_dxdn (unsigned long insn,
1415 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1416 int *invalid ATTRIBUTE_UNUSED)
1417{
08d96e0b 1418 return -extract_dxd (insn, dialect, invalid);
1da177e4
LT		 1419}
1420
1421/* FXM mask in mfcr and mtcrf instructions. */
1422
1423static unsigned long
1424insert_fxm (unsigned long insn,
1425 long value,
08d96e0b 1426 ppc_cpu_t dialect,
1da177e4
LT		 1427 const char **errmsg)
1428{
897f112b
ME		 1429 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1430 one bit of the mask field is set. */
1431 if ((insn & (1 << 20)) != 0)
1432 {
1433 if (value == 0 || (value & -value) != value)
1434 {
1435 *errmsg = _("invalid mask field");
1436 value = 0;
1437 }
1438 }
1439
1da177e4
LT		 1440 /* If only one bit of the FXM field is set, we can use the new form
1441 of the instruction, which is faster. Unlike the Power4 branch hint
897f112b
ME		 1442 encoding, this is not backward compatible. Do not generate the
1443 new form unless -mpower4 has been given, or -many and the two
1444 operand form of mfcr was used. */
08d96e0b
BS		 1445 else if (value > 0
1446 && (value & -value) == value
897f112b
ME		 1447 && ((dialect & PPC_OPCODE_POWER4) != 0
1448 || ((dialect & PPC_OPCODE_ANY) != 0
1449 && (insn & (0x3ff << 1)) == 19 << 1)))
1da177e4
LT		 1450 insn |= 1 << 20;
1451
1452 /* Any other value on mfcr is an error. */
1453 else if ((insn & (0x3ff << 1)) == 19 << 1)
1454 {
08d96e0b
BS		 1455 /* A value of -1 means we used the one operand form of
1456 mfcr which is valid. */
1457 if (value != -1)
1458 *errmsg = _("invalid mfcr mask");
1da177e4
LT		 1459 value = 0;
1460 }
1461
1462 return insn | ((value & 0xff) << 12);
1463}
1464
1465static long
1466extract_fxm (unsigned long insn,
08d96e0b 1467 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1468 int *invalid)
1469{
1470 long mask = (insn >> 12) & 0xff;
1471
1472 /* Is this a Power4 insn? */
1473 if ((insn & (1 << 20)) != 0)
1474 {
897f112b
ME		 1475 /* Exactly one bit of MASK should be set. */
1476 if (mask == 0 || (mask & -mask) != mask)
1da177e4 1477 *invalid = 1;
1da177e4
LT		 1478 }
1479
1480 /* Check that non-power4 form of mfcr has a zero MASK. */
1481 else if ((insn & (0x3ff << 1)) == 19 << 1)
1482 {
1483 if (mask != 0)
1484 *invalid = 1;
08d96e0b
BS		 1485 else
1486 mask = -1;
1da177e4
LT		 1487 }
1488
1489 return mask;
1490}
1491
08d96e0b
BS		 1492static unsigned long
1493insert_li20 (unsigned long insn,
1494 long value,
1495 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1496 const char **errmsg ATTRIBUTE_UNUSED)
1497{
1498 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1499}
1500
1501static long
1502extract_li20 (unsigned long insn,
1503 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1504 int *invalid ATTRIBUTE_UNUSED)
1505{
1506 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1507
1508 return ext
1509 | (((insn >> 11) & 0xf) << 16)
1510 | (((insn >> 17) & 0xf) << 12)
1511 | (((insn >> 16) & 0x1) << 11)
1512 | (insn & 0x7ff);
1513}
1514
1515/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1516 For SYNC, some L values are reserved:
1517 * Value 3 is reserved on newer server cpus.
1518 * Values 2 and 3 are reserved on all other cpus. */
1da177e4 1519
1da177e4 1520static unsigned long
08d96e0b 1521insert_ls (unsigned long insn,
1da177e4 1522 long value,
08d96e0b 1523 ppc_cpu_t dialect,
1da177e4
LT		 1524 const char **errmsg)
1525{
08d96e0b
BS		 1526 /* For SYNC, some L values are illegal. */
1527 if (((insn >> 1) & 0x3ff) == 598)
1528 {
1529 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1530 if (value > max_lvalue)
1531 {
1532 *errmsg = _("illegal L operand value");
1533 return insn;
1534 }
1535 }
1536
1537 return insn | ((value & 0x3) << 21);
1da177e4
LT		 1538}
1539
08d96e0b
BS		 1540/* The 4-bit E field in a sync instruction that accepts 2 operands.
1541 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1542 the complement of ESYNC-bit2. */
1543
1544static unsigned long
1545insert_esync (unsigned long insn,
1546 long value,
1547 ppc_cpu_t dialect,
1548 const char **errmsg)
1da177e4 1549{
08d96e0b
BS		 1550 unsigned long ls = (insn >> 21) & 0x03;
1551
1552 if (value == 0)
1553 {
1554 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1555 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1556 *errmsg = _("illegal L operand value");
1557 return insn;
1558 }
1559
1560 if ((ls & ~0x1)
1561 || (((value >> 1) & 0x1) ^ ls) == 0)
1562 *errmsg = _("incompatible L operand value");
1563
1564 return insn | ((value & 0xf) << 16);
1da177e4
LT		 1565}
1566
1567/* The MB and ME fields in an M form instruction expressed as a single
1568 operand which is itself a bitmask. The extraction function always
1569 marks it as invalid, since we never want to recognize an
1570 instruction which uses a field of this type. */
1571
1572static unsigned long
1573insert_mbe (unsigned long insn,
1574 long value,
08d96e0b 1575 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1576 const char **errmsg)
1577{
1578 unsigned long uval, mask;
1579 int mb, me, mx, count, last;
1580
1581 uval = value;
1582
1583 if (uval == 0)
1584 {
1585 *errmsg = _("illegal bitmask");
1586 return insn;
1587 }
1588
1589 mb = 0;
1590 me = 32;
1591 if ((uval & 1) != 0)
1592 last = 1;
1593 else
1594 last = 0;
1595 count = 0;
1596
1597 /* mb: location of last 0->1 transition */
1598 /* me: location of last 1->0 transition */
1599 /* count: # transitions */
1600
1601 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1602 {
1603 if ((uval & mask) && !last)
1604 {
1605 ++count;
1606 mb = mx;
1607 last = 1;
1608 }
1609 else if (!(uval & mask) && last)
1610 {
1611 ++count;
1612 me = mx;
1613 last = 0;
1614 }
1615 }
1616 if (me == 0)
1617 me = 32;
1618
1619 if (count != 2 && (count != 0 || ! last))
1620 *errmsg = _("illegal bitmask");
1621
1622 return insn | (mb << 6) | ((me - 1) << 1);
1623}
1624
1625static long
1626extract_mbe (unsigned long insn,
08d96e0b 1627 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1628 int *invalid)
1629{
1630 long ret;
1631 int mb, me;
1632 int i;
1633
1634 *invalid = 1;
1635
1636 mb = (insn >> 6) & 0x1f;
1637 me = (insn >> 1) & 0x1f;
1638 if (mb < me + 1)
1639 {
1640 ret = 0;
1641 for (i = mb; i <= me; i++)
1642 ret |= 1L << (31 - i);
1643 }
1644 else if (mb == me + 1)
1645 ret = ~0;
1646 else /* (mb > me + 1) */
1647 {
1648 ret = ~0;
1649 for (i = me + 1; i < mb; i++)
1650 ret &= ~(1L << (31 - i));
1651 }
1652 return ret;
1653}
1654
1655/* The MB or ME field in an MD or MDS form instruction. The high bit
1656 is wrapped to the low end. */
1657
1da177e4
LT		 1658static unsigned long
1659insert_mb6 (unsigned long insn,
1660 long value,
08d96e0b 1661 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1662 const char **errmsg ATTRIBUTE_UNUSED)
1663{
1664 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1665}
1666
1da177e4
LT		 1667static long
1668extract_mb6 (unsigned long insn,
08d96e0b 1669 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1670 int *invalid ATTRIBUTE_UNUSED)
1671{
1672 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1673}
1674
1675/* The NB field in an X form instruction. The value 32 is stored as
1676 0. */
1677
1da177e4
LT		 1678static long
1679extract_nb (unsigned long insn,
08d96e0b 1680 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1681 int *invalid ATTRIBUTE_UNUSED)
1682{
1683 long ret;
1684
1685 ret = (insn >> 11) & 0x1f;
1686 if (ret == 0)
1687 ret = 32;
1688 return ret;
1689}
1690
08d96e0b
BS		 1691/* The NB field in an lswi instruction, which has special value
1692 restrictions. The value 32 is stored as 0. */
1693
1694static unsigned long
1695insert_nbi (unsigned long insn,
1696 long value,
1697 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1698 const char **errmsg ATTRIBUTE_UNUSED)
1699{
1700 long rtvalue = (insn & RT_MASK) >> 21;
1701 long ravalue = (insn & RA_MASK) >> 16;
1702
1703 if (value == 0)
1704 value = 32;
1705 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1706 : ravalue))
1707 *errmsg = _("address register in load range");
1708 return insn | ((value & 0x1f) << 11);
1709}
1710
1da177e4
LT		 1711/* The NSI field in a D form instruction. This is the same as the SI
1712 field, only negated. The extraction function always marks it as
1713 invalid, since we never want to recognize an instruction which uses
1714 a field of this type. */
1715
1da177e4
LT		 1716static unsigned long
1717insert_nsi (unsigned long insn,
1718 long value,
08d96e0b 1719 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1720 const char **errmsg ATTRIBUTE_UNUSED)
1721{
1722 return insn | (-value & 0xffff);
1723}
1724
1725static long
1726extract_nsi (unsigned long insn,
08d96e0b 1727 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1728 int *invalid)
1729{
1730 *invalid = 1;
1731 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1732}
1733
1734/* The RA field in a D or X form instruction which is an updating
1735 load, which means that the RA field may not be zero and may not
1736 equal the RT field. */
1737
1738static unsigned long
1739insert_ral (unsigned long insn,
1740 long value,
08d96e0b 1741 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1742 const char **errmsg)
1743{
1744 if (value == 0
1745 || (unsigned long) value == ((insn >> 21) & 0x1f))
1746 *errmsg = "invalid register operand when updating";
1747 return insn | ((value & 0x1f) << 16);
1748}
1749
1750/* The RA field in an lmw instruction, which has special value
1751 restrictions. */
1752
1753static unsigned long
1754insert_ram (unsigned long insn,
1755 long value,
08d96e0b 1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1757 const char **errmsg)
1758{
1759 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1760 *errmsg = _("index register in load range");
1761 return insn | ((value & 0x1f) << 16);
1762}
1763
08d96e0b 1764/* The RA field in the DQ form lq or an lswx instruction, which have special
1da177e4
LT		 1765 value restrictions. */
1766
1da177e4
LT		 1767static unsigned long
1768insert_raq (unsigned long insn,
1769 long value,
08d96e0b 1770 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1771 const char **errmsg)
1772{
1773 long rtvalue = (insn & RT_MASK) >> 21;
1774
1775 if (value == rtvalue)
1776 *errmsg = _("source and target register operands must be different");
1777 return insn | ((value & 0x1f) << 16);
1778}
1779
1780/* The RA field in a D or X form instruction which is an updating
1781 store or an updating floating point load, which means that the RA
1782 field may not be zero. */
1783
1784static unsigned long
1785insert_ras (unsigned long insn,
1786 long value,
08d96e0b 1787 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1788 const char **errmsg)
1789{
1790 if (value == 0)
1791 *errmsg = _("invalid register operand when updating");
1792 return insn | ((value & 0x1f) << 16);
1793}
1794
1795/* The RB field in an X form instruction when it must be the same as
1796 the RS field in the instruction. This is used for extended
1797 mnemonics like mr. This operand is marked FAKE. The insertion
1798 function just copies the BT field into the BA field, and the
1799 extraction function just checks that the fields are the same. */
1800
1da177e4
LT		 1801static unsigned long
1802insert_rbs (unsigned long insn,
1803 long value ATTRIBUTE_UNUSED,
08d96e0b 1804 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1805 const char **errmsg ATTRIBUTE_UNUSED)
1806{
1807 return insn | (((insn >> 21) & 0x1f) << 11);
1808}
1809
1810static long
1811extract_rbs (unsigned long insn,
08d96e0b 1812 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1813 int *invalid)
1814{
1815 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1816 *invalid = 1;
1817 return 0;
1818}
1819
08d96e0b
BS		 1820/* The RB field in an lswx instruction, which has special value
1821 restrictions. */
1da177e4 1822
1da177e4 1823static unsigned long
08d96e0b 1824insert_rbx (unsigned long insn,
1da177e4 1825 long value,
08d96e0b 1826 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1827 const char **errmsg)
1828{
08d96e0b 1829 long rtvalue = (insn & RT_MASK) >> 21;
1da177e4 1830
08d96e0b
BS		 1831 if (value == rtvalue)
1832 *errmsg = _("source and target register operands must be different");
1833 return insn | ((value & 0x1f) << 11);
1da177e4
LT		 1834}
1835
08d96e0b 1836/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1da177e4 1837static unsigned long
08d96e0b
BS		 1838insert_sci8 (unsigned long insn,
1839 long value,
1840 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1841 const char **errmsg)
1da177e4 1842{
08d96e0b
BS		 1843 unsigned int fill_scale = 0;
1844 unsigned long ui8 = value;
1da177e4 1845
08d96e0b
BS		 1846 if ((ui8 & 0xffffff00) == 0)
1847 ;
1848 else if ((ui8 & 0xffffff00) == 0xffffff00)
1849 fill_scale = 0x400;
1850 else if ((ui8 & 0xffff00ff) == 0)
1851 {
1852 fill_scale = 1 << 8;
1853 ui8 >>= 8;
1854 }
1855 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1856 {
1857 fill_scale = 0x400 | (1 << 8);
1858 ui8 >>= 8;
1859 }
1860 else if ((ui8 & 0xff00ffff) == 0)
1861 {
1862 fill_scale = 2 << 8;
1863 ui8 >>= 16;
1864 }
1865 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1866 {
1867 fill_scale = 0x400 | (2 << 8);
1868 ui8 >>= 16;
1869 }
1870 else if ((ui8 & 0x00ffffff) == 0)
1871 {
1872 fill_scale = 3 << 8;
1873 ui8 >>= 24;
1874 }
1875 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1876 {
1877 fill_scale = 0x400 | (3 << 8);
1878 ui8 >>= 24;
1879 }
1880 else
1881 {
1882 *errmsg = _("illegal immediate value");
1883 ui8 = 0;
1884 }
1885
1886 return insn | fill_scale | (ui8 & 0xff);
1887}
1888
1889static long
1890extract_sci8 (unsigned long insn,
1891 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1892 int *invalid ATTRIBUTE_UNUSED)
1893{
1894 int fill = insn & 0x400;
1895 int scale_factor = (insn & 0x300) >> 5;
1896 long value = (insn & 0xff) << scale_factor;
1897
1898 if (fill != 0)
1899 value |= ~((long) 0xff << scale_factor);
1900 return value;
1901}
1da177e4 1902
1da177e4 1903static unsigned long
08d96e0b
BS		 1904insert_sci8n (unsigned long insn,
1905 long value,
1906 ppc_cpu_t dialect,
1907 const char **errmsg)
1da177e4 1908{
08d96e0b
BS		 1909 return insert_sci8 (insn, -value, dialect, errmsg);
1910}
1911
1912static long
1913extract_sci8n (unsigned long insn,
1914 ppc_cpu_t dialect,
1915 int *invalid)
1916{
1917 return -extract_sci8 (insn, dialect, invalid);
1918}
1919
1920static unsigned long
1921insert_sd4h (unsigned long insn,
1922 long value,
1923 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1924 const char **errmsg ATTRIBUTE_UNUSED)
1925{
1926 return insn | ((value & 0x1e) << 7);
1927}
1928
1929static long
1930extract_sd4h (unsigned long insn,
1931 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1932 int *invalid ATTRIBUTE_UNUSED)
1933{
1934 return ((insn >> 8) & 0xf) << 1;
1935}
1936
1937static unsigned long
1938insert_sd4w (unsigned long insn,
1939 long value,
1940 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1941 const char **errmsg ATTRIBUTE_UNUSED)
1942{
1943 return insn | ((value & 0x3c) << 6);
1944}
1945
1946static long
1947extract_sd4w (unsigned long insn,
1948 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1949 int *invalid ATTRIBUTE_UNUSED)
1950{
1951 return ((insn >> 8) & 0xf) << 2;
1952}
1953
1954static unsigned long
1955insert_oimm (unsigned long insn,
1956 long value,
1957 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1958 const char **errmsg ATTRIBUTE_UNUSED)
1959{
1960 return insn | (((value - 1) & 0x1f) << 4);
1961}
1962
1963static long
1964extract_oimm (unsigned long insn,
1965 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1966 int *invalid ATTRIBUTE_UNUSED)
1967{
1968 return ((insn >> 4) & 0x1f) + 1;
1da177e4
LT		 1969}
1970
1971/* The SH field in an MD form instruction. This is split. */
1972
1da177e4
LT		 1973static unsigned long
1974insert_sh6 (unsigned long insn,
1975 long value,
08d96e0b 1976 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1977 const char **errmsg ATTRIBUTE_UNUSED)
1978{
08d96e0b
BS		 1979 /* SH6 operand in the rldixor instructions. */
1980 if (PPC_OP (insn) == 4)
1981 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
1982 else
1983 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1da177e4
LT		 1984}
1985
1da177e4
LT		 1986static long
1987extract_sh6 (unsigned long insn,
08d96e0b 1988 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 1989 int *invalid ATTRIBUTE_UNUSED)
1990{
08d96e0b
BS		 1991 /* SH6 operand in the rldixor instructions. */
1992 if (PPC_OP (insn) == 4)
1993 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
1994 else
1995 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1da177e4
LT		 1996}
1997
1998/* The SPR field in an XFX form instruction. This is flipped--the
1999 lower 5 bits are stored in the upper 5 and vice- versa. */
2000
2001static unsigned long
2002insert_spr (unsigned long insn,
2003 long value,
08d96e0b 2004 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 2005 const char **errmsg ATTRIBUTE_UNUSED)
2006{
2007 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2008}
2009
2010static long
2011extract_spr (unsigned long insn,
08d96e0b 2012 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1da177e4
LT		 2013 int *invalid ATTRIBUTE_UNUSED)
2014{
2015 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2016}
2017
897f112b 2018/* Some dialects have 8 SPRG registers instead of the standard 4. */
08d96e0b 2019#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
897f112b
ME		 2020
2021static unsigned long
2022insert_sprg (unsigned long insn,
2023 long value,
08d96e0b 2024 ppc_cpu_t dialect,
897f112b
ME		 2025 const char **errmsg)
2026{
897f112b 2027 if (value > 7
08d96e0b 2028 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
897f112b
ME		 2029 *errmsg = _("invalid sprg number");
2030
2031 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2032 user mode. Anything else must use spr 272..279. */
2033 if (value <= 3 || (insn & 0x100) != 0)
2034 value |= 0x10;
2035
2036 return insn | ((value & 0x17) << 16);
2037}
2038
2039static long
2040extract_sprg (unsigned long insn,
08d96e0b 2041 ppc_cpu_t dialect,
897f112b
ME		 2042 int *invalid)
2043{
2044 unsigned long val = (insn >> 16) & 0x1f;
2045
2046 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
08d96e0b
BS		 2047 If not BOOKE, 405 or VLE, then both use only 272..275. */
2048 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
2049 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2050 || val <= 3
2051 || (val & 8) != 0)
897f112b
ME		 2052 *invalid = 1;
2053 return val & 7;
2054}
2055
1da177e4 2056/* The TBR field in an XFX instruction. This is just like SPR, but it
08d96e0b 2057 is optional. */
1da177e4
LT		 2058
2059static unsigned long
2060insert_tbr (unsigned long insn,
2061 long value,
08d96e0b
BS		 2062 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2063 const char **errmsg)
1da177e4 2064{
08d96e0b
BS		 2065 if (value != 268 && value != 269)
2066 *errmsg = _("invalid tbr number");
1da177e4
LT		 2067 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2068}
2069
2070static long
2071extract_tbr (unsigned long insn,
08d96e0b
BS		 2072 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2073 int *invalid)
1da177e4
LT		 2074{
2075 long ret;
2076
2077 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
08d96e0b
BS		 2078 if (ret != 268 && ret != 269)
2079 *invalid = 1;
1da177e4
LT		 2080 return ret;
2081}
08d96e0b
BS		 2082
2083/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2084
2085static unsigned long
2086insert_xt6 (unsigned long insn,
2087 long value,
2088 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2089 const char **errmsg ATTRIBUTE_UNUSED)
2090{
2091 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2092}
2093
2094static long
2095extract_xt6 (unsigned long insn,
2096 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2097 int *invalid ATTRIBUTE_UNUSED)
2098{
2099 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2100}
2101
2102/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2103static unsigned long
2104insert_xtq6 (unsigned long insn,
2105 long value,
2106 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2107 const char **errmsg ATTRIBUTE_UNUSED)
2108{
2109 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2110}
2111
2112static long
2113extract_xtq6 (unsigned long insn,
2114 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2115 int *invalid ATTRIBUTE_UNUSED)
2116{
2117 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2118}
2119
2120/* The XA field in an XX3 form instruction. This is split. */
2121
2122static unsigned long
2123insert_xa6 (unsigned long insn,
2124 long value,
2125 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2126 const char **errmsg ATTRIBUTE_UNUSED)
2127{
2128 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2129}
2130
2131static long
2132extract_xa6 (unsigned long insn,
2133 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2134 int *invalid ATTRIBUTE_UNUSED)
2135{
2136 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2137}
2138
2139/* The XB field in an XX3 form instruction. This is split. */
2140
2141static unsigned long
2142insert_xb6 (unsigned long insn,
2143 long value,
2144 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2145 const char **errmsg ATTRIBUTE_UNUSED)
2146{
2147 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2148}
2149
2150static long
2151extract_xb6 (unsigned long insn,
2152 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2153 int *invalid ATTRIBUTE_UNUSED)
2154{
2155 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2156}
2157
2158/* The XB field in an XX3 form instruction when it must be the same as
2159 the XA field in the instruction. This is used for extended
2160 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2161 function just copies the XA field into the XB field, and the
2162 extraction function just checks that the fields are the same. */
2163
2164static unsigned long
2165insert_xb6s (unsigned long insn,
2166 long value ATTRIBUTE_UNUSED,
2167 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2168 const char **errmsg ATTRIBUTE_UNUSED)
2169{
2170 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2171}
2172
2173static long
2174extract_xb6s (unsigned long insn,
2175 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2176 int *invalid)
2177{
2178 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2179 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2180 *invalid = 1;
2181 return 0;
2182}
2183
2184/* The XC field in an XX4 form instruction. This is split. */
2185
2186static unsigned long
2187insert_xc6 (unsigned long insn,
2188 long value,
2189 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2190 const char **errmsg ATTRIBUTE_UNUSED)
2191{
2192 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2193}
2194
2195static long
2196extract_xc6 (unsigned long insn,
2197 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2198 int *invalid ATTRIBUTE_UNUSED)
2199{
2200 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2201}
2202
2203static unsigned long
2204insert_dm (unsigned long insn,
2205 long value,
2206 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2207 const char **errmsg)
2208{
2209 if (value != 0 && value != 1)
2210 *errmsg = _("invalid constant");
2211 return insn | (((value) ? 3 : 0) << 8);
2212}
2213
2214static long
2215extract_dm (unsigned long insn,
2216 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2217 int *invalid)
2218{
2219 long value;
2220
2221 value = (insn >> 8) & 3;
2222 if (value != 0 && value != 3)
2223 *invalid = 1;
2224 return (value) ? 1 : 0;
2225}
2226
2227/* The VLESIMM field in an I16A form instruction. This is split. */
2228
2229static unsigned long
2230insert_vlesi (unsigned long insn,
2231 long value,
2232 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2233 const char **errmsg ATTRIBUTE_UNUSED)
2234{
2235 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2236}
2237
2238static long
2239extract_vlesi (unsigned long insn,
2240 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2241 int *invalid ATTRIBUTE_UNUSED)
2242{
2243 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2244 value = (value ^ 0x8000) - 0x8000;
2245 return value;
2246}
2247
2248static unsigned long
2249insert_vlensi (unsigned long insn,
2250 long value,
2251 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2252 const char **errmsg ATTRIBUTE_UNUSED)
2253{
2254 value = -value;
2255 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2256}
2257static long
2258extract_vlensi (unsigned long insn,
2259 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2260 int *invalid ATTRIBUTE_UNUSED)
2261{
2262 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2263 value = (value ^ 0x8000) - 0x8000;
2264 /* Don't use for disassembly. */
2265 *invalid = 1;
2266 return -value;
2267}
2268
2269/* The VLEUIMM field in an I16A form instruction. This is split. */
2270
2271static unsigned long
2272insert_vleui (unsigned long insn,
2273 long value,
2274 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2275 const char **errmsg ATTRIBUTE_UNUSED)
2276{
2277 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2278}
2279
2280static long
2281extract_vleui (unsigned long insn,
2282 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2283 int *invalid ATTRIBUTE_UNUSED)
2284{
2285 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2286}
2287
2288/* The VLEUIMML field in an I16L form instruction. This is split. */
2289
2290static unsigned long
2291insert_vleil (unsigned long insn,
2292 long value,
2293 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2294 const char **errmsg ATTRIBUTE_UNUSED)
2295{
2296 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2297}
2298
2299static long
2300extract_vleil (unsigned long insn,
2301 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2302 int *invalid ATTRIBUTE_UNUSED)
2303{
2304 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2305}
2306
1da177e4
LT		 2307\f
2308/* Macros used to form opcodes. */
2309
2310/* The main opcode. */
2311#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2312#define OP_MASK OP (0x3f)
2313
2314/* The main opcode combined with a trap code in the TO field of a D
2315 form instruction. Used for extended mnemonics for the trap
2316 instructions. */
2317#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2318#define OPTO_MASK (OP_MASK | TO_MASK)
2319
2320/* The main opcode combined with a comparison size bit in the L field
2321 of a D form or X form instruction. Used for extended mnemonics for
2322 the comparison instructions. */
2323#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2324#define OPL_MASK OPL (0x3f,1)
2325
08d96e0b
BS		 2326/* The main opcode combined with an update code in D form instruction.
2327 Used for extended mnemonics for VLE memory instructions. */
2328#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2329#define OPVUP_MASK OPVUP (0x3f, 0xff)
2330
2331/* The main opcode combined with an update code and the RT fields specified in
2332 D form instruction. Used for VLE volatile context save/restore
2333 instructions. */
2334#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2335#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2336
1da177e4
LT		 2337/* An A form instruction. */
2338#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2339#define A_MASK A (0x3f, 0x1f, 1)
2340
2341/* An A_MASK with the FRB field fixed. */
2342#define AFRB_MASK (A_MASK | FRB_MASK)
2343
2344/* An A_MASK with the FRC field fixed. */
2345#define AFRC_MASK (A_MASK | FRC_MASK)
2346
2347/* An A_MASK with the FRA and FRC fields fixed. */
2348#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2349
897f112b
ME		 2350/* An AFRAFRC_MASK, but with L bit clear. */
2351#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2352
1da177e4
LT		 2353/* A B form instruction. */
2354#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2355#define B_MASK B (0x3f, 1, 1)
2356
08d96e0b
BS		 2357/* A BD8 form instruction. This is a 16-bit instruction. */
2358#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2359#define BD8_MASK BD8 (0x3f, 1, 1)
2360
2361/* Another BD8 form instruction. This is a 16-bit instruction. */
2362#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2363#define BD8IO_MASK BD8IO (0x1f)
2364
2365/* A BD8 form instruction for simplified mnemonics. */
2366#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2367/* A mask that excludes BO32 and BI32. */
2368#define EBD8IO1_MASK 0xf800
2369/* A mask that includes BO32 and excludes BI32. */
2370#define EBD8IO2_MASK 0xfc00
2371/* A mask that include BO32 AND BI32. */
2372#define EBD8IO3_MASK 0xff00
2373
2374/* A BD15 form instruction. */
2375#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2376#define BD15_MASK BD15 (0x3f, 0xf, 1)
2377
2378/* A BD15 form instruction for extended conditional branch mnemonics. */
2379#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2380#define EBD15_MASK 0xfff00001
2381
2382/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2383#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2384 | (((aa) & 0xf) << 22) \
2385 | (((bo) & 0x3) << 20) \
2386 | (((bi) & 0x3) << 16) \
2387 | ((lk) & 1)
2388#define EBD15BI_MASK 0xfff30001
2389
2390/* A BD24 form instruction. */
2391#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2392#define BD24_MASK BD24 (0x3f, 1, 1)
2393
1da177e4
LT		 2394/* A B form instruction setting the BO field. */
2395#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2396#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2397
2398/* A BBO_MASK with the y bit of the BO field removed. This permits
2399 matching a conditional branch regardless of the setting of the y
2400 bit. Similarly for the 'at' bits used for power4 branch hints. */
08d96e0b 2401#define Y_MASK (((unsigned long) 1) << 21)
1da177e4
LT		 2402#define AT1_MASK (((unsigned long) 3) << 21)
2403#define AT2_MASK (((unsigned long) 9) << 21)
2404#define BBOY_MASK (BBO_MASK &~ Y_MASK)
2405#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2406
2407/* A B form instruction setting the BO field and the condition bits of
2408 the BI field. */
2409#define BBOCB(op, bo, cb, aa, lk) \
2410 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2411#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2412
2413/* A BBOCB_MASK with the y bit of the BO field removed. */
2414#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2415#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2416#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2417
2418/* A BBOYCB_MASK in which the BI field is fixed. */
2419#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2420#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2421
08d96e0b
BS		 2422/* A VLE C form instruction. */
2423#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2424#define C_LK_MASK C_LK(0x7fff, 1)
2425#define C(x) ((((unsigned long)(x)) & 0xffff))
2426#define C_MASK C(0xffff)
2427
1da177e4
LT		 2428/* An Context form instruction. */
2429#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
897f112b 2430#define CTX_MASK CTX(0x3f, 0x7)
1da177e4 2431
9332ef9d 2432/* A User Context form instruction. */
1da177e4 2433#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
897f112b 2434#define UCTX_MASK UCTX(0x3f, 0x1f)
1da177e4
LT		 2435
2436/* The main opcode mask with the RA field clear. */
2437#define DRA_MASK (OP_MASK | RA_MASK)
2438
08d96e0b
BS		 2439/* A DQ form VSX instruction. */
2440#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2441#define DQX_MASK DQX (0x3f, 7)
2442
1da177e4
LT		 2443/* A DS form instruction. */
2444#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2445#define DS_MASK DSO (0x3f, 3)
2446
08d96e0b
BS		 2447/* An DX form instruction. */
2448#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2449#define DX_MASK DX (0x3f, 0x1f)
1da177e4
LT		 2450
2451/* An EVSEL form instruction. */
2452#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2453#define EVSEL_MASK EVSEL(0x3f, 0xff)
2454
08d96e0b
BS		 2455/* An IA16 form instruction. */
2456#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2457#define IA16_MASK IA16(0x3f, 0x1f)
2458
2459/* An I16A form instruction. */
2460#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2461#define I16A_MASK I16A(0x3f, 0x1f)
2462
2463/* An I16L form instruction. */
2464#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2465#define I16L_MASK I16L(0x3f, 0x1f)
2466
2467/* An IM7 form instruction. */
2468#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2469#define IM7_MASK IM7(0x1f)
2470
1da177e4
LT		 2471/* An M form instruction. */
2472#define M(op, rc) (OP (op) | ((rc) & 1))
2473#define M_MASK M (0x3f, 1)
2474
08d96e0b
BS		 2475/* An LI20 form instruction. */
2476#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2477#define LI20_MASK LI20(0x3f, 0x1)
2478
1da177e4
LT		 2479/* An M form instruction with the ME field specified. */
2480#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2481
2482/* An M_MASK with the MB and ME fields fixed. */
2483#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2484
2485/* An M_MASK with the SH and ME fields fixed. */
2486#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2487
2488/* An MD form instruction. */
2489#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2490#define MD_MASK MD (0x3f, 0x7, 1)
2491
2492/* An MD_MASK with the MB field fixed. */
2493#define MDMB_MASK (MD_MASK | MB6_MASK)
2494
2495/* An MD_MASK with the SH field fixed. */
2496#define MDSH_MASK (MD_MASK | SH6_MASK)
2497
2498/* An MDS form instruction. */
2499#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2500#define MDS_MASK MDS (0x3f, 0xf, 1)
2501
2502/* An MDS_MASK with the MB field fixed. */
2503#define MDSMB_MASK (MDS_MASK | MB6_MASK)
2504
2505/* An SC form instruction. */
2506#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2507#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2508
08d96e0b
BS		 2509/* An SCI8 form instruction. */
2510#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2511#define SCI8_MASK SCI8(0x3f, 0x1f)
2512
2513/* An SCI8 form instruction. */
2514#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2515#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2516
2517/* An SD4 form instruction. This is a 16-bit instruction. */
2518#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2519#define SD4_MASK SD4(0xf)
2520
2521/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2522#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2523#define SE_IM5_MASK SE_IM5(0x3f, 1)
2524
2525/* An SE_R form instruction. This is a 16-bit instruction. */
2526#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2527#define SE_R_MASK SE_R(0x3f, 0x3f)
2528
2529/* An SE_RR form instruction. This is a 16-bit instruction. */
2530#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2531#define SE_RR_MASK SE_RR(0x3f, 3)
2532
2533/* A VX form instruction. */
1da177e4
LT		 2534#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2535
2536/* The mask for an VX form instruction. */
2537#define VX_MASK VX(0x3f, 0x7ff)
2538
08d96e0b
BS		 2539/* A VX_MASK with the VA field fixed. */
2540#define VXVA_MASK (VX_MASK | (0x1f << 16))
2541
2542/* A VX_MASK with the VB field fixed. */
2543#define VXVB_MASK (VX_MASK | (0x1f << 11))
2544
2545/* A VX_MASK with the VA and VB fields fixed. */
2546#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2547
2548/* A VX_MASK with the VD and VA fields fixed. */
2549#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2550
2551/* A VX_MASK with a UIMM4 field. */
2552#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2553
2554/* A VX_MASK with a UIMM3 field. */
2555#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2556
2557/* A VX_MASK with a UIMM2 field. */
2558#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2559
2560/* A VX_MASK with a PS field. */
2561#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2562
2563/* A VX_MASK with the VA field fixed with a PS field. */
2564#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2565
2566/* A VA form instruction. */
1da177e4
LT		 2567#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2568
2569/* The mask for an VA form instruction. */
2570#define VXA_MASK VXA(0x3f, 0x3f)
2571
08d96e0b
BS		 2572/* A VXA_MASK with a SHB field. */
2573#define VXASHB_MASK (VXA_MASK | (1 << 10))
2574
2575/* A VXR form instruction. */
1da177e4
LT		 2576#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2577
2578/* The mask for a VXR form instruction. */
2579#define VXR_MASK VXR(0x3f, 0x3ff, 1)
2580
08d96e0b
BS		 2581/* A VX form instruction with a VA tertiary opcode. */
2582#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2583
2584#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2585#define VXASH_MASK VXASH (0x3f, 0x1f)
2586
1da177e4
LT		 2587/* An X form instruction. */
2588#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2589
08d96e0b
BS		 2590/* A X form instruction for Quad-Precision FP Instructions. */
2591#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2592
2593/* An EX form instruction. */
2594#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2595
2596/* The mask for an EX form instruction. */
2597#define EX_MASK EX (0x3f, 0x7ff)
2598
2599/* An XX2 form instruction. */
2600#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2601
2602/* A XX2 form instruction with the VA bits specified. */
2603#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2604
2605/* An XX3 form instruction. */
2606#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2607
2608/* An XX3 form instruction with the RC bit specified. */
2609#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2610
2611/* An XX4 form instruction. */
2612#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2613
897f112b
ME		 2614/* A Z form instruction. */
2615#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2616
1da177e4
LT		 2617/* An X form instruction with the RC bit specified. */
2618#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2619
08d96e0b
BS		 2620/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2621#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2622
2623/* An X form instruction with the RA bits specified as two ops. */
2624#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2625
897f112b
ME		 2626/* A Z form instruction with the RC bit specified. */
2627#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2628
1da177e4
LT		 2629/* The mask for an X form instruction. */
2630#define X_MASK XRC (0x3f, 0x3ff, 1)
2631
08d96e0b
BS		 2632/* The mask for an X form instruction with the BF bits specified. */
2633#define XBF_MASK (X_MASK | (3 << 21))
2634
2635/* An X form wait instruction with everything filled in except the WC field. */
2636#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2637
2638/* The mask for an XX1 form instruction. */
2639#define XX1_MASK X (0x3f, 0x3ff)
2640
2641/* An XX1_MASK with the RB field fixed. */
2642#define XX1RB_MASK (XX1_MASK | RB_MASK)
2643
2644/* The mask for an XX2 form instruction. */
2645#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2646
2647/* The mask for an XX2 form instruction with the UIM bits specified. */
2648#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2649
2650/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2651#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2652
2653/* The mask for an XX2 form instruction with the BF bits specified. */
2654#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2655
2656/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2657#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2658
2659/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2660#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2661
2662/* The mask for an XX3 form instruction. */
2663#define XX3_MASK XX3 (0x3f, 0xff)
2664
2665/* The mask for an XX3 form instruction with the BF bits specified. */
2666#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2667
2668/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2669#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2670#define XX3SHW_MASK XX3DM_MASK
2671
2672/* The mask for an XX4 form instruction. */
2673#define XX4_MASK XX4 (0x3f, 0x3)
2674
2675/* An X form wait instruction with everything filled in except the WC field. */
2676#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2677
2678/* The mask for an XMMF form instruction. */
2679#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2680
897f112b
ME		 2681/* The mask for a Z form instruction. */
2682#define Z_MASK ZRC (0x3f, 0x1ff, 1)
cc7639ce 2683#define Z2_MASK ZRC (0x3f, 0xff, 1)
897f112b 2684
08d96e0b 2685/* An X_MASK with the RA/VA field fixed. */
1da177e4 2686#define XRA_MASK (X_MASK | RA_MASK)
08d96e0b 2687#define XVA_MASK XRA_MASK
1da177e4 2688
08d96e0b 2689/* An XRA_MASK with the A_L/W field clear. */
cc7639ce 2690#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
08d96e0b 2691#define XRLA_MASK XWRA_MASK
1da177e4
LT		 2692
2693/* An X_MASK with the RB field fixed. */
2694#define XRB_MASK (X_MASK | RB_MASK)
2695
2696/* An X_MASK with the RT field fixed. */
2697#define XRT_MASK (X_MASK | RT_MASK)
2698
897f112b
ME		 2699/* An XRT_MASK mask with the L bits clear. */
2700#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2701
1da177e4
LT		 2702/* An X_MASK with the RA and RB fields fixed. */
2703#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2704
08d96e0b
BS		 2705/* An XBF_MASK with the RA and RB fields fixed. */
2706#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2707
1da177e4
LT		 2708/* An XRARB_MASK, but with the L bit clear. */
2709#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2710
08d96e0b
BS		 2711/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2712#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2713
1da177e4
LT		 2714/* An X_MASK with the RT and RA fields fixed. */
2715#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2716
08d96e0b
BS		 2717/* An X_MASK with the RT and RB fields fixed. */
2718#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2719
1da177e4
LT		 2720/* An XRTRA_MASK, but with L bit clear. */
2721#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2722
08d96e0b
BS		 2723/* An X_MASK with the RT, RA and RB fields fixed. */
2724#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2725
2726/* An XRTRARB_MASK, but with L bit clear. */
2727#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2728
2729/* An XRTRARB_MASK, but with A bit clear. */
2730#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2731
2732/* An XRTRARB_MASK, but with BF bits clear. */
2733#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2734
897f112b
ME		 2735/* An X form instruction with the L bit specified. */
2736#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1da177e4 2737
08d96e0b
BS		 2738/* An X form instruction with the L bits specified. */
2739#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2740
2741/* An X form instruction with the L bit and RC bit specified. */
2742#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2743
2744/* An X form instruction with RT fields specified */
2745#define XRT(op, xop, rt) (X ((op), (xop)) \
2746 | ((((unsigned long)(rt)) & 0x1f) << 21))
2747
2748/* An X form instruction with RT and RA fields specified */
2749#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2750 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2751 | ((((unsigned long)(ra)) & 0x1f) << 16))
2752
1da177e4
LT		 2753/* The mask for an X form comparison instruction. */
2754#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2755
2756/* The mask for an X form comparison instruction with the L field
2757 fixed. */
2758#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2759
2760/* An X form trap instruction with the TO field specified. */
2761#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2762#define XTO_MASK (X_MASK | TO_MASK)
2763
2764/* An X form tlb instruction with the SH field specified. */
2765#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2766#define XTLB_MASK (X_MASK | SH_MASK)
2767
2768/* An X form sync instruction. */
2769#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2770
2771/* An X form sync instruction with everything filled in except the LS field. */
2772#define XSYNC_MASK (0xff9fffff)
2773
08d96e0b
BS		 2774/* An X form sync instruction with everything filled in except the L and E fields. */
2775#define XSYNCLE_MASK (0xff90ffff)
2776
897f112b
ME		 2777/* An X_MASK, but with the EH bit clear. */
2778#define XEH_MASK (X_MASK & ~((unsigned long )1))
2779
1da177e4
LT		 2780/* An X form AltiVec dss instruction. */
2781#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2782#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2783
2784/* An XFL form instruction. */
2785#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
cc7639ce 2786#define XFL_MASK XFL (0x3f, 0x3ff, 1)
1da177e4
LT		 2787
2788/* An X form isel instruction. */
08d96e0b
BS		 2789#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2790#define XISEL_MASK XISEL(0x3f, 0x1f)
1da177e4
LT		 2791
2792/* An XL form instruction with the LK field set to 0. */
2793#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2794
2795/* An XL form instruction which uses the LK field. */
2796#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2797
2798/* The mask for an XL form instruction. */
2799#define XL_MASK XLLK (0x3f, 0x3ff, 1)
2800
08d96e0b
BS		 2801/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2802#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2803
1da177e4
LT		 2804/* An XL form instruction which explicitly sets the BO field. */
2805#define XLO(op, bo, xop, lk) \
2806 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2807#define XLO_MASK (XL_MASK | BO_MASK)
2808
2809/* An XL form instruction which explicitly sets the y bit of the BO
2810 field. */
2811#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2812#define XLYLK_MASK (XL_MASK | Y_MASK)
2813
2814/* An XL form instruction which sets the BO field and the condition
2815 bits of the BI field. */
2816#define XLOCB(op, bo, cb, xop, lk) \
2817 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2818#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2819
2820/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2821#define XLBB_MASK (XL_MASK | BB_MASK)
2822#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2823#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2824
897f112b
ME		 2825/* A mask for branch instructions using the BH field. */
2826#define XLBH_MASK (XL_MASK | (0x1c << 11))
2827
1da177e4
LT		 2828/* An XL_MASK with the BO and BB fields fixed. */
2829#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2830
2831/* An XL_MASK with the BO, BI and BB fields fixed. */
2832#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2833
08d96e0b
BS		 2834/* An X form mbar instruction with MO field. */
2835#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2836
1da177e4
LT		 2837/* An XO form instruction. */
2838#define XO(op, xop, oe, rc) \
2839 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2840#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2841
2842/* An XO_MASK with the RB field fixed. */
2843#define XORB_MASK (XO_MASK | RB_MASK)
2844
08d96e0b
BS		 2845/* An XOPS form instruction for paired singles. */
2846#define XOPS(op, xop, rc) \
2847 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2848#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2849
2850
1da177e4
LT		 2851/* An XS form instruction. */
2852#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2853#define XS_MASK XS (0x3f, 0x1ff, 1)
2854
2855/* A mask for the FXM version of an XFX form instruction. */
897f112b 2856#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1da177e4
LT		 2857
2858/* An XFX form instruction with the FXM field filled in. */
897f112b
ME		 2859#define XFXM(op, xop, fxm, p4) \
2860 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2861 | ((unsigned long)(p4) << 20))
1da177e4
LT		 2862
2863/* An XFX form instruction with the SPR field filled in. */
2864#define XSPR(op, xop, spr) \
2865 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2866#define XSPR_MASK (X_MASK | SPR_MASK)
2867
2868/* An XFX form instruction with the SPR field filled in except for the
2869 SPRBAT field. */
2870#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2871
2872/* An XFX form instruction with the SPR field filled in except for the
2873 SPRG field. */
cc7639ce 2874#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1da177e4
LT		 2875
2876/* An X form instruction with everything filled in except the E field. */
2877#define XE_MASK (0xffff7fff)
2878
2879/* An X form user context instruction. */
2880#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2881#define XUC_MASK XUC(0x3f, 0x1f)
2882
08d96e0b
BS		 2883/* An XW form instruction. */
2884#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2885/* The mask for a G form instruction. rc not supported at present. */
2886#define XW_MASK XW (0x3f, 0x3f, 0)
2887
2888/* An APU form instruction. */
2889#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2890
2891/* The mask for an APU form instruction. */
2892#define APU_MASK APU (0x3f, 0x3ff, 1)
2893#define APU_RT_MASK (APU_MASK | RT_MASK)
2894#define APU_RA_MASK (APU_MASK | RA_MASK)
2895
1da177e4
LT		 2896/* The BO encodings used in extended conditional branch mnemonics. */
2897#define BODNZF (0x0)
2898#define BODNZFP (0x1)
2899#define BODZF (0x2)
2900#define BODZFP (0x3)
2901#define BODNZT (0x8)
2902#define BODNZTP (0x9)
2903#define BODZT (0xa)
2904#define BODZTP (0xb)
2905
2906#define BOF (0x4)
2907#define BOFP (0x5)
2908#define BOFM4 (0x6)
2909#define BOFP4 (0x7)
2910#define BOT (0xc)
2911#define BOTP (0xd)
2912#define BOTM4 (0xe)
2913#define BOTP4 (0xf)
2914
2915#define BODNZ (0x10)
2916#define BODNZP (0x11)
2917#define BODZ (0x12)
2918#define BODZP (0x13)
2919#define BODNZM4 (0x18)
2920#define BODNZP4 (0x19)
2921#define BODZM4 (0x1a)
2922#define BODZP4 (0x1b)
2923
2924#define BOU (0x14)
2925
08d96e0b
BS		 2926/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2927#define BO16F (0x0)
2928#define BO16T (0x1)
2929
2930/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2931#define BO32F (0x0)
2932#define BO32T (0x1)
2933#define BO32DNZ (0x2)
2934#define BO32DZ (0x3)
2935
1da177e4
LT		 2936/* The BI condition bit encodings used in extended conditional branch
2937 mnemonics. */
2938#define CBLT (0)
2939#define CBGT (1)
2940#define CBEQ (2)
2941#define CBSO (3)
2942
2943/* The TO encodings used in extended trap mnemonics. */
2944#define TOLGT (0x1)
2945#define TOLLT (0x2)
2946#define TOEQ (0x4)
2947#define TOLGE (0x5)
2948#define TOLNL (0x5)
2949#define TOLLE (0x6)
2950#define TOLNG (0x6)
2951#define TOGT (0x8)
2952#define TOGE (0xc)
2953#define TONL (0xc)
2954#define TOLT (0x10)
2955#define TOLE (0x14)
2956#define TONG (0x14)
2957#define TONE (0x18)
2958#define TOU (0x1f)
2959\f
2960/* Smaller names for the flags so each entry in the opcodes table will
2961 fit on a single line. */
2962#undef PPC
08d96e0b 2963#define PPC PPC_OPCODE_PPC
1da177e4 2964#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1da177e4 2965#define POWER4 PPC_OPCODE_POWER4
897f112b
ME		 2966#define POWER5 PPC_OPCODE_POWER5
2967#define POWER6 PPC_OPCODE_POWER6
08d96e0b
BS		 2968#define POWER7 PPC_OPCODE_POWER7
2969#define POWER8 PPC_OPCODE_POWER8
2970#define POWER9 PPC_OPCODE_POWER9
897f112b 2971#define CELL PPC_OPCODE_CELL
08d96e0b
BS		 2972#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2973#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2974 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1da177e4 2975#define PPC403 PPC_OPCODE_403
08d96e0b 2976#define PPC405 PPC_OPCODE_405
1da177e4 2977#define PPC440 PPC_OPCODE_440
08d96e0b
BS		 2978#define PPC464 PPC440
2979#define PPC476 PPC_OPCODE_476
2980#define PPC750 PPC_OPCODE_750
2981#define PPC7450 PPC_OPCODE_7450
2982#define PPC860 PPC_OPCODE_860
2983#define PPCPS PPC_OPCODE_PPCPS
897f112b 2984#define PPCVEC PPC_OPCODE_ALTIVEC
08d96e0b
BS		 2985#define PPCVEC2 PPC_OPCODE_ALTIVEC2
2986#define PPCVEC3 PPC_OPCODE_ALTIVEC2
2987#define PPCVSX PPC_OPCODE_VSX
2988#define PPCVSX2 PPC_OPCODE_VSX
2989#define PPCVSX3 PPC_OPCODE_VSX3
2990#define POWER PPC_OPCODE_POWER
2991#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2992#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2993#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2994#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2995#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1da177e4 2996#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
08d96e0b
BS		 2997#define MFDEC1 PPC_OPCODE_POWER
2998#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
1da177e4 2999#define BOOKE PPC_OPCODE_BOOKE
08d96e0b 3000#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
897f112b 3001#define PPCE300 PPC_OPCODE_E300
1da177e4 3002#define PPCSPE PPC_OPCODE_SPE
08d96e0b 3003#define PPCISEL PPC_OPCODE_ISEL
1da177e4 3004#define PPCEFS PPC_OPCODE_EFS
08d96e0b 3005#define PPCBRLK PPC_OPCODE_BRLOCK
1da177e4 3006#define PPCPMR PPC_OPCODE_PMR
08d96e0b
BS		 3007#define PPCTMR PPC_OPCODE_TMR
3008#define PPCCHLK PPC_OPCODE_CACHELCK
1da177e4 3009#define PPCRFMCI PPC_OPCODE_RFMCI
08d96e0b
BS		 3010#define E500MC PPC_OPCODE_E500MC
3011#define PPCA2 PPC_OPCODE_A2
3012#define TITAN PPC_OPCODE_TITAN
3013#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
3014#define E500 PPC_OPCODE_E500
3015#define E6500 PPC_OPCODE_E6500
3016#define PPCVLE PPC_OPCODE_VLE
3017#define PPCHTM PPC_OPCODE_HTM
3018#define E200Z4 PPC_OPCODE_E200Z4
3019/* The list of embedded processors that use the embedded operand ordering
3020 for the 3 operand dcbt and dcbtst instructions. */
3021#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3022 | PPC_OPCODE_A2)
3023
3024
1da177e4
LT		 3025\f
3026/* The opcode table.
3027
3028 The format of the opcode table is:
3029
08d96e0b 3030 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
1da177e4
LT		 3031
3032 NAME is the name of the instruction.
3033 OPCODE is the instruction opcode.
3034 MASK is the opcode mask; this is used to tell the disassembler
3035 which bits in the actual opcode must match OPCODE.
08d96e0b
BS		 3036 FLAGS are flags indicating which processors support the instruction.
3037 ANTI indicates which processors don't support the instruction.
1da177e4
LT		 3038 OPERANDS is the list of operands.
3039
3040 The disassembler reads the table in order and prints the first
3041 instruction which matches, so this table is sorted to put more
08d96e0b
BS		 3042 specific instructions before more general instructions.
3043
3044 This table must be sorted by major opcode. Please try to keep it
3045 vaguely sorted within major opcode too, except of course where
3046 constrained otherwise by disassembler operation. */
1da177e4
LT		 3047
3048const struct powerpc_opcode powerpc_opcodes[] = {
08d96e0b
BS		 3049{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3050{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3051{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3052{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3053{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3054{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3055{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3056{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3057{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3058{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3059{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3060{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3061{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3062{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3063{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3064{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3065{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3066
3067{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3068{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3069{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3070{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3071{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3072{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3073{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3074{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3075{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3076{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3077{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3078{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3079{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3080{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3081{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3082{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3083{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3084{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3085{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3086{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3087{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3088{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3089{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3090{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3091{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3092{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3093{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3094{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3095{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3096{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3097{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3098{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3099
3100{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3101{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3102{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3103{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3104{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3105{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3106{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3107{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3108{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3109{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3110{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3111{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3112{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3113{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3114{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3115{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3116{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3117{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3118{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3119{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3120{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3121{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3122{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3123{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3124{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3125{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3126{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3127{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3128{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3129{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3130{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3131{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3132{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3133{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3134{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3135{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3136{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3137{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3138{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3139{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3140{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3141{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3142{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3143{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3144{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3145{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3146{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3147{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3148{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3149{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3150{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3151{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3152{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3153{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3154{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3155{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3156{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3157{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3158{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3159{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3160{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3161{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3162{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3163{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3164{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3165{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3166{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3167{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3168{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3169{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3170{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3171{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3172{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3173{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3174{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3175{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3176{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3177{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3178{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3179{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3180{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3181{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3182{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3183{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3184{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3185{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3186{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3187{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3188{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3189{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3190{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3191{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3192{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3193{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3194{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3195{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3196{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3197{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3198{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3199{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3200{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3201{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3202{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3203{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3204{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3205{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3206{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3207{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3208{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3209{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3210{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3211{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3212{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3213{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3214{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3215{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3216{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3217{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3218{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3219{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3220{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3221{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3222{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3223{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3224{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3225{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3226{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3227{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3228{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3229{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3230{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3231{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3232{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3233{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3234{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3235{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3236{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3237{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3238{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3239{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3240{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3241{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3242{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3243{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3244{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3245{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3246{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3247{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3248{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3249{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3250{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3251{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3252{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3253{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3254{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3255{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3256{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3257{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3258{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3259{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3260{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3261{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3262{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3263{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3264{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3265{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3266{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3267{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3268{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3269{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3270{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3271{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3272{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3273{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3274{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3275{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3276{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3277{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3278{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3279{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3280{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3281{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3282{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3283{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3284{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3285{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3286{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3287{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3288{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3289{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3290{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3291{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3292{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3293{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3294{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3295{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3296{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3297{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3298{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3299{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3300{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3301{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3302{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3303{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3304{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3305{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3306{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3307{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3308{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3309{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3310{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3311{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3312{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3313{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3314{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3315{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3316{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3317{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3318{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3319{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3320{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3321{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3322{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3323{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3324{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3325{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3326{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3327{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3328{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3329{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3330{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3331{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3332{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3333{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3334{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3335{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3336{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3337{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3338{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3339{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3340{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3341{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3342{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3343{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3344{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3345{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3346{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3347{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3348{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3349{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3350{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3351{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3352{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3353{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3354{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3355{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3356{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3357{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3358{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3359{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3360{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3361{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3362{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3363{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3364{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3365{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3366{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3367{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3368{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3369{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3370{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3371{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3372{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3373{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3374{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3375{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3376{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3377{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3378{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3379{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3380{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3381{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3382{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3383{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3384{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3385{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3386{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3387{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3388{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3389{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3390{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3391{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3392{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3393{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3394{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3395{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3396{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3397{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3398{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3399{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3400{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3401{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3402{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3403{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3404{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3405{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3406{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3407{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3408{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3409{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3410{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3411{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3412{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3413{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3414{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3415{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3416{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3417{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3418{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3419{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3420{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3421{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3422{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3423{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3424{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3425{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3426{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3427{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3428{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3429{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3430{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3431{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3432{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3433{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3434{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3435{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3436{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3437{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3438{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3439{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3440{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3441{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3442{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3443{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3444{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3445{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3446{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3447{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3448{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3449{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3450{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3451{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3452{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3453{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3454{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3455{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3456{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3457{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3458{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3459{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3460{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3461{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3462{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3463{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3464{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3465{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3466{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3467{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3468{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3469{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3470{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3471{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3472{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3473{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3474{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3475{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3476{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3477{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3478{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3479{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3480{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3481{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3482{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3483{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3484{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3485{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3486{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3487{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3488{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3489{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3490{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3491{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3492{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3493{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3494{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3495{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3496{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3497{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3498{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3499{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3500{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3501{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3502{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3503{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3504{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3505{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3506{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3507{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3508{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3509{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3510{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3511{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3512{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3513{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3514{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3515{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3516{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3517{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3518{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3519{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3520{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3521{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3522{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3523{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3524{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3525{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3526{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3527{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3528{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3529{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3530{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3531{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3532{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3533{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3534{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3535{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3536{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3537{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3538{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3539{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3540{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3541{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3542{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3543{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3544{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3545{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3546{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3547{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3548{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3549{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3550{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3551{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3552{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3553{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3554{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3555{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3556{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3557{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3558{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3559{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3560{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3561{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3562{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3563{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3564{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3565{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3566{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3567{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3568{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3569{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3570{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3571{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3572{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3573{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3574{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3575{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3576{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3577{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3578{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3579{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3580{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3581{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3582{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3583{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3584{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3585{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3586{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3587{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3588{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3589{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3590{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3591{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3592{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3593{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3594{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3595{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3596{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3597{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3598{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3599{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3600{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3601{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3602{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3603{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3604{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3605{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3606{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3607{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3608{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3609{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3610{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3611{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3612{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3613{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3614{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3615{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3616{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3617{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3618{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3619{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3620{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3621{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3622{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3623{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3624{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3625{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3626{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3627{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3628{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3629{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3630{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3631{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3632{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3633{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3634{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3635{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3636{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3637{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3638{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3639{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3640{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3641{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3642{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3643{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3644{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3645{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3646{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3647{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3648{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3649{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3650{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3651{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3653{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3654{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3655{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3656{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3657{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3658{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3659{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3660{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3661{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3662{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3663{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3664{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3665{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3666{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3667{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3668{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3669{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3670{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3671{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3672{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3673{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3674{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3675{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3676{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3677{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3678{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3679{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3680{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3681{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3682{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3683{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3684{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3685{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3686{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3687{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3688{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3689{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3690{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3691{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3692{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3693{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3694{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3695{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3696{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3697{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3698{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3699{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3700{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3701{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3702{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3703{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3704{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3705{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3706{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3707{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3708{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3709{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3710{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3711{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3712{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3713{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3714{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3715{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3716{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3717{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3718{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3719{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3720{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3721{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3722{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3723{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3724{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3725{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3726{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3727{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3728{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3729{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3730{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3731{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3732{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3733{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3734{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3735{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3736{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3737{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3738{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3739{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3740{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3741{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3742{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3743{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3744{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3745{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3746{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3747{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3748{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3749{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3750{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3751{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3752{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3753{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3754{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3755{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3756{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3757{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3758{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3759{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3760{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3761{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3762{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3763{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3764{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3765{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3766{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3767{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3768{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3769{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3770{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3771{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3772{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3773{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3774{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3775{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3776{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3777{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3778{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3779{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3780{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3781{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3782{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3783{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3784{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3785{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3786{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3787{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3788{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3789{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3790{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3791{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3792{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3793{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3794{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3795{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3796{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3797{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3798{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3799{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3800{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3801{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3802{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3803{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3804{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3805{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3806{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3807{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3808{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3809{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3810{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3811{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3812{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3813{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3814{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3815{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3816{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3817{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3818{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3819{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3820{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3821{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3822{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3823{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3824{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3825{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3826{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3827{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3828{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3829{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3830{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3831{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3832{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3833{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3834{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3835{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3836
3837{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3838{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3839
3840{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3841{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3842
3843{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3844
3845{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3846{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
3847{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
3848{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3849
3850{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3851{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
3852{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
3853{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3854
3855{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3856{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3857{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3858
3859{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3860{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3861{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3862
3863{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3864{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3865{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3866{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3867{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3868{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3869
3870{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3871{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3872{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3873{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3874{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3875
3876{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3877{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3878{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3879{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3880{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3881{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3882{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3883{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3884{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3885{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3886{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3887{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3888{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3889{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3890{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3891{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3892{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3893{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3894{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
3895{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3896{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3897{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
3898{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3899{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3900{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3901{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3902{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3903{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3904
3905{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3906{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3907{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3908{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3909{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3910{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3911{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3912{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3913{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3914{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3915{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3916{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3917{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3918{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3919{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3920{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3921{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3922{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3923{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3924{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3925{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3926{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3927{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3928{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3929{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3930{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3931{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3932{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3933{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3934{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3935{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3936{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3937{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3938{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3939{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3940{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3941{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3942{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3943{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3944{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3945{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3946{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3947{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3948{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3949{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3950{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3951{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3952{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3953{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3954{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3955{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3956{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3957{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3958{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3959{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3960{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3961{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3962{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3963{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3964{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3965{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3966{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3967{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3968{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3969{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3970{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3971{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3972{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3973{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3974{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3975{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3976{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3977{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3978{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3979{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3980{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3981{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3982{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
3983{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3984{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3985{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3986{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3987{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3988{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
3989
3990{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3991{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3992{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3993{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3994{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3995{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3996{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3997{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3998{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3999{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4000{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4001{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4002{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4003{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4004{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4005{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4006{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4007{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4008{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4009{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4010{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4011{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4012{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4013{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4014{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4015{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4016{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4017{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4018{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4019{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4020{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4021{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4022{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4023{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4024{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4025{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4026{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4027{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4028{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4029{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4030{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4031{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4032{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4033{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4034{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4035{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4036{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4037{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4038{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4039{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4040{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4041{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4042{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4043{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4044{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4045{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4046{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4047{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4048{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4049{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4050
4051{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4052{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4053{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4054{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4055{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4056{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4057{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4058{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4059{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4060{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4061{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4062{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4063{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4064{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4065{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4066{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4067{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4068{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4069{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4070{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4071{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4072{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4073{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4074{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4075
4076{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4077{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4078{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4079{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4080{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4081{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4082{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4083{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4084{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4085{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4086{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4087{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4088{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4089{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4090{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4091{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4092
4093{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4094{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4095{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4096{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4097{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4098{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4099{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4100{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4101{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4102{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4103{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4104{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4105{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4106{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4107{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4108{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4109{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4110{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4111{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4112{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4113{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4114{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4115{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4116{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4117
4118{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4119{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4120{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4121{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4122{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4123{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4124{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4125{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4126{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4127{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4128{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4129{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4130{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4131{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4132{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4133{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4134
4135{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4136{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4137{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4138{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4139{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4140{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4141{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4142{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4143{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4144{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4145{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4146{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4147
4148{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4149{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4150{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4151{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4152{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4153
4154{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4155{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4156{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4157{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4158
4159{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4160
4161{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4162{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4163
4164{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4165{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4166{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4167{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4168{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4169{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4170{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4171{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4172{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4173{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4174{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4175{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4176{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4177{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4178{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4179{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4180{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4181{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4182{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4183{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4184{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4185{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4186{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4187{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4188
4189{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4190{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4191{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4192{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4193{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4194{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4195{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4196{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4197{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4198{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4199{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4200{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4201{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4202{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4203{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4204{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4205{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4206{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4207{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4208{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4209{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4210{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4211{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4212{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4213{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4214{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4215{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4216{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4217{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4218{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4219{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4220{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4221{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4222{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4223{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4224{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4225{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4226{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4227{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4228{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4229{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4230{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4231{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4232{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4233{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4234{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4235{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4236{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4237{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4238{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4239{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4240{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4241{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4242{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4243{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4244{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4245{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4246{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4247{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4248{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4249{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4250{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4251{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4252{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4253{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4254{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4255{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4256{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4257{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4258{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4259{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4260{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4261{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4262{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4263{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4264{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4265{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4266{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4267{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4268{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4269{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4270{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4271{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4272{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4273{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4274{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4275{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4276{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4277{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4278{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4279{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4280{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4281{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4282{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4283{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4284{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4285{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4286{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4287{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4288{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4289{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4290{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4291{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4292{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4293{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4294{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4295{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4296{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4297{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4298{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4299{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4300{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4301{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4302{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4303{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4304{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4305{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4306{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4307{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4308{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4309{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4310{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4311{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4312{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4313{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4314{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4315{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4316{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4317{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4318{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4319{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4320{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4321{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4322{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4323{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4324{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4325{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4326{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4327{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4328{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4329
4330{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4331{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4332{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4333{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4334{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4335{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4336{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4337{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4338{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4339{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4340{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4341{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4342{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4343{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4344{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4345{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4346{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4347{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4348{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4349{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4350{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4351{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4352{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4353{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4354{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4355{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4356{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4357{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4358{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4359{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4360{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4361{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4362{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4363{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4364{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4365{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4366{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4367{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4368{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4369{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4370{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4371{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4372{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4373{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4374{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4375{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4376{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4377{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4378
4379{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4380{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4381{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4382{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4383{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4384{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4385{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4386{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4387
4388{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4389
4390{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4391{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4392{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4393
4394{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4395{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4396{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4397
4398{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4399
4400{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4401
4402{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4403
4404{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4405
4406{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4407{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4408
4409{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4410{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4411
4412{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4413
4414{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4415
4416{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4417
4418{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4419
4420{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4421{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4422
4423{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4424{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4425
4426{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4427
4428{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4429
4430{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4431
4432{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4433{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4434
4435{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4436{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4437
4438{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4439{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4440
4441{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4442{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4443{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4444{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4445{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4446{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4447{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4448{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4449{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4450{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4451{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4452{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4453{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4454{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4455{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4456{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4457{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4458{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4459{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4460{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4461{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4462{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4463{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4464{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4465{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4466{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4467{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4468{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4469{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4470{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4471{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4472{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4473{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4474{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4475{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4476{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4477{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4478{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4479{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4480{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4481{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4482{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4483{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4484{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4485{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4486{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4487{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4488{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4489{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4490{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4491{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4492{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4493{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4494{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4495{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4496{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4497{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4498{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4499{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4500{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4501{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4502{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4503{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4504{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4505{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4506{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4507{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4508{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4509{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4510{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4511{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4512{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4513{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4514{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4515{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4516{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4517{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4518{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4519{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4520{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4521{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4522{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4523{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4524{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4525{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4526{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4527{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4528{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4529{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4530{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4531{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4532{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4533{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4534{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4535{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4536{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4537{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4538{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4539{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4540{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4541{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4542{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4543{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4544{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4545{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4546{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4547{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4548{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4549{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4550{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4551{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4552{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4553{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4554{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4556{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4557{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4558{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4559{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4560{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4561
4562{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4563{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4564{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4565{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4566{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4567{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4568{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4569{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4570{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4571{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4572{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4573{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4574{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4575{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4576{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4577{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4578{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4579{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4580{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4581{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4582
4583{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4584{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4585{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4586{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4587{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4588{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4589{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4590{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4591
4592{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4593{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4594{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4595{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4596{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4597{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4598
4599{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4600{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4601
4602{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4603{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4604
4605{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4606{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4607{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4608{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4609{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4610{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4611{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4612{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4613
4614{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4615{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4616
4617{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4618{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4619{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4620{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4621{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4622{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4623
4624{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4625{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4626{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4627
4628{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4629{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4630
4631{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4632{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4633{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4634
4635{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4636{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4637
4638{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4639{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4640
4641{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4642{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4643
4644{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4645{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4646{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4647{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4648{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4649{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4650
4651{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4652{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4653
4654{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4655{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4656
4657{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4658{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4659
4660{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4661{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4662{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4663{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4664
4665{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4666{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4667
4668{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4669{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4670{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4671{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4672
4673{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4674{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4675{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4676{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4677{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4678{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4679{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4680{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4681{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4682{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4683{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4684{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4685{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4686{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4687{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4688{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4689{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4690{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4691{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4692{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4694{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4695{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4696{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4697{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4698{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4699{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4700{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4701{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4702{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4703{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4704{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4705{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4706
4707{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4708{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4709{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4710
4711{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4712{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4713{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4714{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4715{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4716{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4717
4718{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4719{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4720
4721{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4722{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4723{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4724{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4725
4726{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4727{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4728
4729{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4730
4731{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4732
4733{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4734{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4735{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4736{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4737
4738{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4739{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4740
4741{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4742
4743{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4744
4745{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4746
4747{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4748{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4749
4750{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4751{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4752{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4753{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4754
4755{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4756{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4757{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4758{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4759
4760{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4761{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4762
4763{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4764{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4765
4766{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4767{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4768
4769{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4770
4771{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4772{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4773
4774{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4775
4776{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4777{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4778{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4779{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4780
4781{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4782{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4783{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4784
4785{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4786
4787{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4788
4789{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4790
4791{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4792
4793{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4794
4795{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4796
4797{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4798
4799{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4800{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4801{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4802{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4803
4804{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4805{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4806{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4807{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4808
4809{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4810
4811{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4812
4813{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4814
4815{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4816{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4817
4818{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4819{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4820
4821{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4822{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4823
4824{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4825{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4826{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4827
4828{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4829
4830{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4831{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4832{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4833{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4834{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4835{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4836{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4837{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4838{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4839{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4840{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4841{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4842{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4843{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4844{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4845{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4846
4847{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4848{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4849{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4850
4851{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4852{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4853
4854{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4855{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4856
4857{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4858
4859{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4860
4861{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4862
4863{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4864{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
4865
4866{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
1da177e4 4867
08d96e0b 4868{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1da177e4 4869
08d96e0b 4870{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
1da177e4 4871
08d96e0b
BS		 4872{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4873{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 4874
08d96e0b
BS		 4875{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4876{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
1da177e4 4877
08d96e0b
BS		 4878{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4879{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1da177e4 4880
08d96e0b 4881{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
1da177e4 4882
08d96e0b 4883{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
1da177e4 4884
08d96e0b
BS		 4885{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4886{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4887{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
1da177e4 4888
08d96e0b 4889{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
1da177e4 4890
08d96e0b 4891{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
1da177e4 4892
08d96e0b 4893{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
1da177e4 4894
08d96e0b 4895{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
1da177e4 4896
08d96e0b
BS		 4897{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4898{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4899{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4900{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
1da177e4 4901
08d96e0b 4902{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
1da177e4 4903
08d96e0b 4904{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
1da177e4 4905
08d96e0b 4906{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
1da177e4 4907
08d96e0b 4908{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
1da177e4 4909
08d96e0b
BS		 4910{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4911{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 4912
08d96e0b
BS		 4913{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4914{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4915{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4916{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 4917
08d96e0b
BS		 4918{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4919{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4920{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4921{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 4922
08d96e0b 4923{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
1da177e4 4924
08d96e0b
BS		 4925{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4926{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
1da177e4 4927
08d96e0b
BS		 4928{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4929{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4930{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
1da177e4 4931
08d96e0b 4932{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
897f112b 4933
08d96e0b 4934{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
1da177e4 4935
08d96e0b
BS		 4936{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4937{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
1da177e4 4938
08d96e0b 4939{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
1da177e4 4940
08d96e0b 4941{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
1da177e4 4942
08d96e0b
BS		 4943{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4944{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
1da177e4 4945
08d96e0b
BS		 4946{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4947{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 4948
08d96e0b
BS		 4949{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4950{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 4951
08d96e0b 4952{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
1da177e4 4953
08d96e0b 4954{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1da177e4 4955
08d96e0b 4956{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1da177e4 4957
08d96e0b 4958{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
1da177e4 4959
08d96e0b 4960{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
1da177e4 4961
08d96e0b
BS		 4962{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4963{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 4964
08d96e0b 4965{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
1da177e4 4966
08d96e0b
BS		 4967{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4968{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
1da177e4 4969
08d96e0b 4970{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
1da177e4 4971
08d96e0b
BS		 4972{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
4973{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4974{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4975{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
1da177e4 4976
08d96e0b 4977{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
897f112b 4978
08d96e0b
BS		 4979{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4980{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
1da177e4 4981
08d96e0b
BS		 4982{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
4983{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
1da177e4 4984
08d96e0b
BS		 4985{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
4986{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
1da177e4 4987
08d96e0b 4988{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
1da177e4 4989
08d96e0b 4990{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
1da177e4 4991
08d96e0b 4992{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
1da177e4 4993
08d96e0b
BS		 4994{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4995{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
897f112b 4996
08d96e0b
BS		 4997{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4998{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4999{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5000{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5001
08d96e0b
BS		 5002{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5003{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5004{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5005{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5006
08d96e0b 5007{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
1da177e4 5008
08d96e0b 5009{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
1da177e4 5010
08d96e0b
BS		 5011{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5012{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5013{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5014{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
1da177e4 5015
08d96e0b 5016{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
1da177e4 5017
08d96e0b 5018{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
1da177e4 5019
08d96e0b 5020{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
1da177e4 5021
08d96e0b
BS		 5022{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5023{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5024
08d96e0b
BS		 5025{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5026{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5027
08d96e0b 5028{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1da177e4 5029
08d96e0b 5030{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
1da177e4 5031
08d96e0b 5032{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
1da177e4 5033
08d96e0b
BS		 5034{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5035{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 5036
08d96e0b
BS		 5037{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5038{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5039{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5040{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5041
08d96e0b
BS		 5042{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5043{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
1da177e4 5044
08d96e0b
BS		 5045{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5046{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5047{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5048{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5049
08d96e0b
BS		 5050{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5051{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5052{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5053{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 5054
08d96e0b
BS		 5055{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5056{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5057{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5058{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
1da177e4 5059
08d96e0b
BS		 5060{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5061{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5062{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
1da177e4 5063
08d96e0b
BS		 5064{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5065{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5066{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5067{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
1da177e4 5068
08d96e0b 5069{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
1da177e4 5070
08d96e0b
BS		 5071{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5072{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
1da177e4 5073
08d96e0b 5074{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
1da177e4 5075
08d96e0b 5076{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
897f112b 5077
08d96e0b
BS		 5078{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5079{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
1da177e4 5080
08d96e0b 5081{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
1da177e4 5082
08d96e0b 5083{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
1da177e4 5084
08d96e0b 5085{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
1da177e4 5086
08d96e0b
BS		 5087{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5088{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5089{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1da177e4 5090
08d96e0b 5091{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
1da177e4 5092
08d96e0b
BS		 5093{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5094{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5095{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5096{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 5097
08d96e0b 5098{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
1da177e4 5099
08d96e0b
BS		 5100{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5101{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
1da177e4 5102
08d96e0b 5103{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
897f112b 5104
08d96e0b
BS		 5105{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5106{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
1da177e4 5107
08d96e0b 5108{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
1da177e4 5109
08d96e0b 5110{"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
1da177e4 5111
08d96e0b
BS		 5112{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5113{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
1da177e4 5114
08d96e0b
BS		 5115{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5116{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5117{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5118{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
1da177e4 5119
08d96e0b 5120{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
1da177e4 5121
08d96e0b 5122{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
897f112b 5123
08d96e0b
BS		 5124{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5125{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
1da177e4 5126
08d96e0b 5127{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1da177e4 5128
08d96e0b 5129{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
1da177e4 5130
08d96e0b
BS		 5131{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5132{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
1da177e4 5133
08d96e0b 5134{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
1da177e4 5135
08d96e0b
BS		 5136{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5137
5138{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5139{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5140{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5141{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5142
5143{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5144
5145{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5146
5147{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5148
5149{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5150
5151{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5152
5153{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5154{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5155
5156{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5157
5158{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5159{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5160{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5161{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5162{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5163{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5164{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5165{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5166{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5167{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5168{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5169{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5170{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5171{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5172{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5173{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5174{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5175{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5176{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5177{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5178{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5179{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5180{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5181{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5182{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5183{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5184{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5185{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5186{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5187{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5188{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5189{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5190{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5191{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5192{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5193{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5194
5195{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5196
5197{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5198
5199{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5200{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5201
5202{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5203
5204{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5205{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5206
5207{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5208
5209{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5210{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5211{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5212{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5213{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5214{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5215{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5216{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5217{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5218{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5219{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5220{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5221{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5222{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5223{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5224{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5225{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5226{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5227{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5228{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5229{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5230{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5231{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5232{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5233{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5234{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5235{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5236{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5237{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5238{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5239{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5240{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5241{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5242{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5243{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5244{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5245{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5246{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5247{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5248{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5249{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5250{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5251{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5252{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5253{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5254{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5255{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5256{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5257{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5258{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5259{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5260{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5261{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5262{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5263{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5264{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5265{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5266{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5267{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5268{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5269{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5270{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5271{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5272{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5273{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5274{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5275{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5276{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5277{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5278{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5279{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5280{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5281{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5282{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5283{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5284{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5285{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5286{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5287{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5288{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5289{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5290{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5291{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5292{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5293{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5294{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5295{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5296{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5297{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5298{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5299{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5300{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5301{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5302{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5303{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5304{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5305{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5306{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5307{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5308{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5309{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5310{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5311{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5312{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5313{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5314{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5315{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5316{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5317{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5318{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5319{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5320{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5321{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5322{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5323{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5324{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5325{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5326{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5327{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5328{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5329{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5330{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5331{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5332{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5333{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5334{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5335{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5336{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5337{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5338{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5339{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5340{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5341{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5342{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5343{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5344{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5345{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5346{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5347{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5348{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5349{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5350{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5351{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5352{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5353{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5354{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5355{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5356{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5357{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5358{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5359{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5360{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5361{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5362{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5363{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5364{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5365{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5366{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5367{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5368{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5369{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5370{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5371{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5372{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5373{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5374{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5375{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5376{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5377{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5378{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5379{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5380{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5381{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5382{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5383{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5384{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5385{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5386{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5387{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5388{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5389{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5390{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5391{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5392{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5393{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5394{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5395{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5396{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5397{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5398{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5399{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5400{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5401{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5402{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5403{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5404{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5405{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5406{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5407{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5408{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5409{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5410
5411{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5412
5413{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5414
5415{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5416
5417{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5418
5419{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5420{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5421
5422{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5423{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5424
5425{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5426
5427{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5428
5429{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5430{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5431{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5432
5433{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5434
5435{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5436
5437{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5438
5439{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5440
5441{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5442{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5443
5444{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5445
5446{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5447{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5448
5449{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5450{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5451{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5452{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5453
5454{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5455{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5456
5457{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5458
5459{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5460
5461{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5462
5463{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5464
5465{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5466{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5467
5468{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5469
5470{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5471{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5472
5473{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5474
5475{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5476
5477{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5478
5479{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5480
5481{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5482{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5483{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5484{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5485
5486{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5487
5488{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5489
5490{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5491
5492{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5493
5494{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5495
5496{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5497
5498{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
5499
5500{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
5501
5502/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5503 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5504{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5505{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5506{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5507{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5508{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5509{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5510{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5511
5512{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5513{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5514{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5515{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5516{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5517{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5518{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5519{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5520{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5521{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5522{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5523{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5524{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5525{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5526{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5527{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5528{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5529{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5530{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5531{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5532{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5533{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5534{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5535{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5536{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5537{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5538{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5539{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5540{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5541{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5542{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5543{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5544{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5545{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5546{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5547{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5548
5549{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5550
5551{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5552{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5553
5554{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5555{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5556
5557{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5558{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5559
5560{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5561{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5562
5563{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5564
5565{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5566{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5567{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5568{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5569{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5570{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5571{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5572{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5573{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5574{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5575{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5576{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5577{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5578{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5579{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5580{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5581{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5582{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5583{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5584{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5585{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5586{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5587{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5588{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5589{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5590{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5591{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5592{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5593{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5594{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5595{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5596{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5597{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5598{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5599{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5600{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5601{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5602{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5603{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5604{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5605{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5606{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5607{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5608{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5609{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5610{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5611{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5612{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5613{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5614{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5615{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5616{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5617{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5618{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5619{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5620{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5621{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5622{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5623{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5624{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5625{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5626{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5627{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5628{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5629{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5630{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5631{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5632{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5633{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5634{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5635{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5636{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5637{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5638{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5639{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5640{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5641{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5642{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5643{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5644{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5645{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5646{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5647{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5648{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5649{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5650{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5651{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5652{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5653{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5654{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5655{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5656{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5657{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5658{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5659{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5660{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5661{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5662{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5663{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5664{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5665{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5666{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5667{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5668{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5669{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5670{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5671{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5672{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5673{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5674{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5675{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5676{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5677{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5678{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5679{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5680{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5681{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5682{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5683{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5684{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5685{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5686{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5687{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5688{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5689{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5690{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5691{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5692{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5693{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5694{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5695{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5696{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5697{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5698{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5699{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5700{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5701{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5702{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5703{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5704{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5705{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5706{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5707{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5708{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5709{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5710{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5711{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5712{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5713{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5714{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5715{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5716{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5717{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5718{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5719{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5720{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5721{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5722{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5723{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5724{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5725{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5726{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5727{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5728{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5729{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5730
5731{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5732
5733{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5734{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5735
5736{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5737
5738{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5739
5740{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5741
5742{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5743
5744{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5745{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5746
5747{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5748{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5749
5750{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5751{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5752
5753{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5754
5755{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5756{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5757
5758{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5759
5760{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5761
5762{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5763
5764{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5765
5766{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5767{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
1da177e4 5768
08d96e0b 5769{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
1da177e4 5770
08d96e0b
BS		 5771{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5772{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
897f112b 5773
08d96e0b
BS		 5774{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5775{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5776{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5777{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5778{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5779{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
1da177e4 5780
08d96e0b
BS		 5781{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5782{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5783{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5784{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 5785
08d96e0b 5786{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
1da177e4 5787
08d96e0b 5788{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
1da177e4 5789
08d96e0b 5790{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
1da177e4 5791
08d96e0b
BS		 5792{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5793{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 5794
08d96e0b
BS		 5795{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5796{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 5797
08d96e0b 5798{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
1da177e4 5799
08d96e0b
BS		 5800{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5801{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5802{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5803{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
1da177e4 5804
08d96e0b
BS		 5805{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5806{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5807
08d96e0b
BS		 5808{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5809{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
1da177e4 5810
08d96e0b
BS		 5811{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5812{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
1da177e4 5813
08d96e0b
BS		 5814{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5815{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5816
08d96e0b
BS		 5817{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5818{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
1da177e4 5819
08d96e0b 5820{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
897f112b 5821
08d96e0b 5822{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
1da177e4 5823
08d96e0b
BS		 5824{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5825{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 5826
08d96e0b
BS		 5827{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5828{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5829{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5830{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
1da177e4 5831
08d96e0b 5832{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
1da177e4 5833
08d96e0b 5834{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
1da177e4 5835
08d96e0b
BS		 5836{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5837{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
1da177e4 5838
08d96e0b 5839{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
1da177e4 5840
08d96e0b
BS		 5841{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5842{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
897f112b 5843
08d96e0b 5844{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
1da177e4 5845
08d96e0b 5846{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
1da177e4 5847
08d96e0b 5848{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 5849
08d96e0b 5850{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
1da177e4 5851
08d96e0b 5852{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
1da177e4 5853
08d96e0b
BS		 5854{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5855{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
1da177e4 5856
08d96e0b
BS		 5857{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
5858{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5859{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5860{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5861{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
5862{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5863{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5864{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5865{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
897f112b 5866
08d96e0b 5867{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
1da177e4 5868
08d96e0b
BS		 5869{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5870{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
1da177e4 5871
08d96e0b 5872{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
1da177e4 5873
08d96e0b 5874{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
897f112b 5875
08d96e0b 5876{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
1da177e4 5877
08d96e0b 5878{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
897f112b 5879
08d96e0b
BS		 5880{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5881{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
897f112b 5882
08d96e0b
BS		 5883{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5884{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
1da177e4 5885
08d96e0b 5886{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
1da177e4 5887
08d96e0b 5888{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
897f112b 5889
08d96e0b 5890{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
1da177e4 5891
08d96e0b
BS		 5892{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
5893{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
1da177e4 5894
08d96e0b
BS		 5895{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5896{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 5897
08d96e0b 5898{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
1da177e4 5899
08d96e0b 5900{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
1da177e4 5901
08d96e0b
BS		 5902{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5903{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5904{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5905{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 5906
08d96e0b
BS		 5907{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5908{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5909{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5910{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
897f112b 5911
08d96e0b 5912{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
1da177e4 5913
08d96e0b 5914{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
1da177e4 5915
08d96e0b
BS		 5916{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5917{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
1da177e4 5918
08d96e0b
BS		 5919{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5920{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
1da177e4 5921
08d96e0b 5922{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
1da177e4 5923
08d96e0b
BS		 5924{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5925{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5926
08d96e0b
BS		 5927{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5928{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
897f112b 5929
08d96e0b
BS		 5930{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
5931{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
1da177e4 5932
08d96e0b 5933{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
1da177e4 5934
08d96e0b
BS		 5935{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5936{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 5937
08d96e0b
BS		 5938{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5939{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
1da177e4 5940
08d96e0b 5941{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
1da177e4 5942
08d96e0b 5943{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
1da177e4 5944
08d96e0b
BS		 5945{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5946{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
897f112b 5947
08d96e0b
BS		 5948{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
5949{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
1da177e4 5950
08d96e0b 5951{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
1da177e4 5952
08d96e0b 5953{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
1da177e4 5954
08d96e0b 5955{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
897f112b 5956
08d96e0b 5957{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
1da177e4 5958
08d96e0b 5959{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
1da177e4 5960
08d96e0b
BS		 5961{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5962{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5963{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5964{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5965
08d96e0b
BS		 5966{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5967{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5968{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5969{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5970
08d96e0b
BS		 5971{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5972{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
1da177e4 5973
08d96e0b 5974{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
1da177e4 5975
08d96e0b 5976{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
1da177e4 5977
08d96e0b
BS		 5978{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5979{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5980
08d96e0b
BS		 5981{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
5982{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 5983
08d96e0b
BS		 5984{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5985{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
1da177e4 5986
08d96e0b 5987{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
1da177e4 5988
08d96e0b 5989{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
1da177e4 5990
08d96e0b 5991{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
1da177e4 5992
08d96e0b 5993{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 5994
08d96e0b
BS		 5995{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5996{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5997{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5998{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 5999
08d96e0b
BS		 6000{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6001{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
1da177e4 6002
08d96e0b
BS		 6003{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6004{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6005{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6006{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
1da177e4 6007
08d96e0b
BS		 6008{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6009{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6010{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6011{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 6012
08d96e0b
BS		 6013{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6014{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6015{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
1da177e4 6016
08d96e0b 6017{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
1da177e4 6018
08d96e0b
BS		 6019{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6020{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
1da177e4 6021
08d96e0b 6022{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
1da177e4 6023
08d96e0b
BS		 6024{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6025{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
1da177e4 6026
08d96e0b 6027{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
1da177e4 6028
08d96e0b 6029{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
1da177e4 6030
08d96e0b
BS		 6031{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6032{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6033{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
897f112b 6034
08d96e0b
BS		 6035{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6036{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
1da177e4 6037
08d96e0b
BS		 6038{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6039{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6040{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6041{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
1da177e4 6042
08d96e0b
BS		 6043{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6044{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
1da177e4 6045
08d96e0b
BS		 6046{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6047{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
1da177e4 6048
08d96e0b 6049{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
1da177e4 6050
08d96e0b 6051{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
897f112b 6052
08d96e0b 6053{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
897f112b 6054
08d96e0b 6055{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
1da177e4 6056
08d96e0b
BS		 6057{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6058{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
1da177e4 6059
08d96e0b
BS		 6060{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6061{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6062{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6063{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
1da177e4 6064
08d96e0b
BS		 6065{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6066{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
1da177e4 6067
08d96e0b 6068{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
1da177e4 6069
08d96e0b
BS		 6070{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6071{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6072{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
1da177e4 6073
08d96e0b
BS		 6074{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6075{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
1da177e4 6076
08d96e0b 6077{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
897f112b 6078
08d96e0b 6079{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
1da177e4 6080
08d96e0b 6081{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
1da177e4 6082
08d96e0b 6083{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
1da177e4 6084
08d96e0b 6085{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
1da177e4 6086
08d96e0b 6087{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
897f112b 6088
08d96e0b
BS		 6089{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6090{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6091{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6092{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
897f112b 6093
08d96e0b
BS		 6094{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6095{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
897f112b 6096
08d96e0b 6097{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
897f112b 6098
08d96e0b 6099{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
897f112b 6100
08d96e0b
BS		 6101{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6102{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
897f112b 6103
08d96e0b
BS		 6104{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6105{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
897f112b 6106
08d96e0b 6107{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
897f112b 6108
08d96e0b 6109{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
897f112b 6110
08d96e0b
BS		 6111{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6112{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6113{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
897f112b 6114
08d96e0b 6115{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
897f112b 6116
08d96e0b
BS		 6117{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6118{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6119{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6120{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
897f112b 6121
08d96e0b 6122{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
897f112b 6123
08d96e0b 6124{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
897f112b 6125
08d96e0b
BS		 6126{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6127{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
897f112b 6128
08d96e0b
BS		 6129{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6130{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
897f112b 6131
08d96e0b 6132{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
897f112b 6133
08d96e0b 6134{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
897f112b 6135
08d96e0b 6136{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
897f112b 6137
08d96e0b 6138{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
897f112b 6139
08d96e0b 6140{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
897f112b 6141
08d96e0b 6142{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
1da177e4 6143
08d96e0b
BS		 6144{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6145{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
1da177e4 6146
08d96e0b 6147{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
897f112b 6148
08d96e0b
BS		 6149{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6150{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1da177e4 6151
08d96e0b
BS		 6152{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6153{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6154{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6155{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
1da177e4 6156
08d96e0b
BS		 6157{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6158{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
1da177e4 6159
08d96e0b 6160{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
1da177e4 6161
08d96e0b
BS		 6162{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6163{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
1da177e4 6164
08d96e0b
BS		 6165{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6166{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
897f112b 6167
08d96e0b 6168{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
897f112b 6169
08d96e0b 6170{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
897f112b 6171
08d96e0b
BS		 6172{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6173{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
1da177e4 6174
08d96e0b
BS		 6175{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6176{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 6177
08d96e0b
BS		 6178{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6179{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
1da177e4 6180
08d96e0b
BS		 6181{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6182{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6183{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6184{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
1da177e4 6185
08d96e0b 6186{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
1da177e4 6187
08d96e0b 6188{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
1da177e4 6189
08d96e0b
BS		 6190{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6191{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6192{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
1da177e4 6193
08d96e0b 6194{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
1da177e4 6195
08d96e0b
BS		 6196{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6197{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6198{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6199{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
897f112b 6200
08d96e0b
BS		 6201{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6202{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
1da177e4 6203
08d96e0b 6204{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
1da177e4 6205
08d96e0b
BS		 6206{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6207{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6208{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
1da177e4 6209
08d96e0b 6210{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
1da177e4 6211
08d96e0b
BS		 6212{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6213{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
1da177e4 6214
08d96e0b 6215{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
1da177e4 6216
08d96e0b
BS		 6217{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6218{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
1da177e4 6219
08d96e0b
BS		 6220{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6221{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
897f112b 6222
08d96e0b 6223{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
897f112b 6224
08d96e0b
BS		 6225{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6226{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
1da177e4 6227
08d96e0b
BS		 6228{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6229{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
1da177e4 6230
08d96e0b
BS		 6231{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6232{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
1da177e4 6233
08d96e0b
BS		 6234{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6235{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
897f112b 6236
08d96e0b
BS		 6237{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6238{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6239{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6240{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
897f112b 6241
08d96e0b 6242{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
1da177e4 6243
08d96e0b 6244{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
1da177e4 6245
08d96e0b 6246{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
897f112b 6247
08d96e0b 6248{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
897f112b 6249
08d96e0b
BS		 6250{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6251{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
897f112b 6252
08d96e0b 6253{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
1da177e4 6254
08d96e0b 6255{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
1da177e4 6256
08d96e0b 6257{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
897f112b 6258
08d96e0b
BS		 6259{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6260{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
897f112b 6261
08d96e0b
BS		 6262{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6263{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
897f112b 6264
08d96e0b
BS		 6265{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6266{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
1da177e4 6267
08d96e0b 6268{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
897f112b 6269
08d96e0b 6270{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
897f112b 6271
08d96e0b 6272{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
897f112b 6273
08d96e0b 6274{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
897f112b 6275
08d96e0b
BS		 6276{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6277{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
897f112b 6278
08d96e0b 6279{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
897f112b 6280
08d96e0b 6281{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
1da177e4 6282
08d96e0b
BS		 6283{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6284{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6285{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
897f112b 6286
08d96e0b
BS		 6287{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6288{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6289{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
897f112b 6290
08d96e0b
BS		 6291{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6292{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6293{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6294{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
1da177e4 6295
08d96e0b
BS		 6296{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6297{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
897f112b 6298
08d96e0b
BS		 6299{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6300{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
897f112b 6301
08d96e0b 6302{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
1da177e4 6303
08d96e0b 6304{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
1da177e4 6305
08d96e0b
BS		 6306{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6307{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
897f112b 6308
08d96e0b
BS		 6309{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6310{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
1da177e4 6311
08d96e0b 6312{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
897f112b 6313
08d96e0b
BS		 6314{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6315
6316{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6317
6318{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6319
6320{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6321
6322{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6323
6324{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6325
6326{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6327
6328{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6329{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6330
6331{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6332{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6333
6334{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6335
6336{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6337
6338{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6339
6340{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6341
6342{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6343
6344{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6345
6346{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6347
6348{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6349
6350{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6351{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6352{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6353
6354{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6355{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6356{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6357{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6358{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6359
6360{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6361{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6362{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6363
6364{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6365{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6366
6367{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6368{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6369
6370{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6371{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6372
6373{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6374{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6375
6376{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6377{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6378
6379{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6380{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6381
6382{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6383{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6384{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6385{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6386
6387{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6388{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6389
6390{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6391{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6392{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6393{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6394
6395{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6396{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6397
6398{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6399{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6400
6401{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6402{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6403
6404{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6405{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6406
6407{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6408{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6409
6410{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6411{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6412
6413{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6414{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6415
6416{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6417{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6418
6419{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6420{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6421
6422{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6423{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6424
6425{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6426
6427{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6428{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6429{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6430
6431{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6432{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6433
6434{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6435{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6436
6437{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6438{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6439
6440{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6441{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6442
6443{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6444{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6445
6446{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6447{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6448
6449{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6450{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6451
6452{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6453
6454{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6455{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6456
6457{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6458{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6459
6460{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6461{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6462
6463{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6464{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6465
6466{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6467{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6468
6469{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6470{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6471
6472{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6473{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6474
6475{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6476{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6477{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6478{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6479{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6480{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6481{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6482{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6483{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6484{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6485{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6486{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6487{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6488{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6489{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6490{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6491{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6492{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6493{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6494{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6495{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6496{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6497{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6498{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6499{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6500{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6501{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6502{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6503{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6504{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6505{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6506{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6507{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6508{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6509{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6510{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6511{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6512{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6513{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6514{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6515{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6516{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6517{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6518{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6519{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6520{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6521{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6522{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6523{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6524{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6525{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6526{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6527{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6528{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6529{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6530{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6531{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6532{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6533{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6534{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6535{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6536{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6537{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6538{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6539{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6540{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6541{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6542{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6543{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6544{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6545{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6546{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6547{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6548{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6549{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6550{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6551{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6552{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6553{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6554{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6555{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6556{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6557{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6558{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6559{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6560{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6561{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6562{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6563{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6564{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6565{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6566{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6567{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6568{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6569{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6570{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6571{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6572{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6573{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6574{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6575{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6576{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6577{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6578{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6579{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6580{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6581{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6582{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6583{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6584{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6585{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6586{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6587{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6588{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6589{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6590{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6591{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6592{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6593{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6594{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6596{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6597{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6598{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6599{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6600{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6601{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6602{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6603{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6605{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6606{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6607{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6608{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6609{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6610{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6611{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6612{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6613{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6614{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6615{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6616{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6617{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6619{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6620{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6622{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6623{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6624{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6625{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6626{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6627{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6628{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6630{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6631{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6633{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6634{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6635{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6636{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6637{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6638{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6639{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6640{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6641{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6642{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6644{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6645{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6647{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6648{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6649{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6650{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6651{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6652{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6653{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6654{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6655{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6656{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6657{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6658{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6659{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6660{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6661{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6662{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6663{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6664{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6665{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6666{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6667{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6669{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6670{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6671{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6672{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6673
6674{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6675{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6676
6677{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6678{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6679{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6680{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6681{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6682{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6683{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6684
6685{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6686{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6687{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6688
6689{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6690
6691{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6692{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6693
6694{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6695{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6696
6697{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6698{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6699
6700{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6701{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6702
6703{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6704{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6705
6706{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6707{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6708
6709{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6710{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6711{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6712{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6713
6714{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6715{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6716{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6717{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6718
6719{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6720{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6721{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6722{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6723
6724{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6725{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6726{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6727{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6728
6729{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6730{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6731{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6732{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6733
6734{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6735{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6736
6737{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6738{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6739
6740{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6741{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6742{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6743{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6744
6745{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6746{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6747{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6748{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6749
6750{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6751{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6752{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6753{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6754
6755{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6756{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6757{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6758{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6759
6760{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6761{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6762{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6763{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6764
6765{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6766{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6767{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6768{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6769
6770{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6771{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6772{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6773{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6774
6775{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6776
6777{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6778{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6779
6780{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6781{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6782
6783{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6784{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6785
6786{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6787
6788{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6789{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
6790
6791{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6792{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6793
6794{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6795
6796{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6797{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6798
6799{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6800{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6801
6802{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6803{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
6804
6805{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6806{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6807
6808{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6809{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6810
6811{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6812{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6813
6814{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6815
6816{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
6817
6818{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6819
6820{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6821
6822{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6823{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6824{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6825{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6826
6827{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6828{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6829
6830{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6831{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6832{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6833{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6834
6835{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
6836
6837{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6838
6839{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6840
6841{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6842{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
6843
6844{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6845{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6846
6847{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6848{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6849
6850{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6851{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6852
6853{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6854{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6855
6856{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6857{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6858
6859{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6860{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6861
6862{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6863{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6864
6865{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6866{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6867
6868{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6869{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6870
6871{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6872{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6873
6874{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6875{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6876
6877{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6878{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6879
6880{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6881{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6882
6883{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6884{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6885
6886{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6887{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6888
6889{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6890{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6891
6892{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6893{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6894
6895{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6896{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6897
6898{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6899{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6900
6901{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6902{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6903{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6904{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6905{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6906{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6907
6908{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6909
6910{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6911
6912{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6913{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
6914
6915{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
6916
6917{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6918{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6919{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6920{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6921
6922{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6923{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6924
6925{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6926{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6927
6928{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6929{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6930{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6931{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6932{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6933{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6934{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6935
6936{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6937{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6938{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6939{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6940
6941{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6942{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6943{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6944{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6945
6946{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6947{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6948
6949{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6950{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6951{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6952{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6953{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6954{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6955{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6956{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6957{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6958
6959{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6960
6961{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6962{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6963{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6964{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6965
6966{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6967{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6968
6969{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6970
6971{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6972{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6973
6974{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6975{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6976
6977{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6978
6979{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6980{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
1da177e4
LT		 6981};
6982
cc7639ce
BS		 6983const int powerpc_num_opcodes =
6984 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
1da177e4 6985\f
08d96e0b
BS		 6986/* The VLE opcode table.
6987
6988 The format of this opcode table is the same as the main opcode table. */
6989
6990const struct powerpc_opcode vle_opcodes[] = {
6991{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
6992{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
6993{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
6994{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
6995{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
6996{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
6997{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
6998{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
6999{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7000{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7001{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7002{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7003{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7004{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7005{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7006{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7007{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7008{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7009{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7010{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7011{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7012{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7013{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7014{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7015{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7016{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7017{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7018{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7019{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7020{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7021{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7022{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7023
7024{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7025{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7026{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7027{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7028{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7029{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7030{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7031{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7032{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7033{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7034{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7035{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7036{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7037{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7038{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7039{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7040{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7041{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7042{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7043{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7044{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7045{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7046{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7047{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7048{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7049{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7050{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7051{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7052{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7053{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7054{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7055{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7056{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7057{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7058{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7059{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7060{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7061{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7062{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7063{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7064{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7065{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7066{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7067
7068{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7069{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7070{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7071{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7072{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7073{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7074{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7075
7076{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7077{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7078{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7079
7080{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7081{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7082{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7083{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7084{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7085{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7086{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7087{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7088{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7089
7090{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7091{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7092{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7093{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7094
7095{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7096{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7097{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7098{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7099{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7100{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7101{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7102
7103{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7104{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7105{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7106{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7107{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7108{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7109{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7110{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7111{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7112{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7113{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7114{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7115{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7116{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7117{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7118{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7119{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7120{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7121{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7122{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7123{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7124{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7125{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7126{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7127{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7128{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7129{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7130{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7131{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7132{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7133{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7134{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7135{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7136{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7137{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7138{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7139{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7140{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7141{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7142{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7143{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7144{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7145{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7146{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7147{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7148{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7149{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7150{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7151{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7152
7153{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7154{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7155{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7156{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7157
7158{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7159{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7160{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7161{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7162{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7163{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7164{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7165{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7166{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7167{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7168{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7169
7170{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7171
7172{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7173{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7174
7175{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7176{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7177
7178{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7179{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7180
7181{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7182
7183{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7184{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7185
7186{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7187
7188{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7189{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7190
7191{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7192
7193{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7194
7195{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7196
7197{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7198
7199{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7200
7201{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7202
7203{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7204{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7205{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7206{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7207{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7208{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7209{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7210{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7211{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7212{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7213{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7214{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7215{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7216{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7217{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7218{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7219{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
1da177e4
LT		 7220};
7221
08d96e0b
BS		 7222const int vle_num_opcodes =
7223 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
1da177e4
LT		 7224\f
7225/* The macro table. This is only used by the assembler. */
7226
7227/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7228 when x=0; 32-x when x is between 1 and 31; are negative if x is
7229 negative; and are 32 or more otherwise. This is what you want
7230 when, for instance, you are emulating a right shift by a
7231 rotate-left-and-mask, because the underlying instructions support
7232 shifts of size 0 but not shifts of size 32. By comparison, when
7233 extracting x bits from some word you want to use just 32-x, because
7234 the underlying instructions don't support extracting 0 bits but do
7235 support extracting the whole word (32 bits in this case). */
7236
7237const struct powerpc_macro powerpc_macros[] = {
08d96e0b
BS		 7238{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7239{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
7240{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7241{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7242{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7243{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7244{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7245{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7246{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7247{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7248{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7249{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7250{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7251{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7252{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
7253{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
7254
7255{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7256{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7257{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7258{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7259{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7260{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7261{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7262{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7263{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7264{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7265{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7266{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7267{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7268{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7269{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7270{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7271{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7272{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7273{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7274{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7275{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7276{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7277
7278{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7279{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7280{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7281{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7282{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7283{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7284{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7285{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7286{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7287{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7288{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
1da177e4
LT		 7289};
7290
cc7639ce
BS		 7291const int powerpc_num_macros =
7292 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
ubuntu-bionic-kernel mirror