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1da177e4 LT |
1 | /* |
2 | * arch/ppc/kernel/traps.c | |
3 | * | |
4 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
12 | * and Paul Mackerras (paulus@cs.anu.edu.au) | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This file handles the architecture-dependent parts of hardware exceptions | |
17 | */ | |
18 | ||
19 | #include <linux/errno.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/stddef.h> | |
24 | #include <linux/unistd.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/user.h> | |
28 | #include <linux/a.out.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/config.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/prctl.h> | |
34 | ||
35 | #include <asm/pgtable.h> | |
36 | #include <asm/uaccess.h> | |
37 | #include <asm/system.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/reg.h> | |
40 | #include <asm/xmon.h> | |
41 | #ifdef CONFIG_PMAC_BACKLIGHT | |
42 | #include <asm/backlight.h> | |
43 | #endif | |
44 | #include <asm/perfmon.h> | |
45 | ||
46 | #ifdef CONFIG_XMON | |
47 | void (*debugger)(struct pt_regs *regs) = xmon; | |
48 | int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt; | |
49 | int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep; | |
50 | int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match; | |
51 | int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match; | |
52 | void (*debugger_fault_handler)(struct pt_regs *regs); | |
53 | #else | |
54 | #ifdef CONFIG_KGDB | |
55 | void (*debugger)(struct pt_regs *regs); | |
56 | int (*debugger_bpt)(struct pt_regs *regs); | |
57 | int (*debugger_sstep)(struct pt_regs *regs); | |
58 | int (*debugger_iabr_match)(struct pt_regs *regs); | |
59 | int (*debugger_dabr_match)(struct pt_regs *regs); | |
60 | void (*debugger_fault_handler)(struct pt_regs *regs); | |
61 | #else | |
62 | #define debugger(regs) do { } while (0) | |
63 | #define debugger_bpt(regs) 0 | |
64 | #define debugger_sstep(regs) 0 | |
65 | #define debugger_iabr_match(regs) 0 | |
66 | #define debugger_dabr_match(regs) 0 | |
67 | #define debugger_fault_handler ((void (*)(struct pt_regs *))0) | |
68 | #endif | |
69 | #endif | |
70 | ||
71 | /* | |
72 | * Trap & Exception support | |
73 | */ | |
74 | ||
75 | DEFINE_SPINLOCK(die_lock); | |
76 | ||
77 | void die(const char * str, struct pt_regs * fp, long err) | |
78 | { | |
79 | static int die_counter; | |
80 | int nl = 0; | |
81 | console_verbose(); | |
82 | spin_lock_irq(&die_lock); | |
83 | #ifdef CONFIG_PMAC_BACKLIGHT | |
84 | set_backlight_enable(1); | |
85 | set_backlight_level(BACKLIGHT_MAX); | |
86 | #endif | |
87 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
88 | #ifdef CONFIG_PREEMPT | |
89 | printk("PREEMPT "); | |
90 | nl = 1; | |
91 | #endif | |
92 | #ifdef CONFIG_SMP | |
93 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
94 | nl = 1; | |
95 | #endif | |
96 | if (nl) | |
97 | printk("\n"); | |
98 | show_regs(fp); | |
99 | spin_unlock_irq(&die_lock); | |
100 | /* do_exit() should take care of panic'ing from an interrupt | |
101 | * context so we don't handle it here | |
102 | */ | |
103 | do_exit(err); | |
104 | } | |
105 | ||
106 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
107 | { | |
108 | siginfo_t info; | |
109 | ||
110 | if (!user_mode(regs)) { | |
111 | debugger(regs); | |
112 | die("Exception in kernel mode", regs, signr); | |
113 | } | |
114 | info.si_signo = signr; | |
115 | info.si_errno = 0; | |
116 | info.si_code = code; | |
117 | info.si_addr = (void __user *) addr; | |
118 | force_sig_info(signr, &info, current); | |
119 | } | |
120 | ||
121 | /* | |
122 | * I/O accesses can cause machine checks on powermacs. | |
123 | * Check if the NIP corresponds to the address of a sync | |
124 | * instruction for which there is an entry in the exception | |
125 | * table. | |
126 | * Note that the 601 only takes a machine check on TEA | |
127 | * (transfer error ack) signal assertion, and does not | |
128 | * set any of the top 16 bits of SRR1. | |
129 | * -- paulus. | |
130 | */ | |
131 | static inline int check_io_access(struct pt_regs *regs) | |
132 | { | |
133 | #ifdef CONFIG_PPC_PMAC | |
134 | unsigned long msr = regs->msr; | |
135 | const struct exception_table_entry *entry; | |
136 | unsigned int *nip = (unsigned int *)regs->nip; | |
137 | ||
138 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
139 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
140 | /* | |
141 | * Check that it's a sync instruction, or somewhere | |
142 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
143 | * As the address is in the exception table | |
144 | * we should be able to read the instr there. | |
145 | * For the debug message, we look at the preceding | |
146 | * load or store. | |
147 | */ | |
148 | if (*nip == 0x60000000) /* nop */ | |
149 | nip -= 2; | |
150 | else if (*nip == 0x4c00012c) /* isync */ | |
151 | --nip; | |
152 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
153 | /* sync or twi */ | |
154 | unsigned int rb; | |
155 | ||
156 | --nip; | |
157 | rb = (*nip >> 11) & 0x1f; | |
158 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
159 | (*nip & 0x100)? "OUT to": "IN from", | |
160 | regs->gpr[rb] - _IO_BASE, nip); | |
161 | regs->msr |= MSR_RI; | |
162 | regs->nip = entry->fixup; | |
163 | return 1; | |
164 | } | |
165 | } | |
166 | #endif /* CONFIG_PPC_PMAC */ | |
167 | return 0; | |
168 | } | |
169 | ||
170 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
171 | /* On 4xx, the reason for the machine check or program exception | |
172 | is in the ESR. */ | |
173 | #define get_reason(regs) ((regs)->dsisr) | |
174 | #ifndef CONFIG_E500 | |
175 | #define get_mc_reason(regs) ((regs)->dsisr) | |
176 | #else | |
177 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) | |
178 | #endif | |
179 | #define REASON_FP 0 | |
180 | #define REASON_ILLEGAL ESR_PIL | |
181 | #define REASON_PRIVILEGED ESR_PPR | |
182 | #define REASON_TRAP ESR_PTR | |
183 | ||
184 | /* single-step stuff */ | |
185 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
186 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
187 | ||
188 | #else | |
189 | /* On non-4xx, the reason for the machine check or program | |
190 | exception is in the MSR. */ | |
191 | #define get_reason(regs) ((regs)->msr) | |
192 | #define get_mc_reason(regs) ((regs)->msr) | |
193 | #define REASON_FP 0x100000 | |
194 | #define REASON_ILLEGAL 0x80000 | |
195 | #define REASON_PRIVILEGED 0x40000 | |
196 | #define REASON_TRAP 0x20000 | |
197 | ||
198 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
199 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
200 | #endif | |
201 | ||
202 | /* | |
203 | * This is "fall-back" implementation for configurations | |
204 | * which don't provide platform-specific machine check info | |
205 | */ | |
206 | void __attribute__ ((weak)) | |
207 | platform_machine_check(struct pt_regs *regs) | |
208 | { | |
209 | } | |
210 | ||
211 | void MachineCheckException(struct pt_regs *regs) | |
212 | { | |
213 | unsigned long reason = get_mc_reason(regs); | |
214 | ||
215 | if (user_mode(regs)) { | |
216 | regs->msr |= MSR_RI; | |
217 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
218 | return; | |
219 | } | |
220 | ||
221 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
222 | /* the qspan pci read routines can cause machine checks -- Cort */ | |
223 | bad_page_fault(regs, regs->dar, SIGBUS); | |
224 | return; | |
225 | #endif | |
226 | ||
227 | if (debugger_fault_handler) { | |
228 | debugger_fault_handler(regs); | |
229 | regs->msr |= MSR_RI; | |
230 | return; | |
231 | } | |
232 | ||
233 | if (check_io_access(regs)) | |
234 | return; | |
235 | ||
236 | #if defined(CONFIG_4xx) && !defined(CONFIG_440A) | |
237 | if (reason & ESR_IMCP) { | |
238 | printk("Instruction"); | |
239 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
240 | } else | |
241 | printk("Data"); | |
242 | printk(" machine check in kernel mode.\n"); | |
243 | #elif defined(CONFIG_440A) | |
244 | printk("Machine check in kernel mode.\n"); | |
245 | if (reason & ESR_IMCP){ | |
246 | printk("Instruction Synchronous Machine Check exception\n"); | |
247 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
248 | } | |
249 | else { | |
250 | u32 mcsr = mfspr(SPRN_MCSR); | |
251 | if (mcsr & MCSR_IB) | |
252 | printk("Instruction Read PLB Error\n"); | |
253 | if (mcsr & MCSR_DRB) | |
254 | printk("Data Read PLB Error\n"); | |
255 | if (mcsr & MCSR_DWB) | |
256 | printk("Data Write PLB Error\n"); | |
257 | if (mcsr & MCSR_TLBP) | |
258 | printk("TLB Parity Error\n"); | |
259 | if (mcsr & MCSR_ICP){ | |
260 | flush_instruction_cache(); | |
261 | printk("I-Cache Parity Error\n"); | |
262 | } | |
263 | if (mcsr & MCSR_DCSP) | |
264 | printk("D-Cache Search Parity Error\n"); | |
265 | if (mcsr & MCSR_DCFP) | |
266 | printk("D-Cache Flush Parity Error\n"); | |
267 | if (mcsr & MCSR_IMPE) | |
268 | printk("Machine Check exception is imprecise\n"); | |
269 | ||
270 | /* Clear MCSR */ | |
271 | mtspr(SPRN_MCSR, mcsr); | |
272 | } | |
273 | #elif defined (CONFIG_E500) | |
274 | printk("Machine check in kernel mode.\n"); | |
275 | printk("Caused by (from MCSR=%lx): ", reason); | |
276 | ||
277 | if (reason & MCSR_MCP) | |
278 | printk("Machine Check Signal\n"); | |
279 | if (reason & MCSR_ICPERR) | |
280 | printk("Instruction Cache Parity Error\n"); | |
281 | if (reason & MCSR_DCP_PERR) | |
282 | printk("Data Cache Push Parity Error\n"); | |
283 | if (reason & MCSR_DCPERR) | |
284 | printk("Data Cache Parity Error\n"); | |
285 | if (reason & MCSR_GL_CI) | |
286 | printk("Guarded Load or Cache-Inhibited stwcx.\n"); | |
287 | if (reason & MCSR_BUS_IAERR) | |
288 | printk("Bus - Instruction Address Error\n"); | |
289 | if (reason & MCSR_BUS_RAERR) | |
290 | printk("Bus - Read Address Error\n"); | |
291 | if (reason & MCSR_BUS_WAERR) | |
292 | printk("Bus - Write Address Error\n"); | |
293 | if (reason & MCSR_BUS_IBERR) | |
294 | printk("Bus - Instruction Data Error\n"); | |
295 | if (reason & MCSR_BUS_RBERR) | |
296 | printk("Bus - Read Data Bus Error\n"); | |
297 | if (reason & MCSR_BUS_WBERR) | |
298 | printk("Bus - Read Data Bus Error\n"); | |
299 | if (reason & MCSR_BUS_IPERR) | |
300 | printk("Bus - Instruction Parity Error\n"); | |
301 | if (reason & MCSR_BUS_RPERR) | |
302 | printk("Bus - Read Parity Error\n"); | |
303 | #else /* !CONFIG_4xx && !CONFIG_E500 */ | |
304 | printk("Machine check in kernel mode.\n"); | |
305 | printk("Caused by (from SRR1=%lx): ", reason); | |
306 | switch (reason & 0x601F0000) { | |
307 | case 0x80000: | |
308 | printk("Machine check signal\n"); | |
309 | break; | |
310 | case 0: /* for 601 */ | |
311 | case 0x40000: | |
312 | case 0x140000: /* 7450 MSS error and TEA */ | |
313 | printk("Transfer error ack signal\n"); | |
314 | break; | |
315 | case 0x20000: | |
316 | printk("Data parity error signal\n"); | |
317 | break; | |
318 | case 0x10000: | |
319 | printk("Address parity error signal\n"); | |
320 | break; | |
321 | case 0x20000000: | |
322 | printk("L1 Data Cache error\n"); | |
323 | break; | |
324 | case 0x40000000: | |
325 | printk("L1 Instruction Cache error\n"); | |
326 | break; | |
327 | case 0x00100000: | |
328 | printk("L2 data cache parity error\n"); | |
329 | break; | |
330 | default: | |
331 | printk("Unknown values in msr\n"); | |
332 | } | |
333 | #endif /* CONFIG_4xx */ | |
334 | ||
335 | /* | |
336 | * Optional platform-provided routine to print out | |
337 | * additional info, e.g. bus error registers. | |
338 | */ | |
339 | platform_machine_check(regs); | |
340 | ||
341 | debugger(regs); | |
342 | die("machine check", regs, SIGBUS); | |
343 | } | |
344 | ||
345 | void SMIException(struct pt_regs *regs) | |
346 | { | |
347 | debugger(regs); | |
348 | #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB)) | |
349 | show_regs(regs); | |
350 | panic("System Management Interrupt"); | |
351 | #endif | |
352 | } | |
353 | ||
354 | void UnknownException(struct pt_regs *regs) | |
355 | { | |
356 | printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
357 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
358 | _exception(SIGTRAP, regs, 0, 0); | |
359 | } | |
360 | ||
361 | void InstructionBreakpoint(struct pt_regs *regs) | |
362 | { | |
363 | if (debugger_iabr_match(regs)) | |
364 | return; | |
365 | _exception(SIGTRAP, regs, TRAP_BRKPT, 0); | |
366 | } | |
367 | ||
368 | void RunModeException(struct pt_regs *regs) | |
369 | { | |
370 | _exception(SIGTRAP, regs, 0, 0); | |
371 | } | |
372 | ||
373 | /* Illegal instruction emulation support. Originally written to | |
374 | * provide the PVR to user applications using the mfspr rd, PVR. | |
375 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
376 | * memory access caused an access fault. Return zero on success. | |
377 | * | |
378 | * There are a couple of ways to do this, either "decode" the instruction | |
379 | * or directly match lots of bits. In this case, matching lots of | |
380 | * bits is faster and easier. | |
381 | * | |
382 | */ | |
383 | #define INST_MFSPR_PVR 0x7c1f42a6 | |
384 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | |
385 | ||
386 | #define INST_DCBA 0x7c0005ec | |
387 | #define INST_DCBA_MASK 0x7c0007fe | |
388 | ||
389 | #define INST_MCRXR 0x7c000400 | |
390 | #define INST_MCRXR_MASK 0x7c0007fe | |
391 | ||
392 | #define INST_STRING 0x7c00042a | |
393 | #define INST_STRING_MASK 0x7c0007fe | |
394 | #define INST_STRING_GEN_MASK 0x7c00067e | |
395 | #define INST_LSWI 0x7c0004aa | |
396 | #define INST_LSWX 0x7c00042a | |
397 | #define INST_STSWI 0x7c0005aa | |
398 | #define INST_STSWX 0x7c00052a | |
399 | ||
400 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) | |
401 | { | |
402 | u8 rT = (instword >> 21) & 0x1f; | |
403 | u8 rA = (instword >> 16) & 0x1f; | |
404 | u8 NB_RB = (instword >> 11) & 0x1f; | |
405 | u32 num_bytes; | |
406 | u32 EA; | |
407 | int pos = 0; | |
408 | ||
409 | /* Early out if we are an invalid form of lswx */ | |
410 | if ((instword & INST_STRING_MASK) == INST_LSWX) | |
411 | if ((rA >= rT) || (NB_RB >= rT) || (rT == rA) || (rT == NB_RB)) | |
412 | return -EINVAL; | |
413 | ||
414 | /* Early out if we are an invalid form of lswi */ | |
415 | if ((instword & INST_STRING_MASK) == INST_LSWI) | |
416 | if ((rA >= rT) || (rT == rA)) | |
417 | return -EINVAL; | |
418 | ||
419 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
420 | ||
421 | switch (instword & INST_STRING_MASK) { | |
422 | case INST_LSWX: | |
423 | case INST_STSWX: | |
424 | EA += NB_RB; | |
425 | num_bytes = regs->xer & 0x7f; | |
426 | break; | |
427 | case INST_LSWI: | |
428 | case INST_STSWI: | |
429 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; | |
430 | break; | |
431 | default: | |
432 | return -EINVAL; | |
433 | } | |
434 | ||
435 | while (num_bytes != 0) | |
436 | { | |
437 | u8 val; | |
438 | u32 shift = 8 * (3 - (pos & 0x3)); | |
439 | ||
440 | switch ((instword & INST_STRING_MASK)) { | |
441 | case INST_LSWX: | |
442 | case INST_LSWI: | |
443 | if (get_user(val, (u8 __user *)EA)) | |
444 | return -EFAULT; | |
445 | /* first time updating this reg, | |
446 | * zero it out */ | |
447 | if (pos == 0) | |
448 | regs->gpr[rT] = 0; | |
449 | regs->gpr[rT] |= val << shift; | |
450 | break; | |
451 | case INST_STSWI: | |
452 | case INST_STSWX: | |
453 | val = regs->gpr[rT] >> shift; | |
454 | if (put_user(val, (u8 __user *)EA)) | |
455 | return -EFAULT; | |
456 | break; | |
457 | } | |
458 | /* move EA to next address */ | |
459 | EA += 1; | |
460 | num_bytes--; | |
461 | ||
462 | /* manage our position within the register */ | |
463 | if (++pos == 4) { | |
464 | pos = 0; | |
465 | if (++rT == 32) | |
466 | rT = 0; | |
467 | } | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static int emulate_instruction(struct pt_regs *regs) | |
474 | { | |
475 | u32 instword; | |
476 | u32 rd; | |
477 | ||
478 | if (!user_mode(regs)) | |
479 | return -EINVAL; | |
480 | CHECK_FULL_REGS(regs); | |
481 | ||
482 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
483 | return -EFAULT; | |
484 | ||
485 | /* Emulate the mfspr rD, PVR. | |
486 | */ | |
487 | if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { | |
488 | rd = (instword >> 21) & 0x1f; | |
489 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
490 | return 0; | |
491 | } | |
492 | ||
493 | /* Emulating the dcba insn is just a no-op. */ | |
494 | if ((instword & INST_DCBA_MASK) == INST_DCBA) | |
495 | return 0; | |
496 | ||
497 | /* Emulate the mcrxr insn. */ | |
498 | if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { | |
499 | int shift = (instword >> 21) & 0x1c; | |
500 | unsigned long msk = 0xf0000000UL >> shift; | |
501 | ||
502 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | |
503 | regs->xer &= ~0xf0000000UL; | |
504 | return 0; | |
505 | } | |
506 | ||
507 | /* Emulate load/store string insn. */ | |
508 | if ((instword & INST_STRING_GEN_MASK) == INST_STRING) | |
509 | return emulate_string_inst(regs, instword); | |
510 | ||
511 | return -EINVAL; | |
512 | } | |
513 | ||
514 | /* | |
515 | * After we have successfully emulated an instruction, we have to | |
516 | * check if the instruction was being single-stepped, and if so, | |
517 | * pretend we got a single-step exception. This was pointed out | |
518 | * by Kumar Gala. -- paulus | |
519 | */ | |
520 | static void emulate_single_step(struct pt_regs *regs) | |
521 | { | |
522 | if (single_stepping(regs)) { | |
523 | clear_single_step(regs); | |
524 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
525 | } | |
526 | } | |
527 | ||
528 | /* | |
529 | * Look through the list of trap instructions that are used for BUG(), | |
530 | * BUG_ON() and WARN_ON() and see if we hit one. At this point we know | |
531 | * that the exception was caused by a trap instruction of some kind. | |
532 | * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 | |
533 | * otherwise. | |
534 | */ | |
535 | extern struct bug_entry __start___bug_table[], __stop___bug_table[]; | |
536 | ||
537 | #ifndef CONFIG_MODULES | |
538 | #define module_find_bug(x) NULL | |
539 | #endif | |
540 | ||
541 | static struct bug_entry *find_bug(unsigned long bugaddr) | |
542 | { | |
543 | struct bug_entry *bug; | |
544 | ||
545 | for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) | |
546 | if (bugaddr == bug->bug_addr) | |
547 | return bug; | |
548 | return module_find_bug(bugaddr); | |
549 | } | |
550 | ||
551 | int check_bug_trap(struct pt_regs *regs) | |
552 | { | |
553 | struct bug_entry *bug; | |
554 | unsigned long addr; | |
555 | ||
556 | if (regs->msr & MSR_PR) | |
557 | return 0; /* not in kernel */ | |
558 | addr = regs->nip; /* address of trap instruction */ | |
559 | if (addr < PAGE_OFFSET) | |
560 | return 0; | |
561 | bug = find_bug(regs->nip); | |
562 | if (bug == NULL) | |
563 | return 0; | |
564 | if (bug->line & BUG_WARNING_TRAP) { | |
565 | /* this is a WARN_ON rather than BUG/BUG_ON */ | |
566 | #ifdef CONFIG_XMON | |
567 | xmon_printf(KERN_ERR "Badness in %s at %s:%d\n", | |
568 | bug->function, bug->file, | |
569 | bug->line & ~BUG_WARNING_TRAP); | |
570 | #endif /* CONFIG_XMON */ | |
571 | printk(KERN_ERR "Badness in %s at %s:%d\n", | |
572 | bug->function, bug->file, | |
573 | bug->line & ~BUG_WARNING_TRAP); | |
574 | dump_stack(); | |
575 | return 1; | |
576 | } | |
577 | #ifdef CONFIG_XMON | |
578 | xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n", | |
579 | bug->function, bug->file, bug->line); | |
580 | xmon(regs); | |
581 | #endif /* CONFIG_XMON */ | |
582 | printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n", | |
583 | bug->function, bug->file, bug->line); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | void ProgramCheckException(struct pt_regs *regs) | |
589 | { | |
590 | unsigned int reason = get_reason(regs); | |
591 | extern int do_mathemu(struct pt_regs *regs); | |
592 | ||
593 | #ifdef CONFIG_MATH_EMULATION | |
594 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
595 | * but there seems to be a hardware bug on the 405GP (RevD) | |
596 | * that means ESR is sometimes set incorrectly - either to | |
597 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
598 | * hardware people - not sure if it can happen on any illegal | |
599 | * instruction or only on FP instructions, whether there is a | |
600 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
601 | if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { | |
602 | emulate_single_step(regs); | |
603 | return; | |
604 | } | |
605 | #endif /* CONFIG_MATH_EMULATION */ | |
606 | ||
607 | if (reason & REASON_FP) { | |
608 | /* IEEE FP exception */ | |
609 | int code = 0; | |
610 | u32 fpscr; | |
611 | ||
612 | /* We must make sure the FP state is consistent with | |
613 | * our MSR_FP in regs | |
614 | */ | |
615 | preempt_disable(); | |
616 | if (regs->msr & MSR_FP) | |
617 | giveup_fpu(current); | |
618 | preempt_enable(); | |
619 | ||
620 | fpscr = current->thread.fpscr; | |
621 | fpscr &= fpscr << 22; /* mask summary bits with enables */ | |
622 | if (fpscr & FPSCR_VX) | |
623 | code = FPE_FLTINV; | |
624 | else if (fpscr & FPSCR_OX) | |
625 | code = FPE_FLTOVF; | |
626 | else if (fpscr & FPSCR_UX) | |
627 | code = FPE_FLTUND; | |
628 | else if (fpscr & FPSCR_ZX) | |
629 | code = FPE_FLTDIV; | |
630 | else if (fpscr & FPSCR_XX) | |
631 | code = FPE_FLTRES; | |
632 | _exception(SIGFPE, regs, code, regs->nip); | |
633 | return; | |
634 | } | |
635 | ||
636 | if (reason & REASON_TRAP) { | |
637 | /* trap exception */ | |
638 | if (debugger_bpt(regs)) | |
639 | return; | |
640 | if (check_bug_trap(regs)) { | |
641 | regs->nip += 4; | |
642 | return; | |
643 | } | |
644 | _exception(SIGTRAP, regs, TRAP_BRKPT, 0); | |
645 | return; | |
646 | } | |
647 | ||
648 | /* Try to emulate it if we should. */ | |
649 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
650 | switch (emulate_instruction(regs)) { | |
651 | case 0: | |
652 | regs->nip += 4; | |
653 | emulate_single_step(regs); | |
654 | return; | |
655 | case -EFAULT: | |
656 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
657 | return; | |
658 | } | |
659 | } | |
660 | ||
661 | if (reason & REASON_PRIVILEGED) | |
662 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
663 | else | |
664 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
665 | } | |
666 | ||
667 | void SingleStepException(struct pt_regs *regs) | |
668 | { | |
669 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
670 | if (debugger_sstep(regs)) | |
671 | return; | |
672 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
673 | } | |
674 | ||
675 | void AlignmentException(struct pt_regs *regs) | |
676 | { | |
677 | int fixed; | |
678 | ||
679 | fixed = fix_alignment(regs); | |
680 | if (fixed == 1) { | |
681 | regs->nip += 4; /* skip over emulated instruction */ | |
682 | return; | |
683 | } | |
684 | if (fixed == -EFAULT) { | |
685 | /* fixed == -EFAULT means the operand address was bad */ | |
686 | if (user_mode(regs)) | |
687 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); | |
688 | else | |
689 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
690 | return; | |
691 | } | |
692 | _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); | |
693 | } | |
694 | ||
695 | void StackOverflow(struct pt_regs *regs) | |
696 | { | |
697 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
698 | current, regs->gpr[1]); | |
699 | debugger(regs); | |
700 | show_regs(regs); | |
701 | panic("kernel stack overflow"); | |
702 | } | |
703 | ||
704 | void nonrecoverable_exception(struct pt_regs *regs) | |
705 | { | |
706 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
707 | regs->nip, regs->msr); | |
708 | debugger(regs); | |
709 | die("nonrecoverable exception", regs, SIGKILL); | |
710 | } | |
711 | ||
712 | void trace_syscall(struct pt_regs *regs) | |
713 | { | |
714 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
715 | current, current->pid, regs->nip, regs->link, regs->gpr[0], | |
716 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); | |
717 | } | |
718 | ||
719 | #ifdef CONFIG_8xx | |
720 | void SoftwareEmulation(struct pt_regs *regs) | |
721 | { | |
722 | extern int do_mathemu(struct pt_regs *); | |
723 | extern int Soft_emulate_8xx(struct pt_regs *); | |
724 | int errcode; | |
725 | ||
726 | CHECK_FULL_REGS(regs); | |
727 | ||
728 | if (!user_mode(regs)) { | |
729 | debugger(regs); | |
730 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
731 | } | |
732 | ||
733 | #ifdef CONFIG_MATH_EMULATION | |
734 | errcode = do_mathemu(regs); | |
735 | #else | |
736 | errcode = Soft_emulate_8xx(regs); | |
737 | #endif | |
738 | if (errcode) { | |
739 | if (errcode > 0) | |
740 | _exception(SIGFPE, regs, 0, 0); | |
741 | else if (errcode == -EFAULT) | |
742 | _exception(SIGSEGV, regs, 0, 0); | |
743 | else | |
744 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
745 | } else | |
746 | emulate_single_step(regs); | |
747 | } | |
748 | #endif /* CONFIG_8xx */ | |
749 | ||
750 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
751 | ||
752 | void DebugException(struct pt_regs *regs, unsigned long debug_status) | |
753 | { | |
754 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
755 | regs->msr &= ~MSR_DE; | |
756 | if (user_mode(regs)) { | |
757 | current->thread.dbcr0 &= ~DBCR0_IC; | |
758 | } else { | |
759 | /* Disable instruction completion */ | |
760 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
761 | /* Clear the instruction completion event */ | |
762 | mtspr(SPRN_DBSR, DBSR_IC); | |
763 | if (debugger_sstep(regs)) | |
764 | return; | |
765 | } | |
766 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
767 | } | |
768 | } | |
769 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
770 | ||
771 | #if !defined(CONFIG_TAU_INT) | |
772 | void TAUException(struct pt_regs *regs) | |
773 | { | |
774 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
775 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
776 | } | |
777 | #endif /* CONFIG_INT_TAU */ | |
778 | ||
779 | void AltivecUnavailException(struct pt_regs *regs) | |
780 | { | |
781 | static int kernel_altivec_count; | |
782 | ||
783 | #ifndef CONFIG_ALTIVEC | |
784 | if (user_mode(regs)) { | |
785 | /* A user program has executed an altivec instruction, | |
786 | but this kernel doesn't support altivec. */ | |
787 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
788 | return; | |
789 | } | |
790 | #endif | |
791 | /* The kernel has executed an altivec instruction without | |
792 | first enabling altivec. Whinge but let it do it. */ | |
793 | if (++kernel_altivec_count < 10) | |
794 | printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n", | |
795 | current, regs->nip); | |
796 | regs->msr |= MSR_VEC; | |
797 | } | |
798 | ||
799 | #ifdef CONFIG_ALTIVEC | |
800 | void AltivecAssistException(struct pt_regs *regs) | |
801 | { | |
802 | int err; | |
803 | ||
804 | preempt_disable(); | |
805 | if (regs->msr & MSR_VEC) | |
806 | giveup_altivec(current); | |
807 | preempt_enable(); | |
808 | ||
809 | err = emulate_altivec(regs); | |
810 | if (err == 0) { | |
811 | regs->nip += 4; /* skip emulated instruction */ | |
812 | emulate_single_step(regs); | |
813 | return; | |
814 | } | |
815 | ||
816 | if (err == -EFAULT) { | |
817 | /* got an error reading the instruction */ | |
818 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
819 | } else { | |
820 | /* didn't recognize the instruction */ | |
821 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
822 | printk(KERN_ERR "unrecognized altivec instruction " | |
823 | "in %s at %lx\n", current->comm, regs->nip); | |
824 | current->thread.vscr.u[3] |= 0x10000; | |
825 | } | |
826 | } | |
827 | #endif /* CONFIG_ALTIVEC */ | |
828 | ||
829 | void PerformanceMonitorException(struct pt_regs *regs) | |
830 | { | |
831 | perf_irq(regs); | |
832 | } | |
833 | ||
834 | #ifdef CONFIG_FSL_BOOKE | |
835 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
836 | unsigned long error_code) | |
837 | { | |
838 | /* We treat cache locking instructions from the user | |
839 | * as priv ops, in the future we could try to do | |
840 | * something smarter | |
841 | */ | |
842 | if (error_code & (ESR_DLK|ESR_ILK)) | |
843 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
844 | return; | |
845 | } | |
846 | #endif /* CONFIG_FSL_BOOKE */ | |
847 | ||
848 | #ifdef CONFIG_SPE | |
849 | void SPEFloatingPointException(struct pt_regs *regs) | |
850 | { | |
851 | unsigned long spefscr; | |
852 | int fpexc_mode; | |
853 | int code = 0; | |
854 | ||
855 | spefscr = current->thread.spefscr; | |
856 | fpexc_mode = current->thread.fpexc_mode; | |
857 | ||
858 | /* Hardware does not neccessarily set sticky | |
859 | * underflow/overflow/invalid flags */ | |
860 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { | |
861 | code = FPE_FLTOVF; | |
862 | spefscr |= SPEFSCR_FOVFS; | |
863 | } | |
864 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
865 | code = FPE_FLTUND; | |
866 | spefscr |= SPEFSCR_FUNFS; | |
867 | } | |
868 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
869 | code = FPE_FLTDIV; | |
870 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
871 | code = FPE_FLTINV; | |
872 | spefscr |= SPEFSCR_FINVS; | |
873 | } | |
874 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
875 | code = FPE_FLTRES; | |
876 | ||
877 | current->thread.spefscr = spefscr; | |
878 | ||
879 | _exception(SIGFPE, regs, code, regs->nip); | |
880 | return; | |
881 | } | |
882 | #endif | |
883 | ||
884 | void __init trap_init(void) | |
885 | { | |
886 | } |