[mirror_ubuntu-bionic-kernel.git] / arch / ppc / platforms / 4xx / ebony.c

/*
 * arch/ppc/platforms/4xx/ebony.c
 *
 * Ebony board specific routines
 *
 * Matt Porter <mporter@kernel.crashing.org>
 * Copyright 2002-2005 MontaVista Software Inc.
 *
 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
 * Copyright (c) 2003-2005 Zultys Technologies
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/blkdev.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/initrd.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>

#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/ocp.h>
#include <asm/pci-bridge.h>
#include <asm/time.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/ppc4xx_pic.h>
#include <asm/ppcboot.h>
#include <asm/tlbflush.h>

#include <syslib/gen550.h>
#include <syslib/ibm440gp_common.h>

bd_t __res;

static struct ibm44x_clocks clocks __initdata;

/*
 * Ebony external IRQ triggering/polarity settings
 */
unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ0: PCI slot 0 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ1: PCI slot 1 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ2: PCI slot 2 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ3: PCI slot 3 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ4: IRDA */
	(IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),	/* IRQ5: SMI pushbutton */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ6: PHYs */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ7: AUX */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ8: EXT */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ9: EXT */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ10: EXT */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ11: EXT */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ12: EXT */
};

static void __init
ebony_calibrate_decr(void)
{
	unsigned int freq;

	/*
	 * Determine system clock speed
	 *
	 * If we are on Rev. B silicon, then use
	 * default external system clock.  If we are
	 * on Rev. C silicon then errata forces us to
	 * use the internal clock.
	 */
	switch (PVR_REV(mfspr(SPRN_PVR))) {
		case PVR_REV(PVR_440GP_RB):
			freq = EBONY_440GP_RB_SYSCLK;
			break;
		case PVR_REV(PVR_440GP_RC1):
		default:
			freq = EBONY_440GP_RC_SYSCLK;
			break;
	}

	ibm44x_calibrate_decr(freq);
}

static int
ebony_show_cpuinfo(struct seq_file *m)
{
	seq_printf(m, "vendor\t\t: IBM\n");
	seq_printf(m, "machine\t\t: Ebony\n");

	return 0;
}

static inline int
ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	static char pci_irq_table[][4] =
	/*
	 *	PCI IDSEL/INTPIN->INTLINE
	 * 	   A   B   C   D
	 */
	{
		{ 23, 23, 23, 23 },	/* IDSEL 1 - PCI Slot 0 */
		{ 24, 24, 24, 24 },	/* IDSEL 2 - PCI Slot 1 */
		{ 25, 25, 25, 25 },	/* IDSEL 3 - PCI Slot 2 */
		{ 26, 26, 26, 26 },	/* IDSEL 4 - PCI Slot 3 */
	};

	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
	return PCI_IRQ_TABLE_LOOKUP;
}

#define PCIX_WRITEL(value, offset) \
	(writel(value, pcix_reg_base + offset))

/*
 * FIXME: This is only here to "make it work".  This will move
 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 * configuration library. -Matt
 */
static void __init
ebony_setup_pcix(void)
{
	void __iomem *pcix_reg_base;

	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);

	/* Disable all windows */
	PCIX_WRITEL(0, PCIX0_POM0SA);
	PCIX_WRITEL(0, PCIX0_POM1SA);
	PCIX_WRITEL(0, PCIX0_POM2SA);
	PCIX_WRITEL(0, PCIX0_PIM0SA);
	PCIX_WRITEL(0, PCIX0_PIM1SA);
	PCIX_WRITEL(0, PCIX0_PIM2SA);

	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);

	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);

	eieio();
}

static void __init
ebony_setup_hose(void)
{
	struct pci_controller *hose;

	/* Configure windows on the PCI-X host bridge */
	ebony_setup_pcix();

	hose = pcibios_alloc_controller();

	if (!hose)
		return;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;

	pci_init_resource(&hose->io_resource,
			EBONY_PCI_LOWER_IO,
			EBONY_PCI_UPPER_IO,
			IORESOURCE_IO,
			"PCI host bridge");

	pci_init_resource(&hose->mem_resources[0],
			EBONY_PCI_LOWER_MEM,
			EBONY_PCI_UPPER_MEM,
			IORESOURCE_MEM,
			"PCI host bridge");

	hose->io_space.start = EBONY_PCI_LOWER_IO;
	hose->io_space.end = EBONY_PCI_UPPER_IO;
	hose->mem_space.start = EBONY_PCI_LOWER_MEM;
	hose->mem_space.end = EBONY_PCI_UPPER_MEM;
	hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
	isa_io_base = (unsigned long)hose->io_base_virt;

	setup_indirect_pci(hose,
			EBONY_PCI_CFGA_PLB32,
			EBONY_PCI_CFGD_PLB32);
	hose->set_cfg_type = 1;

	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);

	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = ebony_map_irq;
}

TODC_ALLOC();

static void __init
ebony_early_serial_map(void)
{
	struct uart_port port;

	/* Setup ioremapped serial port access */
	memset(&port, 0, sizeof(port));
	port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
	port.irq = 0;
	port.uartclk = clocks.uart0;
	port.regshift = 0;
	port.iotype = SERIAL_IO_MEM;
	port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
	port.line = 0;

	if (early_serial_setup(&port) != 0) {
		printk("Early serial init of port 0 failed\n");
	}

#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
	/* Configure debug serial access */
	gen550_init(0, &port);

	/* Purge TLB entry added in head_44x.S for early serial access */
	_tlbie(UART0_IO_BASE);
#endif

	port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
	port.irq = 1;
	port.uartclk = clocks.uart1;
	port.line = 1;

	if (early_serial_setup(&port) != 0) {
		printk("Early serial init of port 1 failed\n");
	}

#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
	/* Configure debug serial access */
	gen550_init(1, &port);
#endif
}

static void __init
ebony_setup_arch(void)
{
	struct ocp_def *def;
	struct ocp_func_emac_data *emacdata;

	/* Set mac_addr for each EMAC */
	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
	emacdata = def->additions;
	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
	emacdata->phy_mode = PHY_MODE_RMII;
	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);

	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
	emacdata = def->additions;
	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
	emacdata->phy_mode = PHY_MODE_RMII;
	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);

	/*
	 * Determine various clocks.
	 * To be completely correct we should get SysClk
	 * from FPGA, because it can be changed by on-board switches
	 * --ebs
	 */
	ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
	ocp_sys_info.opb_bus_freq = clocks.opb;

	/* Setup TODC access */
	TODC_INIT(TODC_TYPE_DS1743,
			0,
			0,
			ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
			8);

	/* init to some ~sane value until calibrate_delay() runs */
        loops_per_jiffy = 50000000/HZ;

	/* Setup PCI host bridge */
	ebony_setup_hose();

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
#ifdef CONFIG_ROOT_NFS
		ROOT_DEV = Root_NFS;
#else
		ROOT_DEV = Root_HDA1;
#endif

	ebony_early_serial_map();

	/* Identify the system */
	printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
}

void __init platform_init(unsigned long r3, unsigned long r4,
		unsigned long r5, unsigned long r6, unsigned long r7)
{
	parse_bootinfo(find_bootinfo());

	/*
	 * If we were passed in a board information, copy it into the
	 * residual data area.
	 */
	if (r3)
		__res = *(bd_t *)(r3 + KERNELBASE);

	ibm44x_platform_init();

	ppc_md.setup_arch = ebony_setup_arch;
	ppc_md.show_cpuinfo = ebony_show_cpuinfo;
	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */

	ppc_md.calibrate_decr = ebony_calibrate_decr;
	ppc_md.time_init = todc_time_init;
	ppc_md.set_rtc_time = todc_set_rtc_time;
	ppc_md.get_rtc_time = todc_get_rtc_time;

	ppc_md.nvram_read_val = todc_direct_read_val;
	ppc_md.nvram_write_val = todc_direct_write_val;
#ifdef CONFIG_KGDB
	ppc_md.early_serial_map = ebony_early_serial_map;
#endif
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/ppc/platforms/4xx/ebony.c
	3	*
	4	* Ebony board specific routines
	5	*
	6	* Matt Porter <mporter@kernel.crashing.org>
	7	* Copyright 2002-2005 MontaVista Software Inc.
	8	*
	9	* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
5ce17b18	10	* Copyright (c) 2003-2005 Zultys Technologies
1da177e4 LT	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*/
	17
	18	#include <linux/config.h>
	19	#include <linux/stddef.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/errno.h>
	23	#include <linux/reboot.h>
	24	#include <linux/pci.h>
	25	#include <linux/kdev_t.h>
	26	#include <linux/types.h>
	27	#include <linux/major.h>
	28	#include <linux/blkdev.h>
	29	#include <linux/console.h>
	30	#include <linux/delay.h>
	31	#include <linux/ide.h>
	32	#include <linux/initrd.h>
	33	#include <linux/irq.h>
	34	#include <linux/seq_file.h>
	35	#include <linux/root_dev.h>
	36	#include <linux/tty.h>
	37	#include <linux/serial.h>
	38	#include <linux/serial_core.h>
	39
	40	#include <asm/system.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/page.h>
	43	#include <asm/dma.h>
	44	#include <asm/io.h>
	45	#include <asm/machdep.h>
	46	#include <asm/ocp.h>
	47	#include <asm/pci-bridge.h>
	48	#include <asm/time.h>
	49	#include <asm/todc.h>
	50	#include <asm/bootinfo.h>
	51	#include <asm/ppc4xx_pic.h>
	52	#include <asm/ppcboot.h>
5ce17b18	53	#include <asm/tlbflush.h>
1da177e4 LT	54
	55	#include <syslib/gen550.h>
	56	#include <syslib/ibm440gp_common.h>
	57
1da177e4 LT	58	bd_t __res;
	59
	60	static struct ibm44x_clocks clocks __initdata;
	61
	62	/*
	63	* Ebony external IRQ triggering/polarity settings
	64	*/
	65	unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
	66	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
	67	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
	68	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
	69	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
	70	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
	71	(IRQ_SENSE_EDGE \| IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
	72	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
	73	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
	74	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
	75	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
	76	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
	77	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
	78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
	79	};
	80
	81	static void __init
	82	ebony_calibrate_decr(void)
	83	{
	84	unsigned int freq;
	85
	86	/*
	87	* Determine system clock speed
	88	*
	89	* If we are on Rev. B silicon, then use
	90	* default external system clock. If we are
	91	* on Rev. C silicon then errata forces us to
	92	* use the internal clock.
	93	*/
	94	switch (PVR_REV(mfspr(SPRN_PVR))) {
	95	case PVR_REV(PVR_440GP_RB):
	96	freq = EBONY_440GP_RB_SYSCLK;
	97	break;
	98	case PVR_REV(PVR_440GP_RC1):
	99	default:
	100	freq = EBONY_440GP_RC_SYSCLK;
	101	break;
	102	}
	103
	104	ibm44x_calibrate_decr(freq);
	105	}
	106
	107	static int
	108	ebony_show_cpuinfo(struct seq_file *m)
	109	{
	110	seq_printf(m, "vendor\t\t: IBM\n");
	111	seq_printf(m, "machine\t\t: Ebony\n");
	112
	113	return 0;
	114	}
	115
	116	static inline int
	117	ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
	118	{
	119	static char pci_irq_table[][4] =
	120	/*
	121	* PCI IDSEL/INTPIN->INTLINE
122	* A B C D
123	*/
124	{
125	{ 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
126	{ 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
127	{ 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
128	{ 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
129	};
130
131	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
132	return PCI_IRQ_TABLE_LOOKUP;
133	}
134
135	#define PCIX_WRITEL(value, offset) \
136	(writel(value, pcix_reg_base + offset))
137
138	/*
139	* FIXME: This is only here to "make it work". This will move
140	* to a ibm_pcix.c which will contain a generic IBM PCIX bridge
141	* configuration library. -Matt
142	*/
143	static void __init
144	ebony_setup_pcix(void)
145	{
ba724a37	146	void __iomem *pcix_reg_base;
1da177e4 LT	147
	148	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
	149
	150	/* Disable all windows */
	151	PCIX_WRITEL(0, PCIX0_POM0SA);
	152	PCIX_WRITEL(0, PCIX0_POM1SA);
	153	PCIX_WRITEL(0, PCIX0_POM2SA);
	154	PCIX_WRITEL(0, PCIX0_PIM0SA);
	155	PCIX_WRITEL(0, PCIX0_PIM1SA);
	156	PCIX_WRITEL(0, PCIX0_PIM2SA);
	157
	158	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
	159	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
	160	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
	161	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
	162	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
	163	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
	164
	165	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
	166	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
	167	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
	168	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
	169
	170	eieio();
	171	}
	172
	173	static void __init
	174	ebony_setup_hose(void)
	175	{
	176	struct pci_controller *hose;
	177
	178	/* Configure windows on the PCI-X host bridge */
	179	ebony_setup_pcix();
	180
	181	hose = pcibios_alloc_controller();
	182
	183	if (!hose)
	184	return;
	185
	186	hose->first_busno = 0;
	187	hose->last_busno = 0xff;
	188
	189	hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
	190
	191	pci_init_resource(&hose->io_resource,
	192	EBONY_PCI_LOWER_IO,
	193	EBONY_PCI_UPPER_IO,
	194	IORESOURCE_IO,
	195	"PCI host bridge");
	196
	197	pci_init_resource(&hose->mem_resources[0],
	198	EBONY_PCI_LOWER_MEM,
	199	EBONY_PCI_UPPER_MEM,
	200	IORESOURCE_MEM,
	201	"PCI host bridge");
	202
	203	hose->io_space.start = EBONY_PCI_LOWER_IO;
	204	hose->io_space.end = EBONY_PCI_UPPER_IO;
	205	hose->mem_space.start = EBONY_PCI_LOWER_MEM;
	206	hose->mem_space.end = EBONY_PCI_UPPER_MEM;
92a11f9e AV	207	hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
92a11f9e AV	208	isa_io_base = (unsigned long)hose->io_base_virt;
1da177e4 LT	209
	210	setup_indirect_pci(hose,
	211	EBONY_PCI_CFGA_PLB32,
	212	EBONY_PCI_CFGD_PLB32);
	213	hose->set_cfg_type = 1;
	214
	215	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
	216
	217	ppc_md.pci_swizzle = common_swizzle;
	218	ppc_md.pci_map_irq = ebony_map_irq;
	219	}
	220
	221	TODC_ALLOC();
	222
	223	static void __init
	224	ebony_early_serial_map(void)
	225	{
	226	struct uart_port port;
	227
	228	/* Setup ioremapped serial port access */
	229	memset(&port, 0, sizeof(port));
	230	port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
	231	port.irq = 0;
	232	port.uartclk = clocks.uart0;
	233	port.regshift = 0;
	234	port.iotype = SERIAL_IO_MEM;
	235	port.flags = ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST;
	236	port.line = 0;
	237
	238	if (early_serial_setup(&port) != 0) {
	239	printk("Early serial init of port 0 failed\n");
	240	}
	241
	242	#if defined(CONFIG_SERIAL_TEXT_DEBUG) \|\| defined(CONFIG_KGDB)
	243	/* Configure debug serial access */
	244	gen550_init(0, &port);
5ce17b18 ES	245
	246	/* Purge TLB entry added in head_44x.S for early serial access */
	247	_tlbie(UART0_IO_BASE);
1da177e4 LT	248	#endif
	249
	250	port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
	251	port.irq = 1;
	252	port.uartclk = clocks.uart1;
	253	port.line = 1;
	254
	255	if (early_serial_setup(&port) != 0) {
	256	printk("Early serial init of port 1 failed\n");
	257	}
	258
	259	#if defined(CONFIG_SERIAL_TEXT_DEBUG) \|\| defined(CONFIG_KGDB)
	260	/* Configure debug serial access */
	261	gen550_init(1, &port);
	262	#endif
	263	}
	264
	265	static void __init
	266	ebony_setup_arch(void)
	267	{
	268	struct ocp_def *def;
	269	struct ocp_func_emac_data *emacdata;
	270
	271	/* Set mac_addr for each EMAC */
	272	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
	273	emacdata = def->additions;
	274	emacdata->phy_map = 0x00000001; /* Skip 0x00 */
	275	emacdata->phy_mode = PHY_MODE_RMII;
	276	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
	277
	278	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
	279	emacdata = def->additions;
	280	emacdata->phy_map = 0x00000001; /* Skip 0x00 */
	281	emacdata->phy_mode = PHY_MODE_RMII;
	282	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
	283
	284	/*
	285	* Determine various clocks.
	286	* To be completely correct we should get SysClk
	287	* from FPGA, because it can be changed by on-board switches
	288	* --ebs
	289	*/
	290	ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
	291	ocp_sys_info.opb_bus_freq = clocks.opb;
	292
	293	/* Setup TODC access */
	294	TODC_INIT(TODC_TYPE_DS1743,
	295	0,
	296	0,
	297	ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
	298	8);
	299
	300	/* init to some ~sane value until calibrate_delay() runs */
	301	loops_per_jiffy = 50000000/HZ;
	302
	303	/* Setup PCI host bridge */
	304	ebony_setup_hose();
	305
	306	#ifdef CONFIG_BLK_DEV_INITRD
	307	if (initrd_start)
	308	ROOT_DEV = Root_RAM0;
	309	else
	310	#endif
	311	#ifdef CONFIG_ROOT_NFS
312	ROOT_DEV = Root_NFS;
313	#else
314	ROOT_DEV = Root_HDA1;
315	#endif
316
317	ebony_early_serial_map();
318
319	/* Identify the system */
320	printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
321	}
322
323	void __init platform_init(unsigned long r3, unsigned long r4,
324	unsigned long r5, unsigned long r6, unsigned long r7)
325	{
326	parse_bootinfo(find_bootinfo());
327
328	/*
329	* If we were passed in a board information, copy it into the
330	* residual data area.
331	*/
332	if (r3)
333	__res = (bd_t )(r3 + KERNELBASE);
334
335	ibm44x_platform_init();
336
337	ppc_md.setup_arch = ebony_setup_arch;
338	ppc_md.show_cpuinfo = ebony_show_cpuinfo;
339	ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
340
341	ppc_md.calibrate_decr = ebony_calibrate_decr;
342	ppc_md.time_init = todc_time_init;
343	ppc_md.set_rtc_time = todc_set_rtc_time;
344	ppc_md.get_rtc_time = todc_get_rtc_time;
345
346	ppc_md.nvram_read_val = todc_direct_read_val;
347	ppc_md.nvram_write_val = todc_direct_write_val;
348	#ifdef CONFIG_KGDB
349	ppc_md.early_serial_map = ebony_early_serial_map;
350	#endif
351	}
352