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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Embedded Planet 405GP board |
3 | * http://www.embeddedplanet.com | |
4 | * | |
5 | * Author: Matthew Locke <mlocke@mvista.com> | |
6 | * | |
7 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/config.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <asm/system.h> | |
16 | #include <asm/pci-bridge.h> | |
17 | #include <asm/machdep.h> | |
18 | #include <asm/todc.h> | |
19 | #include <asm/ocp.h> | |
20 | #include <asm/ibm_ocp_pci.h> | |
21 | ||
22 | #undef DEBUG | |
23 | #ifdef DEBUG | |
24 | #define DBG(x...) printk(x) | |
25 | #else | |
26 | #define DBG(x...) | |
27 | #endif | |
28 | ||
29 | u8 *ep405_bcsr; | |
30 | u8 *ep405_nvram; | |
31 | ||
32 | static struct { | |
33 | u8 cpld_xirq_select; | |
34 | int pci_idsel; | |
35 | int irq; | |
36 | } ep405_devtable[] = { | |
37 | #ifdef CONFIG_EP405PC | |
38 | {0x07, 0x0E, 25}, /* EP405PC: USB */ | |
39 | #endif | |
40 | }; | |
41 | ||
42 | int __init | |
43 | ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
44 | { | |
45 | int i; | |
46 | ||
47 | /* AFAICT this is only called a few times during PCI setup, so | |
48 | performance is not critical */ | |
49 | for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) { | |
50 | if (idsel == ep405_devtable[i].pci_idsel) | |
51 | return ep405_devtable[i].irq; | |
52 | } | |
53 | return -1; | |
54 | }; | |
55 | ||
56 | void __init | |
57 | ep405_setup_arch(void) | |
58 | { | |
59 | ppc4xx_setup_arch(); | |
60 | ||
61 | ibm_ocp_set_emac(0, 0); | |
62 | ||
63 | if (__res.bi_nvramsize == 512*1024) { | |
64 | /* FIXME: we should properly handle NVRTCs of different sizes */ | |
65 | TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8); | |
66 | } | |
67 | } | |
68 | ||
69 | void __init | |
70 | bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) | |
71 | { | |
72 | unsigned int bar_response, bar; | |
73 | /* | |
74 | * Expected PCI mapping: | |
75 | * | |
76 | * PLB addr PCI memory addr | |
77 | * --------------------- --------------------- | |
78 | * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff | |
79 | * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff | |
80 | * | |
81 | * PLB addr PCI io addr | |
82 | * --------------------- --------------------- | |
83 | * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 | |
84 | * | |
85 | */ | |
86 | ||
87 | /* Disable region zero first */ | |
88 | out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); | |
89 | /* PLB starting addr, PCI: 0x80000000 */ | |
90 | out_le32((void *) &(pcip->pmm[0].la), 0x80000000); | |
91 | /* PCI start addr, 0x80000000 */ | |
92 | out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); | |
93 | /* 512MB range of PLB to PCI */ | |
94 | out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); | |
95 | /* Enable no pre-fetch, enable region */ | |
96 | out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - | |
97 | (PPC405_PCI_UPPER_MEM - | |
98 | PPC405_PCI_MEM_BASE)) | 0x01)); | |
99 | ||
100 | /* Disable region one */ | |
101 | out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); | |
102 | out_le32((void *) &(pcip->pmm[1].la), 0x00000000); | |
103 | out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); | |
104 | out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); | |
105 | out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); | |
106 | out_le32((void *) &(pcip->ptm1ms), 0x00000000); | |
107 | ||
108 | /* Disable region two */ | |
109 | out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); | |
110 | out_le32((void *) &(pcip->pmm[2].la), 0x00000000); | |
111 | out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); | |
112 | out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); | |
113 | out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); | |
114 | out_le32((void *) &(pcip->ptm2ms), 0x00000000); | |
115 | ||
116 | /* Configure PTM (PCI->PLB) region 1 */ | |
117 | out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */ | |
118 | /* Disable PTM region 2 */ | |
119 | out_le32((void *) &(pcip->ptm2ms), 0x00000000); | |
120 | ||
121 | /* Zero config bars */ | |
122 | for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { | |
123 | early_write_config_dword(hose, hose->first_busno, | |
124 | PCI_FUNC(hose->first_busno), bar, | |
125 | 0x00000000); | |
126 | early_read_config_dword(hose, hose->first_busno, | |
127 | PCI_FUNC(hose->first_busno), bar, | |
128 | &bar_response); | |
129 | DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", | |
130 | hose->first_busno, PCI_SLOT(hose->first_busno), | |
131 | PCI_FUNC(hose->first_busno), bar, bar_response); | |
132 | } | |
133 | /* end work arround */ | |
134 | } | |
135 | ||
136 | void __init | |
137 | ep405_map_io(void) | |
138 | { | |
139 | bd_t *bip = &__res; | |
140 | ||
141 | ppc4xx_map_io(); | |
142 | ||
143 | ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE); | |
144 | ||
145 | if (bip->bi_nvramsize > 0) { | |
146 | ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize); | |
147 | } | |
148 | } | |
149 | ||
150 | void __init | |
151 | ep405_init_IRQ(void) | |
152 | { | |
153 | int i; | |
154 | ||
155 | ppc4xx_init_IRQ(); | |
156 | ||
157 | /* Workaround for a bug in the firmware it incorrectly sets | |
158 | the IRQ polarities for XIRQ0 and XIRQ1 */ | |
159 | mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */ | |
160 | mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */ | |
161 | ||
162 | /* Activate the XIRQs from the CPLD */ | |
163 | writeb(0xf0, ep405_bcsr+10); | |
164 | ||
165 | /* Set up IRQ routing */ | |
166 | for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) { | |
167 | if ( (ep405_devtable[i].irq >= 25) | |
168 | && (ep405_devtable[i].irq) <= 31) { | |
169 | writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5); | |
170 | writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6); | |
171 | } | |
172 | } | |
173 | } | |
174 | ||
175 | void __init | |
176 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
177 | unsigned long r6, unsigned long r7) | |
178 | { | |
179 | ppc4xx_init(r3, r4, r5, r6, r7); | |
180 | ||
181 | ppc_md.setup_arch = ep405_setup_arch; | |
182 | ppc_md.setup_io_mappings = ep405_map_io; | |
183 | ppc_md.init_IRQ = ep405_init_IRQ; | |
184 | ||
185 | ppc_md.nvram_read_val = todc_direct_read_val; | |
186 | ppc_md.nvram_write_val = todc_direct_write_val; | |
187 | ||
188 | if (__res.bi_nvramsize == 512*1024) { | |
189 | ppc_md.time_init = todc_time_init; | |
190 | ppc_md.set_rtc_time = todc_set_rtc_time; | |
191 | ppc_md.get_rtc_time = todc_get_rtc_time; | |
192 | } else { | |
193 | printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n"); | |
194 | } | |
195 | } |