projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * arch/ppc/platforms/4xx/ibm405gpr.c | |
| 3 | * | |
| 4 | * Author: Armin Kuster <akuster@mvista.com> | |
| 5 | * | |
| 6 | * 2002 (c) MontaVista, Software, Inc. This file is licensed under | |
| 7 | * the terms of the GNU General Public License version 2. This program | |
| 8 | * is licensed "as is" without any warranty of any kind, whether express | |
| 9 | * or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/config.h> | |
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/smp.h> | |
| 15 | #include <linux/threads.h> | |
| 16 | #include <linux/param.h> | |
| 17 | #include <linux/string.h> | |
| 18 | #include <platforms/4xx/ibm405gpr.h> | |
| 19 | #include <asm/ibm4xx.h> | |
| 20 | #include <asm/ocp.h> | |
| 21 | #include <asm/ppc4xx_pic.h> | |
| 22 | ||
| 23 | static struct ocp_func_emac_data ibm405gpr_emac0_def = { | |
| 24 | .rgmii_idx = -1, /* No RGMII */ | |
| 25 | .rgmii_mux = -1, /* No RGMII */ | |
| 26 | .zmii_idx = -1, /* ZMII device index */ | |
| 27 | .zmii_mux = 0, /* ZMII input of this EMAC */ | |
| 28 | .mal_idx = 0, /* MAL device index */ | |
| 29 | .mal_rx_chan = 0, /* MAL rx channel number */ | |
| 30 | .mal_tx_chan = 0, /* MAL tx channel number */ | |
| 31 | .wol_irq = 9, /* WOL interrupt number */ | |
| 32 | .mdio_idx = -1, /* No shared MDIO */ | |
| 33 | .tah_idx = -1, /* No TAH */ | |
| 34 | }; | |
| 35 | OCP_SYSFS_EMAC_DATA() | |
| 36 | ||
| 37 | static struct ocp_func_mal_data ibm405gpr_mal0_def = { | |
| 38 | .num_tx_chans = 1, /* Number of TX channels */ | |
| 39 | .num_rx_chans = 1, /* Number of RX channels */ | |
| 40 | .txeob_irq = 11, /* TX End Of Buffer IRQ */ | |
| 41 | .rxeob_irq = 12, /* RX End Of Buffer IRQ */ | |
| 42 | .txde_irq = 13, /* TX Descriptor Error IRQ */ | |
| 43 | .rxde_irq = 14, /* RX Descriptor Error IRQ */ | |
| 44 | .serr_irq = 10, /* MAL System Error IRQ */ | |
| 3a0a401b | 45 | .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ |
| 1da177e4 LT |
46 | }; |
| 47 | OCP_SYSFS_MAL_DATA() | |
| 48 | ||
| 49 | static struct ocp_func_iic_data ibm405gpr_iic0_def = { | |
| 50 | .fast_mode = 0, /* Use standad mode (100Khz) */ | |
| 51 | }; | |
| 52 | ||
| 53 | OCP_SYSFS_IIC_DATA() | |
| 54 | ||
| 55 | struct ocp_def core_ocp[] = { | |
| 56 | { .vendor = OCP_VENDOR_IBM, | |
| 57 | .function = OCP_FUNC_OPB, | |
| 58 | .index = 0, | |
| 59 | .paddr = 0xEF600000, | |
| 60 | .irq = OCP_IRQ_NA, | |
| 61 | .pm = OCP_CPM_NA, | |
| 62 | }, | |
| 63 | { .vendor = OCP_VENDOR_IBM, | |
| 64 | .function = OCP_FUNC_16550, | |
| 65 | .index = 0, | |
| 66 | .paddr = UART0_IO_BASE, | |
| 67 | .irq = UART0_INT, | |
| 68 | .pm = IBM_CPM_UART0 | |
| 69 | }, | |
| 70 | { .vendor = OCP_VENDOR_IBM, | |
| 71 | .function = OCP_FUNC_16550, | |
| 72 | .index = 1, | |
| 73 | .paddr = UART1_IO_BASE, | |
| 74 | .irq = UART1_INT, | |
| 75 | .pm = IBM_CPM_UART1 | |
| 76 | }, | |
| 77 | { .vendor = OCP_VENDOR_IBM, | |
| 78 | .function = OCP_FUNC_IIC, | |
| 79 | .paddr = 0xEF600500, | |
| 80 | .irq = 2, | |
| 81 | .pm = IBM_CPM_IIC0, | |
| 82 | .additions = &ibm405gpr_iic0_def, | |
| 83 | .show = &ocp_show_iic_data, | |
| 84 | }, | |
| 85 | { .vendor = OCP_VENDOR_IBM, | |
| 86 | .function = OCP_FUNC_GPIO, | |
| 87 | .paddr = 0xEF600700, | |
| 88 | .irq = OCP_IRQ_NA, | |
| 89 | .pm = IBM_CPM_GPIO0 | |
| 90 | }, | |
| 91 | { .vendor = OCP_VENDOR_IBM, | |
| 92 | .function = OCP_FUNC_MAL, | |
| 93 | .paddr = OCP_PADDR_NA, | |
| 94 | .irq = OCP_IRQ_NA, | |
| 95 | .pm = OCP_CPM_NA, | |
| 96 | .additions = &ibm405gpr_mal0_def, | |
| 97 | .show = &ocp_show_mal_data, | |
| 98 | }, | |
| 99 | { .vendor = OCP_VENDOR_IBM, | |
| 100 | .function = OCP_FUNC_EMAC, | |
| 101 | .index = 0, | |
| 102 | .paddr = EMAC0_BASE, | |
| 103 | .irq = 15, | |
| 104 | .pm = IBM_CPM_EMAC0, | |
| 105 | .additions = &ibm405gpr_emac0_def, | |
| 106 | .show = &ocp_show_emac_data, | |
| 107 | }, | |
| 108 | { .vendor = OCP_VENDOR_INVALID | |
| 109 | } | |
| 110 | }; | |
| 111 | ||
| 112 | /* Polarity and triggering settings for internal interrupt sources */ | |
| 113 | struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { | |
| 114 | { .polarity = 0xffffe000, | |
| 115 | .triggering = 0x10000000, | |
| 116 | .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */ | |
| 117 | } | |
| 118 | }; |