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1da177e4 LT |
1 | /* |
2 | * arch/ppc/platforms/4xx/ocotea.c | |
3 | * | |
4 | * Ocotea board specific routines | |
5 | * | |
6 | * Matt Porter <mporter@kernel.crashing.org> | |
7 | * | |
8 | * Copyright 2003-2005 MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/stddef.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/reboot.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/kdev_t.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/major.h> | |
26 | #include <linux/blkdev.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/ide.h> | |
30 | #include <linux/initrd.h> | |
1da177e4 LT |
31 | #include <linux/seq_file.h> |
32 | #include <linux/root_dev.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/serial_core.h> | |
36 | ||
37 | #include <asm/system.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/page.h> | |
40 | #include <asm/dma.h> | |
41 | #include <asm/io.h> | |
42 | #include <asm/machdep.h> | |
43 | #include <asm/ocp.h> | |
44 | #include <asm/pci-bridge.h> | |
45 | #include <asm/time.h> | |
46 | #include <asm/todc.h> | |
47 | #include <asm/bootinfo.h> | |
48 | #include <asm/ppc4xx_pic.h> | |
49 | #include <asm/ppcboot.h> | |
5ce17b18 | 50 | #include <asm/tlbflush.h> |
1da177e4 LT |
51 | |
52 | #include <syslib/gen550.h> | |
53 | #include <syslib/ibm440gx_common.h> | |
54 | ||
d5f7b06b | 55 | extern bd_t __res; |
1da177e4 LT |
56 | |
57 | static struct ibm44x_clocks clocks __initdata; | |
58 | ||
59 | static void __init | |
60 | ocotea_calibrate_decr(void) | |
61 | { | |
62 | unsigned int freq; | |
63 | ||
64 | if (mfspr(SPRN_CCR1) & CCR1_TCS) | |
65 | freq = OCOTEA_TMR_CLK; | |
66 | else | |
67 | freq = clocks.cpu; | |
68 | ||
69 | ibm44x_calibrate_decr(freq); | |
70 | } | |
71 | ||
72 | static int | |
73 | ocotea_show_cpuinfo(struct seq_file *m) | |
74 | { | |
75 | seq_printf(m, "vendor\t\t: IBM\n"); | |
76 | seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n"); | |
77 | ibm440gx_show_cpuinfo(m); | |
78 | return 0; | |
79 | } | |
80 | ||
81 | static inline int | |
82 | ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
83 | { | |
84 | static char pci_irq_table[][4] = | |
85 | /* | |
86 | * PCI IDSEL/INTPIN->INTLINE | |
87 | * A B C D | |
88 | */ | |
89 | { | |
90 | { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ | |
91 | { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ | |
92 | { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ | |
93 | { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ | |
94 | }; | |
95 | ||
96 | const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; | |
97 | return PCI_IRQ_TABLE_LOOKUP; | |
98 | } | |
99 | ||
100 | static void __init ocotea_set_emacdata(void) | |
101 | { | |
102 | struct ocp_def *def; | |
103 | struct ocp_func_emac_data *emacdata; | |
104 | int i; | |
105 | ||
106 | /* | |
107 | * Note: Current rev. board only operates in Group 4a | |
108 | * mode, so we always set EMAC0-1 for SMII and EMAC2-3 | |
109 | * for RGMII (though these could run in RTBI just the same). | |
110 | * | |
111 | * The FPGA reg 3 information isn't even suitable for | |
112 | * determining the phy_mode, so if the board becomes | |
113 | * usable in !4a, it will be necessary to parse an environment | |
114 | * variable from the firmware or similar to properly configure | |
115 | * the phy_map/phy_mode. | |
116 | */ | |
117 | /* Set phy_map, phy_mode, and mac_addr for each EMAC */ | |
118 | for (i=0; i<4; i++) { | |
119 | def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); | |
120 | emacdata = def->additions; | |
121 | if (i < 2) { | |
122 | emacdata->phy_map = 0x00000001; /* Skip 0x00 */ | |
123 | emacdata->phy_mode = PHY_MODE_SMII; | |
124 | } | |
125 | else { | |
126 | emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */ | |
127 | emacdata->phy_mode = PHY_MODE_RGMII; | |
128 | } | |
129 | if (i == 0) | |
130 | memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); | |
131 | else if (i == 1) | |
132 | memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); | |
133 | else if (i == 2) | |
134 | memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6); | |
135 | else if (i == 3) | |
136 | memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6); | |
137 | } | |
138 | } | |
139 | ||
140 | #define PCIX_READW(offset) \ | |
141 | (readw(pcix_reg_base+offset)) | |
142 | ||
143 | #define PCIX_WRITEW(value, offset) \ | |
144 | (writew(value, pcix_reg_base+offset)) | |
145 | ||
146 | #define PCIX_WRITEL(value, offset) \ | |
147 | (writel(value, pcix_reg_base+offset)) | |
148 | ||
149 | /* | |
150 | * FIXME: This is only here to "make it work". This will move | |
151 | * to a ibm_pcix.c which will contain a generic IBM PCIX bridge | |
152 | * configuration library. -Matt | |
153 | */ | |
154 | static void __init | |
155 | ocotea_setup_pcix(void) | |
156 | { | |
157 | void *pcix_reg_base; | |
158 | ||
159 | pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); | |
160 | ||
161 | /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ | |
162 | PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); | |
163 | ||
164 | /* Disable all windows */ | |
165 | PCIX_WRITEL(0, PCIX0_POM0SA); | |
166 | PCIX_WRITEL(0, PCIX0_POM1SA); | |
167 | PCIX_WRITEL(0, PCIX0_POM2SA); | |
168 | PCIX_WRITEL(0, PCIX0_PIM0SA); | |
169 | PCIX_WRITEL(0, PCIX0_PIM0SAH); | |
170 | PCIX_WRITEL(0, PCIX0_PIM1SA); | |
171 | PCIX_WRITEL(0, PCIX0_PIM2SA); | |
172 | PCIX_WRITEL(0, PCIX0_PIM2SAH); | |
173 | ||
174 | /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ | |
175 | PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); | |
176 | PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); | |
177 | PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); | |
178 | PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); | |
179 | PCIX_WRITEL(0x80000001, PCIX0_POM0SA); | |
180 | ||
181 | /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ | |
182 | PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); | |
183 | PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); | |
184 | PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); | |
185 | ||
186 | eieio(); | |
187 | } | |
188 | ||
189 | static void __init | |
190 | ocotea_setup_hose(void) | |
191 | { | |
192 | struct pci_controller *hose; | |
193 | ||
194 | /* Configure windows on the PCI-X host bridge */ | |
195 | ocotea_setup_pcix(); | |
196 | ||
197 | hose = pcibios_alloc_controller(); | |
198 | ||
199 | if (!hose) | |
200 | return; | |
201 | ||
202 | hose->first_busno = 0; | |
203 | hose->last_busno = 0xff; | |
204 | ||
205 | hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET; | |
206 | ||
207 | pci_init_resource(&hose->io_resource, | |
208 | OCOTEA_PCI_LOWER_IO, | |
209 | OCOTEA_PCI_UPPER_IO, | |
210 | IORESOURCE_IO, | |
211 | "PCI host bridge"); | |
212 | ||
213 | pci_init_resource(&hose->mem_resources[0], | |
214 | OCOTEA_PCI_LOWER_MEM, | |
215 | OCOTEA_PCI_UPPER_MEM, | |
216 | IORESOURCE_MEM, | |
217 | "PCI host bridge"); | |
218 | ||
219 | hose->io_space.start = OCOTEA_PCI_LOWER_IO; | |
220 | hose->io_space.end = OCOTEA_PCI_UPPER_IO; | |
221 | hose->mem_space.start = OCOTEA_PCI_LOWER_MEM; | |
222 | hose->mem_space.end = OCOTEA_PCI_UPPER_MEM; | |
92a11f9e AV |
223 | hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE); |
224 | isa_io_base = (unsigned long) hose->io_base_virt; | |
1da177e4 LT |
225 | |
226 | setup_indirect_pci(hose, | |
227 | OCOTEA_PCI_CFGA_PLB32, | |
228 | OCOTEA_PCI_CFGD_PLB32); | |
229 | hose->set_cfg_type = 1; | |
230 | ||
231 | hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); | |
232 | ||
233 | ppc_md.pci_swizzle = common_swizzle; | |
234 | ppc_md.pci_map_irq = ocotea_map_irq; | |
235 | } | |
236 | ||
237 | ||
238 | TODC_ALLOC(); | |
239 | ||
240 | static void __init | |
241 | ocotea_early_serial_map(void) | |
242 | { | |
243 | struct uart_port port; | |
244 | ||
245 | /* Setup ioremapped serial port access */ | |
246 | memset(&port, 0, sizeof(port)); | |
247 | port.membase = ioremap64(PPC440GX_UART0_ADDR, 8); | |
248 | port.irq = UART0_INT; | |
249 | port.uartclk = clocks.uart0; | |
250 | port.regshift = 0; | |
9b4a1617 | 251 | port.iotype = UPIO_MEM; |
59a675b2 | 252 | port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; |
1da177e4 LT |
253 | port.line = 0; |
254 | ||
255 | if (early_serial_setup(&port) != 0) { | |
256 | printk("Early serial init of port 0 failed\n"); | |
257 | } | |
258 | ||
259 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | |
260 | /* Configure debug serial access */ | |
261 | gen550_init(0, &port); | |
5ce17b18 ES |
262 | |
263 | /* Purge TLB entry added in head_44x.S for early serial access */ | |
264 | _tlbie(UART0_IO_BASE); | |
1da177e4 LT |
265 | #endif |
266 | ||
267 | port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); | |
268 | port.irq = UART1_INT; | |
269 | port.uartclk = clocks.uart1; | |
270 | port.line = 1; | |
271 | ||
272 | if (early_serial_setup(&port) != 0) { | |
273 | printk("Early serial init of port 1 failed\n"); | |
274 | } | |
275 | ||
276 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | |
277 | /* Configure debug serial access */ | |
278 | gen550_init(1, &port); | |
279 | #endif | |
280 | } | |
281 | ||
282 | static void __init | |
283 | ocotea_setup_arch(void) | |
284 | { | |
285 | ocotea_set_emacdata(); | |
286 | ||
287 | ibm440gx_tah_enable(); | |
288 | ||
d5f7b06b MP |
289 | /* |
290 | * Determine various clocks. | |
291 | * To be completely correct we should get SysClk | |
292 | * from FPGA, because it can be changed by on-board switches | |
293 | * --ebs | |
294 | */ | |
295 | ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); | |
296 | ocp_sys_info.opb_bus_freq = clocks.opb; | |
297 | ||
1da177e4 LT |
298 | /* Setup TODC access */ |
299 | TODC_INIT(TODC_TYPE_DS1743, | |
300 | 0, | |
301 | 0, | |
302 | ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE), | |
303 | 8); | |
304 | ||
305 | /* init to some ~sane value until calibrate_delay() runs */ | |
306 | loops_per_jiffy = 50000000/HZ; | |
307 | ||
308 | /* Setup PCI host bridge */ | |
309 | ocotea_setup_hose(); | |
310 | ||
311 | #ifdef CONFIG_BLK_DEV_INITRD | |
312 | if (initrd_start) | |
313 | ROOT_DEV = Root_RAM0; | |
314 | else | |
315 | #endif | |
316 | #ifdef CONFIG_ROOT_NFS | |
317 | ROOT_DEV = Root_NFS; | |
318 | #else | |
319 | ROOT_DEV = Root_HDA1; | |
320 | #endif | |
321 | ||
322 | ocotea_early_serial_map(); | |
323 | ||
324 | /* Identify the system */ | |
325 | printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n"); | |
326 | } | |
327 | ||
328 | static void __init ocotea_init(void) | |
329 | { | |
330 | ibm440gx_l2c_setup(&clocks); | |
331 | } | |
332 | ||
333 | void __init platform_init(unsigned long r3, unsigned long r4, | |
334 | unsigned long r5, unsigned long r6, unsigned long r7) | |
335 | { | |
d5f7b06b | 336 | ibm44x_platform_init(r3, r4, r5, r6, r7); |
1da177e4 LT |
337 | |
338 | ppc_md.setup_arch = ocotea_setup_arch; | |
339 | ppc_md.show_cpuinfo = ocotea_show_cpuinfo; | |
340 | ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ | |
341 | ||
342 | ppc_md.calibrate_decr = ocotea_calibrate_decr; | |
343 | ppc_md.time_init = todc_time_init; | |
344 | ppc_md.set_rtc_time = todc_set_rtc_time; | |
345 | ppc_md.get_rtc_time = todc_get_rtc_time; | |
346 | ||
347 | ppc_md.nvram_read_val = todc_direct_read_val; | |
348 | ppc_md.nvram_write_val = todc_direct_write_val; | |
349 | #ifdef CONFIG_KGDB | |
350 | ppc_md.early_serial_map = ocotea_early_serial_map; | |
351 | #endif | |
352 | ppc_md.init = ocotea_init; | |
353 | } |