[mirror_ubuntu-artful-kernel.git] / arch / ppc / platforms / cpci690.c

/*
 * Board setup routines for the Force CPCI690 board.
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This programr
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/irq.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/console.h>
#include <linux/initrd.h>
#include <linux/root_dev.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include <asm/bootinfo.h>
#include <asm/machdep.h>
#include <asm/todc.h>
#include <asm/time.h>
#include <asm/mv64x60.h>
#include <platforms/cpci690.h>

#define BOARD_VENDOR	"Force"
#define BOARD_MACHINE	"CPCI690"

/* Set IDE controllers into Native mode? */
#define SET_PCI_IDE_NATIVE

static struct mv64x60_handle	bh;
static void __iomem *cpci690_br_base;

TODC_ALLOC();

static int __init
cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);

	if (hose->index == 0) {
		static char pci_irq_table[][4] =
		/*
		 *	PCI IDSEL/INTPIN->INTLINE
		 * 	   A   B   C   D
		 */
		{
			{ 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */
		};

		const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
		return PCI_IRQ_TABLE_LOOKUP;
	} else {
		static char pci_irq_table[][4] =
		/*
		 *	PCI IDSEL/INTPIN->INTLINE
		 * 	   A   B   C   D
		 */
		{
			{ 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */
			{  0,  0,  0,  0 }, /* IDSEL 29/19 - Not used */
			{ 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */
		};

		const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
		return PCI_IRQ_TABLE_LOOKUP;
	}
}

#define	GB	(1024UL * 1024UL * 1024UL)

static u32
cpci690_get_bus_freq(void)
{
	if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */
		return 100000000;
	else
		return 133333333;
}

static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
	 0,  0,  2,  2,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,/* 0-15*/
	16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40,  0 /*16-31*/
};

static int
cpci690_get_cpu_freq(void)
{
	unsigned long	pll_cfg;

	pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
	return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2;
}

static void __init
cpci690_setup_bridge(void)
{
	struct mv64x60_setup_info	si;
	int				i;

	memset(&si, 0, sizeof(si));

	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;

	si.pci_0.enable_bus = 1;
	si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
	si.pci_0.pci_io.pci_base_hi = 0;
	si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
	si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
	si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
	si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
	si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_0.pci_cmd_bits = 0;
	si.pci_0.latency_timer = 0x80;

	si.pci_1.enable_bus = 1;
	si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
	si.pci_1.pci_io.pci_base_hi = 0;
	si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
	si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
	si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
	si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
	si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_cmd_bits = 0;
	si.pci_1.latency_timer = 0x80;

	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
		si.cpu_prot_options[i] = 0;
		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
		si.pci_0.acc_cntl_options[i] =
			GT64260_PCI_ACC_CNTL_DREADEN |
			GT64260_PCI_ACC_CNTL_RDPREFETCH |
			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
			GT64260_PCI_ACC_CNTL_SWAP_NONE |
			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
		si.pci_1.acc_cntl_options[i] =
			GT64260_PCI_ACC_CNTL_DREADEN |
			GT64260_PCI_ACC_CNTL_RDPREFETCH |
			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
			GT64260_PCI_ACC_CNTL_SWAP_NONE |
			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
	}

        /* Lookup PCI host bridges */
        if (mv64x60_init(&bh, &si))
                printk(KERN_ERR "Bridge initialization failed.\n");

	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = cpci690_map_irq;
	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;

	mv64x60_set_bus(&bh, 0, 0);
	bh.hose_a->first_busno = 0;
	bh.hose_a->last_busno = 0xff;
	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);

	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
	bh.hose_b->last_busno = 0xff;
	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
		bh.hose_b->first_busno);
}

static void __init
cpci690_setup_peripherals(void)
{
	/* Set up windows to CPLD, RTC/TODC, IPMI. */
	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
		CPCI690_BR_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
	cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
		CPCI690_TODC_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
	TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
			ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
		CPCI690_IPMI_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);

	mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
	mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));

        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */

	/*
	 * Turn off timer/counters.  Not turning off watchdog timer because
	 * can't read its reg on the 64260A so don't know if we'll be enabling
	 * or disabling.
	 */
	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
			((1<<0) | (1<<8) | (1<<16) | (1<<24)));

	/*
	 * Set MPSC Multiplex RMII
	 * NOTE: ethernet driver modifies bit 0 and 1
	 */
	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);

#define GPP_EXTERNAL_INTERRUPTS \
		((1<<24) | (1<<25) | (1<<26) | (1<<27) | \
		 (1<<28) | (1<<29) | (1<<30) | (1<<31))
	/* PCI interrupts are inputs */
	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
	/* PCI interrupts are active low */
	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);

	/* Clear any pending interrupts for these inputs and enable them. */
	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);

	/* Route MPP interrupt inputs to GPP */
	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
	mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
}

static void __init
cpci690_setup_arch(void)
{
	if (ppc_md.progress)
		ppc_md.progress("cpci690_setup_arch: enter", 0);
#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
#ifdef   CONFIG_ROOT_NFS
		ROOT_DEV = Root_NFS;
#else
		ROOT_DEV = Root_SDA2;
#endif

	if (ppc_md.progress)
		ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);

	/* Enable L2 and L3 caches (if 745x) */
	_set_L2CR(_get_L2CR() | L2CR_L2E);
	_set_L3CR(_get_L3CR() | L3CR_L3E);

	if (ppc_md.progress)
		ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);

	cpci690_setup_bridge();		/* set up PCI bridge(s) */
	cpci690_setup_peripherals();	/* set up chip selects/GPP/MPP etc */

	if (ppc_md.progress)
		ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);

	printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
		"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);

	if (ppc_md.progress)
		ppc_md.progress("cpci690_setup_arch: exit", 0);
}

/* Platform device data fixup routines. */
#if defined(CONFIG_SERIAL_MPSC)
static void __init
cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
{
	struct mpsc_pdata *pdata;

	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;

	pdata->max_idle = 40;
	pdata->default_baud = CPCI690_MPSC_BAUD;
	pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
	pdata->brg_clk_freq = cpci690_get_bus_freq();
}

static int __init
cpci690_platform_notify(struct device *dev)
{
	static struct {
		char	*bus_id;
		void	((*rtn)(struct platform_device *pdev));
	} dev_map[] = {
		{ MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
		{ MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
	};
	struct platform_device	*pdev;
	int	i;

	if (dev && dev->bus_id)
		for (i=0; i<ARRAY_SIZE(dev_map); i++)
			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
				BUS_ID_SIZE)) {

				pdev = container_of(dev,
					struct platform_device, dev);
				dev_map[i].rtn(pdev);
			}

	return 0;
}
#endif

static void
cpci690_reset_board(void)
{
	u32	i = 10000;

	local_irq_disable();
	out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);

	while (i != 0) i++;
	panic("restart failed\n");
}

static void
cpci690_restart(char *cmd)
{
	cpci690_reset_board();
}

static void
cpci690_halt(void)
{
	while (1);
	/* NOTREACHED */
}

static void
cpci690_power_off(void)
{
	cpci690_halt();
	/* NOTREACHED */
}

static int
cpci690_show_cpuinfo(struct seq_file *m)
{
	char	*s;

	seq_printf(m, "cpu MHz\t\t: %d\n",
		(cpci690_get_cpu_freq() + 500000) / 1000000);
	seq_printf(m, "bus MHz\t\t: %d\n",
		(cpci690_get_bus_freq() + 500000) / 1000000);
	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
	seq_printf(m, "FPGA Revision\t: %d\n",
		in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);

	switch(bh.type) {
	case MV64x60_TYPE_GT64260A:
		s = "gt64260a";
		break;
	case MV64x60_TYPE_GT64260B:
		s = "gt64260b";
		break;
	case MV64x60_TYPE_MV64360:
		s = "mv64360";
		break;
	case MV64x60_TYPE_MV64460:
		s = "mv64460";
		break;
	default:
		s = "Unknown";
	}
	seq_printf(m, "bridge type\t: %s\n", s);
	seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
#if defined(CONFIG_NOT_COHERENT_CACHE)
	seq_printf(m, "coherency\t: %s\n", "off");
#else
	seq_printf(m, "coherency\t: %s\n", "on");
#endif

	return 0;
}

static void __init
cpci690_calibrate_decr(void)
{
	ulong freq;

	freq = cpci690_get_bus_freq() / 4;

	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
	       freq/1000000, freq%1000000);

	tb_ticks_per_jiffy = freq / HZ;
	tb_to_us = mulhwu_scale_factor(freq, 1000000);
}

#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
static void __init
cpci690_map_io(void)
{
	io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
		128 * 1024, _PAGE_IO);
}
#endif

void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
	      unsigned long r6, unsigned long r7)
{
	parse_bootinfo(find_bootinfo());

#ifdef CONFIG_BLK_DEV_INITRD
	/* take care of initrd if we have one */
	if (r4) {
		initrd_start = r4 + KERNELBASE;
		initrd_end = r5 + KERNELBASE;
	}
#endif /* CONFIG_BLK_DEV_INITRD */

	isa_mem_base = 0;

	ppc_md.setup_arch = cpci690_setup_arch;
	ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
	ppc_md.init_IRQ = gt64260_init_irq;
	ppc_md.get_irq = gt64260_get_irq;
	ppc_md.restart = cpci690_restart;
	ppc_md.power_off = cpci690_power_off;
	ppc_md.halt = cpci690_halt;
	ppc_md.time_init = todc_time_init;
	ppc_md.set_rtc_time = todc_set_rtc_time;
	ppc_md.get_rtc_time = todc_get_rtc_time;
	ppc_md.nvram_read_val = todc_direct_read_val;
	ppc_md.nvram_write_val = todc_direct_write_val;
	ppc_md.calibrate_decr = cpci690_calibrate_decr;

#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
	ppc_md.setup_io_mappings = cpci690_map_io;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
	ppc_md.progress = mv64x60_mpsc_progress;
	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
#endif	/* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */

#if defined(CONFIG_SERIAL_MPSC)
	platform_notify = cpci690_platform_notify;
#endif
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Board setup routines for the Force CPCI690 board.
	3	*
	4	* Author: Mark A. Greer <mgreer@mvista.com>
	5	*
	6	* 2003 (c) MontaVista Software, Inc. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This programr
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/config.h>
	12	#include <linux/delay.h>
	13	#include <linux/pci.h>
	14	#include <linux/ide.h>
	15	#include <linux/irq.h>
	16	#include <linux/fs.h>
	17	#include <linux/seq_file.h>
	18	#include <linux/console.h>
	19	#include <linux/initrd.h>
	20	#include <linux/root_dev.h>
	21	#include <linux/mv643xx.h>
d052d1be	22	#include <linux/platform_device.h>
1da177e4 LT	23	#include <asm/bootinfo.h>
	24	#include <asm/machdep.h>
	25	#include <asm/todc.h>
	26	#include <asm/time.h>
	27	#include <asm/mv64x60.h>
	28	#include <platforms/cpci690.h>
	29
	30	#define BOARD_VENDOR "Force"
	31	#define BOARD_MACHINE "CPCI690"
	32
	33	/* Set IDE controllers into Native mode? */
	34	#define SET_PCI_IDE_NATIVE
	35
	36	static struct mv64x60_handle bh;
f54bef9e	37	static void __iomem *cpci690_br_base;
1da177e4 LT	38
	39	TODC_ALLOC();
	40
	41	static int __init
	42	cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
	43	{
	44	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
	45
	46	if (hose->index == 0) {
	47	static char pci_irq_table[][4] =
	48	/*
	49	* PCI IDSEL/INTPIN->INTLINE
	50	* A B C D
	51	*/
	52	{
f54bef9e	53	{ 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */
1da177e4 LT	54	};
	55
	56	const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
	57	return PCI_IRQ_TABLE_LOOKUP;
	58	} else {
	59	static char pci_irq_table[][4] =
	60	/*
	61	* PCI IDSEL/INTPIN->INTLINE
	62	* A B C D
	63	*/
	64	{
f54bef9e MG	65	{ 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */
	66	{ 0, 0, 0, 0 }, /* IDSEL 29/19 - Not used */
	67	{ 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */
1da177e4 LT	68	};
	69
	70	const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
	71	return PCI_IRQ_TABLE_LOOKUP;
	72	}
	73	}
	74
f54bef9e	75	#define GB (1024UL * 1024UL * 1024UL)
1da177e4	76
f54bef9e MG	77	static u32
	78	cpci690_get_bus_freq(void)
	79	{
	80	if (boot_mem_size >= (1GB)) / bus speed based on mem size */
	81	return 100000000;
	82	else
	83	return 133333333;
1da177e4 LT	84	}
1da177e4 LT	85
f54bef9e MG	86	static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
	87	0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
	88	16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /16-31/
	89	};
1da177e4	90
f54bef9e MG	91	static int
f54bef9e MG	92	cpci690_get_cpu_freq(void)
1da177e4	93	{
f54bef9e MG	94	unsigned long pll_cfg;
	95
	96	pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
	97	return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2;
1da177e4 LT	98	}
	99
	100	static void __init
	101	cpci690_setup_bridge(void)
	102	{
	103	struct mv64x60_setup_info si;
	104	int i;
	105
	106	memset(&si, 0, sizeof(si));
	107
	108	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
	109
	110	si.pci_0.enable_bus = 1;
	111	si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
	112	si.pci_0.pci_io.pci_base_hi = 0;
	113	si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
	114	si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
	115	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	116	si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
	117	si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
	118	si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
	119	si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
	120	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	121	si.pci_0.pci_cmd_bits = 0;
	122	si.pci_0.latency_timer = 0x80;
	123
	124	si.pci_1.enable_bus = 1;
	125	si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
	126	si.pci_1.pci_io.pci_base_hi = 0;
	127	si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
	128	si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
	129	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	130	si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
	131	si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
	132	si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
	133	si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
	134	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	135	si.pci_1.pci_cmd_bits = 0;
	136	si.pci_1.latency_timer = 0x80;
	137
	138	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
	139	si.cpu_prot_options[i] = 0;
	140	si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
	141	si.pci_0.acc_cntl_options[i] =
	142	GT64260_PCI_ACC_CNTL_DREADEN \|
	143	GT64260_PCI_ACC_CNTL_RDPREFETCH \|
	144	GT64260_PCI_ACC_CNTL_RDLINEPREFETCH \|
	145	GT64260_PCI_ACC_CNTL_RDMULPREFETCH \|
	146	GT64260_PCI_ACC_CNTL_SWAP_NONE \|
	147	GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
	148	si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
	149	si.pci_1.acc_cntl_options[i] =
	150	GT64260_PCI_ACC_CNTL_DREADEN \|
	151	GT64260_PCI_ACC_CNTL_RDPREFETCH \|
	152	GT64260_PCI_ACC_CNTL_RDLINEPREFETCH \|
	153	GT64260_PCI_ACC_CNTL_RDMULPREFETCH \|
	154	GT64260_PCI_ACC_CNTL_SWAP_NONE \|
	155	GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
	156	si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
	157	}
	158
	159	/* Lookup PCI host bridges */
	160	if (mv64x60_init(&bh, &si))
	161	printk(KERN_ERR "Bridge initialization failed.\n");
162
163	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
164	ppc_md.pci_swizzle = common_swizzle;
165	ppc_md.pci_map_irq = cpci690_map_irq;
166	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
167
168	mv64x60_set_bus(&bh, 0, 0);
169	bh.hose_a->first_busno = 0;
170	bh.hose_a->last_busno = 0xff;
171	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
172
173	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
174	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
175	bh.hose_b->last_busno = 0xff;
176	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
177	bh.hose_b->first_busno);
178	}
179
180	static void __init
181	cpci690_setup_peripherals(void)
182	{
183	/* Set up windows to CPLD, RTC/TODC, IPMI. */
184	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
185	CPCI690_BR_SIZE, 0);
186	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
f54bef9e	187	cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
1da177e4 LT	188
	189	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
	190	CPCI690_TODC_SIZE, 0);
	191	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
	192	TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
	193	ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);
	194
	195	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
	196	CPCI690_IPMI_SIZE, 0);
	197	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
	198
	199	mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
	200	mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
	201
	202	mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
	203
	204	/*
	205	* Turn off timer/counters. Not turning off watchdog timer because
	206	* can't read its reg on the 64260A so don't know if we'll be enabling
	207	* or disabling.
	208	*/
	209	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
	210	((1<<0) \| (1<<8) \| (1<<16) \| (1<<24)));
	211	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
	212	((1<<0) \| (1<<8) \| (1<<16) \| (1<<24)));
	213
	214	/*
	215	* Set MPSC Multiplex RMII
	216	* NOTE: ethernet driver modifies bit 0 and 1
	217	*/
	218	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
	219
	220	#define GPP_EXTERNAL_INTERRUPTS \
	221	((1<<24) \| (1<<25) \| (1<<26) \| (1<<27) \| \
	222	(1<<28) \| (1<<29) \| (1<<30) \| (1<<31))
	223	/* PCI interrupts are inputs */
	224	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
	225	/* PCI interrupts are active low */
	226	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
	227
	228	/* Clear any pending interrupts for these inputs and enable them. */
	229	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
	230	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
	231
	232	/* Route MPP interrupt inputs to GPP */
	233	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
	234	mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
	235	}
	236
	237	static void __init
	238	cpci690_setup_arch(void)
	239	{
	240	if (ppc_md.progress)
	241	ppc_md.progress("cpci690_setup_arch: enter", 0);
	242	#ifdef CONFIG_BLK_DEV_INITRD
	243	if (initrd_start)
	244	ROOT_DEV = Root_RAM0;
	245	else
	246	#endif
	247	#ifdef CONFIG_ROOT_NFS
	248	ROOT_DEV = Root_NFS;
	249	#else
	250	ROOT_DEV = Root_SDA2;
	251	#endif
252
253	if (ppc_md.progress)
254	ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);
255
256	/* Enable L2 and L3 caches (if 745x) */
257	_set_L2CR(_get_L2CR() \| L2CR_L2E);
258	_set_L3CR(_get_L3CR() \| L3CR_L3E);
259
260	if (ppc_md.progress)
261	ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);
262
263	cpci690_setup_bridge(); /* set up PCI bridge(s) */
264	cpci690_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
265
266	if (ppc_md.progress)
267	ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);
268
269	printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
270	"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
271
272	if (ppc_md.progress)
273	ppc_md.progress("cpci690_setup_arch: exit", 0);
274	}
275
276	/* Platform device data fixup routines. */
277	#if defined(CONFIG_SERIAL_MPSC)
278	static void __init
279	cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
280	{
281	struct mpsc_pdata *pdata;
282
283	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
284
285	pdata->max_idle = 40;
286	pdata->default_baud = CPCI690_MPSC_BAUD;
287	pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
f54bef9e	288	pdata->brg_clk_freq = cpci690_get_bus_freq();
1da177e4 LT	289	}
	290
	291	static int __init
	292	cpci690_platform_notify(struct device *dev)
	293	{
	294	static struct {
	295	char *bus_id;
	296	void ((rtn)(struct platform_device pdev));
	297	} dev_map[] = {
	298	{ MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
	299	{ MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
	300	};
	301	struct platform_device *pdev;
	302	int i;
	303
	304	if (dev && dev->bus_id)
	305	for (i=0; i<ARRAY_SIZE(dev_map); i++)
	306	if (!strncmp(dev->bus_id, dev_map[i].bus_id,
	307	BUS_ID_SIZE)) {
	308
	309	pdev = container_of(dev,
	310	struct platform_device, dev);
	311	dev_map[i].rtn(pdev);
	312	}
	313
	314	return 0;
	315	}
	316	#endif
	317
	318	static void
	319	cpci690_reset_board(void)
	320	{
	321	u32 i = 10000;
	322
	323	local_irq_disable();
f54bef9e	324	out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
1da177e4 LT	325
	326	while (i != 0) i++;
	327	panic("restart failed\n");
	328	}
	329
	330	static void
	331	cpci690_restart(char *cmd)
	332	{
	333	cpci690_reset_board();
	334	}
	335
	336	static void
	337	cpci690_halt(void)
	338	{
	339	while (1);
	340	/* NOTREACHED */
	341	}
	342
	343	static void
	344	cpci690_power_off(void)
	345	{
	346	cpci690_halt();
	347	/* NOTREACHED */
	348	}
	349
	350	static int
	351	cpci690_show_cpuinfo(struct seq_file *m)
	352	{
f54bef9e MG	353	char *s;
	354
	355	seq_printf(m, "cpu MHz\t\t: %d\n",
	356	(cpci690_get_cpu_freq() + 500000) / 1000000);
	357	seq_printf(m, "bus MHz\t\t: %d\n",
	358	(cpci690_get_bus_freq() + 500000) / 1000000);
1da177e4 LT	359	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
1da177e4 LT	360	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
f54bef9e MG	361	seq_printf(m, "FPGA Revision\t: %d\n",
	362	in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);
	363
	364	switch(bh.type) {
	365	case MV64x60_TYPE_GT64260A:
	366	s = "gt64260a";
	367	break;
	368	case MV64x60_TYPE_GT64260B:
	369	s = "gt64260b";
	370	break;
	371	case MV64x60_TYPE_MV64360:
	372	s = "mv64360";
	373	break;
	374	case MV64x60_TYPE_MV64460:
	375	s = "mv64460";
	376	break;
	377	default:
	378	s = "Unknown";
	379	}
	380	seq_printf(m, "bridge type\t: %s\n", s);
	381	seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
	382	#if defined(CONFIG_NOT_COHERENT_CACHE)
	383	seq_printf(m, "coherency\t: %s\n", "off");
	384	#else
	385	seq_printf(m, "coherency\t: %s\n", "on");
	386	#endif
1da177e4 LT	387
	388	return 0;
	389	}
	390
	391	static void __init
	392	cpci690_calibrate_decr(void)
	393	{
	394	ulong freq;
	395
f54bef9e	396	freq = cpci690_get_bus_freq() / 4;
1da177e4 LT	397
	398	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
	399	freq/1000000, freq%1000000);
	400
	401	tb_ticks_per_jiffy = freq / HZ;
	402	tb_to_us = mulhwu_scale_factor(freq, 1000000);
	403	}
	404
f54bef9e	405	#if defined(CONFIG_SERIAL_TEXT_DEBUG) \|\| defined(CONFIG_KGDB_MPSC)
1da177e4 LT	406	static void __init
	407	cpci690_map_io(void)
	408	{
	409	io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
f54bef9e	410	128 * 1024, _PAGE_IO);
1da177e4 LT	411	}
	412	#endif
	413
	414	void __init
	415	platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
	416	unsigned long r6, unsigned long r7)
	417	{
1da177e4 LT	418	parse_bootinfo(find_bootinfo());
1da177e4 LT	419
f54bef9e MG	420	#ifdef CONFIG_BLK_DEV_INITRD
	421	/* take care of initrd if we have one */
	422	if (r4) {
	423	initrd_start = r4 + KERNELBASE;
	424	initrd_end = r5 + KERNELBASE;
	425	}
	426	#endif /* CONFIG_BLK_DEV_INITRD */
1da177e4 LT	427
	428	isa_mem_base = 0;
	429
	430	ppc_md.setup_arch = cpci690_setup_arch;
	431	ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
	432	ppc_md.init_IRQ = gt64260_init_irq;
	433	ppc_md.get_irq = gt64260_get_irq;
	434	ppc_md.restart = cpci690_restart;
	435	ppc_md.power_off = cpci690_power_off;
	436	ppc_md.halt = cpci690_halt;
1da177e4 LT	437	ppc_md.time_init = todc_time_init;
	438	ppc_md.set_rtc_time = todc_set_rtc_time;
	439	ppc_md.get_rtc_time = todc_get_rtc_time;
	440	ppc_md.nvram_read_val = todc_direct_read_val;
	441	ppc_md.nvram_write_val = todc_direct_write_val;
	442	ppc_md.calibrate_decr = cpci690_calibrate_decr;
	443
f54bef9e	444	#if defined(CONFIG_SERIAL_TEXT_DEBUG) \|\| defined(CONFIG_KGDB_MPSC)
1da177e4	445	ppc_md.setup_io_mappings = cpci690_map_io;
f54bef9e	446	#ifdef CONFIG_SERIAL_TEXT_DEBUG
1da177e4 LT	447	ppc_md.progress = mv64x60_mpsc_progress;
	448	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
	449	#endif /* CONFIG_SERIAL_TEXT_DEBUG */
f54bef9e	450	#endif /* defined(CONFIG_SERIAL_TEXT_DEBUG) \|\| defined(CONFIG_KGDB_MPSC) */
1da177e4 LT	451
	452	#if defined(CONFIG_SERIAL_MPSC)
	453	platform_notify = cpci690_platform_notify;
	454	#endif
	455	}