]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/ppc/platforms/ev64260.c | |
3 | * | |
4 | * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board. | |
5 | * | |
6 | * Author: Mark A. Greer <mgreer@mvista.com> | |
7 | * | |
8 | * 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under | |
9 | * the terms of the GNU General Public License version 2. This program | |
10 | * is licensed "as is" without any warranty of any kind, whether express | |
11 | * or implied. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * The EV-64260-BP port is the result of hard work from many people from | |
16 | * many companies. In particular, employees of Marvell/Galileo, Mission | |
17 | * Critical Linux, Xyterra, and MontaVista Software were heavily involved. | |
18 | * | |
19 | * Note: I have not been able to get *all* PCI slots to work reliably | |
20 | * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2 | |
21 | * so that 33 MHz is used. --MAG | |
22 | * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK. | |
23 | * At 100MHz, they are solid. | |
24 | */ | |
25 | #include <linux/config.h> | |
26 | ||
27 | #include <linux/delay.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/ide.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/fs.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/console.h> | |
34 | #include <linux/initrd.h> | |
35 | #include <linux/root_dev.h> | |
d052d1be | 36 | #include <linux/platform_device.h> |
1da177e4 LT |
37 | #if !defined(CONFIG_SERIAL_MPSC_CONSOLE) |
38 | #include <linux/serial.h> | |
39 | #include <linux/tty.h> | |
40 | #include <linux/serial_core.h> | |
41 | #else | |
42 | #include <linux/mv643xx.h> | |
43 | #endif | |
44 | #include <asm/bootinfo.h> | |
45 | #include <asm/machdep.h> | |
46 | #include <asm/mv64x60.h> | |
47 | #include <asm/todc.h> | |
48 | #include <asm/time.h> | |
49 | ||
50 | #include <platforms/ev64260.h> | |
51 | ||
52 | #define BOARD_VENDOR "Marvell/Galileo" | |
53 | #define BOARD_MACHINE "EV-64260-BP" | |
54 | ||
55 | static struct mv64x60_handle bh; | |
56 | ||
57 | #if !defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
58 | extern void gen550_progress(char *, unsigned short); | |
59 | extern void gen550_init(int, struct uart_port *); | |
60 | #endif | |
61 | ||
62 | static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */ | |
63 | 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 | |
64 | }; | |
65 | static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */ | |
66 | { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 }, | |
67 | { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 } | |
68 | }; | |
69 | ||
70 | ||
71 | TODC_ALLOC(); | |
72 | ||
73 | static int | |
74 | ev64260_get_bus_speed(void) | |
75 | { | |
76 | return 100000000; | |
77 | } | |
78 | ||
79 | static int | |
80 | ev64260_get_cpu_speed(void) | |
81 | { | |
82 | unsigned long pvr, hid1, pll_ext; | |
83 | ||
84 | pvr = PVR_VER(mfspr(SPRN_PVR)); | |
85 | ||
86 | if (pvr != PVR_VER(PVR_7450)) { | |
87 | hid1 = mfspr(SPRN_HID1) >> 28; | |
88 | return ev64260_get_bus_speed() * cpu_7xx[hid1]/2; | |
89 | } | |
90 | else { | |
91 | hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13; | |
92 | pll_ext = 0; /* No way to read; must get from schematic */ | |
93 | return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2; | |
94 | } | |
95 | } | |
96 | ||
97 | unsigned long __init | |
98 | ev64260_find_end_of_memory(void) | |
99 | { | |
100 | return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, | |
101 | MV64x60_TYPE_GT64260A); | |
102 | } | |
103 | ||
104 | /* | |
105 | * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing. | |
106 | * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first | |
107 | * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ). | |
108 | * This is the most IRQs you can get from one bus with this board, though. | |
109 | */ | |
110 | static int __init | |
111 | ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
112 | { | |
113 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | |
114 | ||
115 | if (hose->index == 0) { | |
116 | static char pci_irq_table[][4] = | |
117 | /* | |
118 | * PCI IDSEL/INTPIN->INTLINE | |
119 | * A B C D | |
120 | */ | |
121 | { | |
122 | {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */ | |
123 | {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */ | |
124 | }; | |
125 | ||
126 | const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4; | |
127 | return PCI_IRQ_TABLE_LOOKUP; | |
128 | } | |
129 | else { | |
130 | static char pci_irq_table[][4] = | |
131 | /* | |
132 | * PCI IDSEL/INTPIN->INTLINE | |
133 | * A B C D | |
134 | */ | |
135 | { | |
136 | { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */ | |
137 | { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */ | |
138 | }; | |
139 | ||
140 | const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4; | |
141 | return PCI_IRQ_TABLE_LOOKUP; | |
142 | } | |
143 | } | |
144 | ||
145 | static void __init | |
146 | ev64260_setup_peripherals(void) | |
147 | { | |
148 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, | |
149 | EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0); | |
150 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); | |
151 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, | |
152 | EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0); | |
153 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); | |
154 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, | |
155 | EV64260_TODC_BASE, EV64260_TODC_SIZE, 0); | |
156 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); | |
157 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, | |
158 | EV64260_UART_BASE, EV64260_UART_SIZE, 0); | |
159 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); | |
160 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, | |
161 | EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0); | |
162 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); | |
163 | ||
164 | TODC_INIT(TODC_TYPE_DS1501, 0, 0, | |
165 | ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8); | |
166 | ||
167 | mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29))); | |
168 | mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27)); | |
169 | ||
170 | if (ev64260_get_bus_speed() > 100000000) | |
171 | mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23)); | |
172 | ||
173 | mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); | |
174 | mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); | |
175 | ||
176 | /* | |
177 | * Enabling of PCI internal-vs-external arbitration | |
178 | * is a platform- and errata-dependent decision. | |
179 | */ | |
180 | if (bh.type == MV64x60_TYPE_GT64260A ) { | |
181 | mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31)); | |
182 | mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31)); | |
183 | } | |
184 | ||
185 | mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */ | |
186 | ||
187 | /* | |
188 | * Turn off timer/counters. Not turning off watchdog timer because | |
189 | * can't read its reg on the 64260A so don't know if we'll be enabling | |
190 | * or disabling. | |
191 | */ | |
192 | mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, | |
193 | ((1<<0) | (1<<8) | (1<<16) | (1<<24))); | |
194 | mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL, | |
195 | ((1<<0) | (1<<8) | (1<<16) | (1<<24))); | |
196 | ||
197 | /* | |
198 | * Set MPSC Multiplex RMII | |
199 | * NOTE: ethernet driver modifies bit 0 and 1 | |
200 | */ | |
201 | mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102); | |
202 | ||
203 | /* | |
204 | * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260 | |
205 | * bridge as interrupt inputs (via the General Purpose Ports (GPP) | |
206 | * register). Need to route the MPP inputs to the GPP and set the | |
207 | * polarity correctly. | |
208 | * | |
209 | * In MPP Control 2 Register | |
210 | * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0 | |
211 | * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0 | |
212 | */ | |
213 | mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) ); | |
214 | ||
215 | /* | |
216 | * In MPP Control 3 Register | |
217 | * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0 | |
218 | * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0 | |
219 | * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0 | |
220 | */ | |
221 | mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20)); | |
222 | ||
223 | #define GPP_EXTERNAL_INTERRUPTS \ | |
224 | ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29)) | |
225 | /* DUART & PCI interrupts are inputs */ | |
226 | mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS); | |
227 | /* DUART & PCI interrupts are active low */ | |
228 | mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS); | |
229 | ||
230 | /* Clear any pending interrupts for these inputs and enable them. */ | |
231 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS); | |
232 | mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS); | |
233 | ||
234 | return; | |
235 | } | |
236 | ||
237 | static void __init | |
238 | ev64260_setup_bridge(void) | |
239 | { | |
240 | struct mv64x60_setup_info si; | |
241 | int i; | |
242 | ||
243 | memset(&si, 0, sizeof(si)); | |
244 | ||
245 | si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; | |
246 | ||
247 | si.pci_0.enable_bus = 1; | |
248 | si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE; | |
249 | si.pci_0.pci_io.pci_base_hi = 0; | |
250 | si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE; | |
251 | si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE; | |
252 | si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; | |
253 | si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE; | |
254 | si.pci_0.pci_mem[0].pci_base_hi = 0; | |
255 | si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE; | |
256 | si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE; | |
257 | si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
258 | si.pci_0.pci_cmd_bits = 0; | |
259 | si.pci_0.latency_timer = 0x8; | |
260 | ||
261 | si.pci_1.enable_bus = 1; | |
262 | si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE; | |
263 | si.pci_1.pci_io.pci_base_hi = 0; | |
264 | si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE; | |
265 | si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE; | |
266 | si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; | |
267 | si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE; | |
268 | si.pci_1.pci_mem[0].pci_base_hi = 0; | |
269 | si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE; | |
270 | si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE; | |
271 | si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
272 | si.pci_1.pci_cmd_bits = 0; | |
273 | si.pci_1.latency_timer = 0x8; | |
274 | ||
275 | for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) { | |
276 | si.cpu_prot_options[i] = 0; | |
277 | si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB; | |
278 | si.pci_0.acc_cntl_options[i] = | |
279 | GT64260_PCI_ACC_CNTL_DREADEN | | |
280 | GT64260_PCI_ACC_CNTL_RDPREFETCH | | |
281 | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH | | |
282 | GT64260_PCI_ACC_CNTL_RDMULPREFETCH | | |
283 | GT64260_PCI_ACC_CNTL_SWAP_NONE | | |
284 | GT64260_PCI_ACC_CNTL_MBURST_32_BTYES; | |
285 | si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB; | |
286 | si.pci_1.acc_cntl_options[i] = | |
287 | GT64260_PCI_ACC_CNTL_DREADEN | | |
288 | GT64260_PCI_ACC_CNTL_RDPREFETCH | | |
289 | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH | | |
290 | GT64260_PCI_ACC_CNTL_RDMULPREFETCH | | |
291 | GT64260_PCI_ACC_CNTL_SWAP_NONE | | |
292 | GT64260_PCI_ACC_CNTL_MBURST_32_BTYES; | |
293 | si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB; | |
294 | } | |
295 | ||
296 | /* Lookup PCI host bridges */ | |
297 | if (mv64x60_init(&bh, &si)) | |
298 | printk(KERN_ERR "Bridge initialization failed.\n"); | |
299 | ||
300 | pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */ | |
301 | ppc_md.pci_swizzle = common_swizzle; | |
302 | ppc_md.pci_map_irq = ev64260_map_irq; | |
303 | ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; | |
304 | ||
305 | mv64x60_set_bus(&bh, 0, 0); | |
306 | bh.hose_a->first_busno = 0; | |
307 | bh.hose_a->last_busno = 0xff; | |
308 | bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); | |
309 | ||
310 | bh.hose_b->first_busno = bh.hose_a->last_busno + 1; | |
311 | mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); | |
312 | bh.hose_b->last_busno = 0xff; | |
313 | bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, | |
314 | bh.hose_b->first_busno); | |
315 | ||
316 | return; | |
317 | } | |
318 | ||
319 | #if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
320 | static void __init | |
321 | ev64260_early_serial_map(void) | |
322 | { | |
323 | struct uart_port port; | |
324 | static char first_time = 1; | |
325 | ||
326 | if (first_time) { | |
327 | memset(&port, 0, sizeof(port)); | |
328 | ||
329 | port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE); | |
330 | port.irq = EV64260_UART_0_IRQ; | |
331 | port.uartclk = BASE_BAUD * 16; | |
332 | port.regshift = 2; | |
333 | port.iotype = SERIAL_IO_MEM; | |
334 | port.flags = STD_COM_FLAGS; | |
335 | ||
336 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | |
337 | gen550_init(0, &port); | |
338 | #endif | |
339 | ||
340 | if (early_serial_setup(&port) != 0) | |
341 | printk(KERN_WARNING "Early serial init of port 0" | |
342 | "failed\n"); | |
343 | ||
344 | first_time = 0; | |
345 | } | |
346 | ||
347 | return; | |
348 | } | |
349 | #elif defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
350 | static void __init | |
351 | ev64260_early_serial_map(void) | |
352 | { | |
353 | } | |
354 | #endif | |
355 | ||
356 | static void __init | |
357 | ev64260_setup_arch(void) | |
358 | { | |
359 | if (ppc_md.progress) | |
360 | ppc_md.progress("ev64260_setup_arch: enter", 0); | |
361 | ||
362 | #ifdef CONFIG_BLK_DEV_INITRD | |
363 | if (initrd_start) | |
364 | ROOT_DEV = Root_RAM0; | |
365 | else | |
366 | #endif | |
367 | #ifdef CONFIG_ROOT_NFS | |
368 | ROOT_DEV = Root_NFS; | |
369 | #else | |
370 | ROOT_DEV = Root_SDA2; | |
371 | #endif | |
372 | ||
373 | if (ppc_md.progress) | |
374 | ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0); | |
375 | ||
376 | /* Enable L2 and L3 caches (if 745x) */ | |
377 | _set_L2CR(_get_L2CR() | L2CR_L2E); | |
378 | _set_L3CR(_get_L3CR() | L3CR_L3E); | |
379 | ||
380 | if (ppc_md.progress) | |
381 | ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0); | |
382 | ||
383 | ev64260_setup_bridge(); /* set up PCI bridge(s) */ | |
384 | ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */ | |
385 | ||
386 | if (ppc_md.progress) | |
387 | ppc_md.progress("ev64260_setup_arch: bridge init complete", 0); | |
388 | ||
389 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
390 | ev64260_early_serial_map(); | |
391 | #endif | |
392 | ||
393 | printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc." | |
394 | "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE); | |
395 | ||
396 | if (ppc_md.progress) | |
397 | ppc_md.progress("ev64260_setup_arch: exit", 0); | |
398 | ||
399 | return; | |
400 | } | |
401 | ||
402 | /* Platform device data fixup routines. */ | |
403 | #if defined(CONFIG_SERIAL_MPSC) | |
404 | static void __init | |
405 | ev64260_fixup_mpsc_pdata(struct platform_device *pdev) | |
406 | { | |
407 | struct mpsc_pdata *pdata; | |
408 | ||
409 | pdata = (struct mpsc_pdata *)pdev->dev.platform_data; | |
410 | ||
411 | pdata->max_idle = 40; | |
412 | pdata->default_baud = EV64260_DEFAULT_BAUD; | |
413 | pdata->brg_clk_src = EV64260_MPSC_CLK_SRC; | |
414 | pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ; | |
415 | ||
416 | return; | |
417 | } | |
418 | ||
419 | static int __init | |
420 | ev64260_platform_notify(struct device *dev) | |
421 | { | |
422 | static struct { | |
423 | char *bus_id; | |
424 | void ((*rtn)(struct platform_device *pdev)); | |
425 | } dev_map[] = { | |
426 | { MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata }, | |
427 | { MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata }, | |
428 | }; | |
429 | struct platform_device *pdev; | |
430 | int i; | |
431 | ||
432 | if (dev && dev->bus_id) | |
433 | for (i=0; i<ARRAY_SIZE(dev_map); i++) | |
434 | if (!strncmp(dev->bus_id, dev_map[i].bus_id, | |
435 | BUS_ID_SIZE)) { | |
436 | ||
437 | pdev = container_of(dev, | |
438 | struct platform_device, dev); | |
439 | dev_map[i].rtn(pdev); | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | #endif | |
445 | ||
446 | static void | |
447 | ev64260_reset_board(void *addr) | |
448 | { | |
449 | local_irq_disable(); | |
450 | ||
451 | /* disable and invalidate the L2 cache */ | |
452 | _set_L2CR(0); | |
453 | _set_L2CR(0x200000); | |
454 | ||
455 | /* flush and disable L1 I/D cache */ | |
456 | __asm__ __volatile__ | |
457 | ("mfspr 3,1008\n\t" | |
458 | "ori 5,5,0xcc00\n\t" | |
459 | "ori 4,3,0xc00\n\t" | |
460 | "andc 5,3,5\n\t" | |
461 | "sync\n\t" | |
462 | "mtspr 1008,4\n\t" | |
463 | "isync\n\t" | |
464 | "sync\n\t" | |
465 | "mtspr 1008,5\n\t" | |
466 | "isync\n\t" | |
467 | "sync\n\t"); | |
468 | ||
469 | /* unmap any other random cs's that might overlap with bootcs */ | |
470 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0); | |
471 | bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); | |
472 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0); | |
473 | bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); | |
474 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0); | |
475 | bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); | |
476 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0); | |
477 | bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); | |
478 | ||
479 | /* map bootrom back in to gt @ reset defaults */ | |
480 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, | |
481 | 0xff800000, 8*1024*1024, 0); | |
482 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); | |
483 | ||
484 | /* move reg base back to default, setup default pci0 */ | |
485 | mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE, | |
486 | (1<<24) | CONFIG_MV64X60_BASE >> 20); | |
487 | ||
488 | /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped | |
489 | * via BAT or MMU, and MSR IR/DR is ON */ | |
490 | /* SRR0 has system reset vector, SRR1 has default MSR value */ | |
491 | /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ | |
492 | /* NOTE: assumes reset vector is at 0xfff00100 */ | |
493 | __asm__ __volatile__ | |
494 | ("mtspr 26, %0\n\t" | |
495 | "li 4,(1<<6)\n\t" | |
496 | "mtspr 27,4\n\t" | |
497 | "rfi\n\t" | |
498 | :: "r" (addr):"r4"); | |
499 | ||
500 | return; | |
501 | } | |
502 | ||
503 | static void | |
504 | ev64260_restart(char *cmd) | |
505 | { | |
506 | volatile ulong i = 10000000; | |
507 | ||
508 | ev64260_reset_board((void *)0xfff00100); | |
509 | ||
510 | while (i-- > 0); | |
511 | panic("restart failed\n"); | |
512 | } | |
513 | ||
514 | static void | |
515 | ev64260_halt(void) | |
516 | { | |
517 | local_irq_disable(); | |
518 | while (1); | |
519 | /* NOTREACHED */ | |
520 | } | |
521 | ||
522 | static void | |
523 | ev64260_power_off(void) | |
524 | { | |
525 | ev64260_halt(); | |
526 | /* NOTREACHED */ | |
527 | } | |
528 | ||
529 | static int | |
530 | ev64260_show_cpuinfo(struct seq_file *m) | |
531 | { | |
532 | uint pvid; | |
533 | ||
534 | pvid = mfspr(SPRN_PVR); | |
535 | seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); | |
536 | seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); | |
537 | seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000); | |
538 | seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | /* DS1501 RTC has too much variation to use RTC for calibration */ | |
544 | static void __init | |
545 | ev64260_calibrate_decr(void) | |
546 | { | |
547 | ulong freq; | |
548 | ||
549 | freq = ev64260_get_bus_speed()/4; | |
550 | ||
551 | printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", | |
552 | freq/1000000, freq%1000000); | |
553 | ||
554 | tb_ticks_per_jiffy = freq / HZ; | |
555 | tb_to_us = mulhwu_scale_factor(freq, 1000000); | |
556 | ||
557 | return; | |
558 | } | |
559 | ||
560 | /* | |
561 | * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space. | |
562 | */ | |
563 | static __inline__ void | |
564 | ev64260_set_bat(void) | |
565 | { | |
566 | mb(); | |
567 | mtspr(SPRN_DBAT1U, 0xfb0001fe); | |
568 | mtspr(SPRN_DBAT1L, 0xfb00002a); | |
569 | mb(); | |
570 | ||
571 | return; | |
572 | } | |
573 | ||
574 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | |
575 | static void __init | |
576 | ev64260_map_io(void) | |
577 | { | |
578 | io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO); | |
579 | } | |
580 | #endif | |
581 | ||
582 | void __init | |
583 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
584 | unsigned long r6, unsigned long r7) | |
585 | { | |
586 | #ifdef CONFIG_BLK_DEV_INITRD | |
587 | extern int initrd_below_start_ok; | |
588 | ||
589 | initrd_start=initrd_end=0; | |
590 | initrd_below_start_ok=0; | |
591 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
592 | ||
593 | parse_bootinfo(find_bootinfo()); | |
594 | ||
595 | isa_mem_base = 0; | |
596 | isa_io_base = EV64260_PCI0_IO_CPU_BASE; | |
597 | pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE; | |
598 | ||
599 | loops_per_jiffy = ev64260_get_cpu_speed() / HZ; | |
600 | ||
601 | ppc_md.setup_arch = ev64260_setup_arch; | |
602 | ppc_md.show_cpuinfo = ev64260_show_cpuinfo; | |
603 | ppc_md.init_IRQ = gt64260_init_irq; | |
604 | ppc_md.get_irq = gt64260_get_irq; | |
605 | ||
606 | ppc_md.restart = ev64260_restart; | |
607 | ppc_md.power_off = ev64260_power_off; | |
608 | ppc_md.halt = ev64260_halt; | |
609 | ||
610 | ppc_md.find_end_of_memory = ev64260_find_end_of_memory; | |
611 | ||
612 | ppc_md.init = NULL; | |
613 | ||
614 | ppc_md.time_init = todc_time_init; | |
615 | ppc_md.set_rtc_time = todc_set_rtc_time; | |
616 | ppc_md.get_rtc_time = todc_get_rtc_time; | |
617 | ppc_md.nvram_read_val = todc_direct_read_val; | |
618 | ppc_md.nvram_write_val = todc_direct_write_val; | |
619 | ppc_md.calibrate_decr = ev64260_calibrate_decr; | |
620 | ||
621 | bh.p_base = CONFIG_MV64X60_NEW_BASE; | |
622 | ||
623 | ev64260_set_bat(); | |
624 | ||
625 | #ifdef CONFIG_SERIAL_8250 | |
626 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) | |
627 | ppc_md.setup_io_mappings = ev64260_map_io; | |
628 | ppc_md.progress = gen550_progress; | |
629 | #endif | |
630 | #if defined(CONFIG_KGDB) | |
631 | ppc_md.setup_io_mappings = ev64260_map_io; | |
632 | ppc_md.early_serial_map = ev64260_early_serial_map; | |
633 | #endif | |
634 | #elif defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
635 | #ifdef CONFIG_SERIAL_TEXT_DEBUG | |
636 | ppc_md.setup_io_mappings = ev64260_map_io; | |
637 | ppc_md.progress = mv64x60_mpsc_progress; | |
638 | mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); | |
639 | #endif /* CONFIG_SERIAL_TEXT_DEBUG */ | |
640 | #ifdef CONFIG_KGDB | |
641 | ppc_md.setup_io_mappings = ev64260_map_io; | |
642 | ppc_md.early_serial_map = ev64260_early_serial_map; | |
643 | #endif /* CONFIG_KGDB */ | |
644 | ||
645 | #endif | |
646 | ||
647 | #if defined(CONFIG_SERIAL_MPSC) | |
648 | platform_notify = ev64260_platform_notify; | |
649 | #endif | |
650 | ||
651 | return; | |
652 | } |