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1da177e4 1/*
1da177e4
LT		 2 * Board setup routines for the Artesyn Katana cPCI boards.
3 *
4 * Author: Tim Montgomery <timm@artesyncp.com>
5 * Maintained by: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
8 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15/*
16 * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical
17 * to the 750i except that it has an mv64460 bridge.
18 */
19#include <linux/config.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/console.h>
24#include <linux/initrd.h>
25#include <linux/root_dev.h>
26#include <linux/delay.h>
27#include <linux/seq_file.h>
1da177e4
LT		 28#include <linux/mtd/physmap.h>
29#include <linux/mv643xx.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4
LT		 31#ifdef CONFIG_BOOTIMG
32#include <linux/bootimg.h>
33#endif
2ec19faf 34#include <asm/io.h>
f4c6cc8d 35#include <asm/unistd.h>
1da177e4
LT		 36#include <asm/page.h>
37#include <asm/time.h>
38#include <asm/smp.h>
39#include <asm/todc.h>
40#include <asm/bootinfo.h>
41#include <asm/ppcboot.h>
42#include <asm/mv64x60.h>
43#include <platforms/katana.h>
fd582ec8 44#include <asm/machdep.h>
1da177e4 45
f4c6cc8d
MG		 46static struct mv64x60_handle bh;
47static katana_id_t katana_id;
48static void __iomem *cpld_base;
49static void __iomem *sram_base;
50static u32 katana_flash_size_0;
51static u32 katana_flash_size_1;
52static u32 katana_bus_frequency;
53static struct pci_controller katana_hose_a;
1da177e4
LT		 54
55unsigned char __res[sizeof(bd_t)];
56
57/* PCI Interrupt routing */
58static int __init
59katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
60{
61 static char pci_irq_table[][4] = {
62 /*
63 * PCI IDSEL/INTPIN->INTLINE
64 * A B C D
65 */
66 /* IDSEL 4 (PMC 1) */
67 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
68 KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
69 /* IDSEL 5 (PMC 2) */
70 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
71 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
72 /* IDSEL 6 (T8110) */
73 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
f4c6cc8d
MG		 74 /* IDSEL 7 (unused) */
75 {0, 0, 0, 0 },
76 /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
77 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
1da177e4 78 };
f4c6cc8d 79 const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
1da177e4
LT		 80
81 return PCI_IRQ_TABLE_LOOKUP;
82}
83
84static int __init
85katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
86{
87 static char pci_irq_table[][4] = {
88 /*
89 * PCI IDSEL/INTPIN->INTLINE
90 * A B C D
91 */
92 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
93 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
94 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
95 };
96 const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
97
98 return PCI_IRQ_TABLE_LOOKUP;
99}
100
101static int __init
102katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
103{
104 switch (katana_id) {
105 case KATANA_ID_750I:
106 case KATANA_ID_752I:
107 return katana_irq_lookup_750i(idsel, pin);
108
109 case KATANA_ID_3750:
110 return katana_irq_lookup_3750(idsel, pin);
111
112 default:
113 printk(KERN_ERR "Bogus board ID\n");
114 return 0;
115 }
116}
117
118/* Board info retrieval routines */
119void __init
120katana_get_board_id(void)
121{
122 switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
123 case KATANA_PRODUCT_ID_3750:
124 katana_id = KATANA_ID_3750;
125 break;
126
127 case KATANA_PRODUCT_ID_750i:
128 katana_id = KATANA_ID_750I;
129 break;
130
131 case KATANA_PRODUCT_ID_752i:
132 katana_id = KATANA_ID_752I;
133 break;
134
135 default:
136 printk(KERN_ERR "Unsupported board\n");
137 }
138}
139
140int __init
141katana_get_proc_num(void)
142{
143 u16 val;
144 u8 save_exclude;
145 static int proc = -1;
146 static u8 first_time = 1;
147
148 if (first_time) {
149 if (katana_id != KATANA_ID_3750)
150 proc = 0;
151 else {
152 save_exclude = mv64x60_pci_exclude_bridge;
153 mv64x60_pci_exclude_bridge = 0;
154
f4c6cc8d 155 early_read_config_word(bh.hose_b, 0,
1da177e4
LT		 156 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
157
158 mv64x60_pci_exclude_bridge = save_exclude;
159
160 switch(val) {
161 case PCI_DEVICE_ID_KATANA_3750_PROC0:
162 proc = 0;
163 break;
164
165 case PCI_DEVICE_ID_KATANA_3750_PROC1:
166 proc = 1;
167 break;
168
169 case PCI_DEVICE_ID_KATANA_3750_PROC2:
170 proc = 2;
171 break;
172
173 default:
174 printk(KERN_ERR "Bogus Device ID\n");
175 }
176 }
177
178 first_time = 0;
179 }
180
181 return proc;
182}
183
184static inline int
185katana_is_monarch(void)
186{
187 return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
188 KATANA_CPLD_BD_CFG_3_MONARCH;
189}
190
191static void __init
192katana_setup_bridge(void)
193{
194 struct pci_controller hose;
195 struct mv64x60_setup_info si;
196 void __iomem *vaddr;
197 int i;
f4c6cc8d
MG		 198 u32 v;
199 u16 val, type;
1da177e4
LT		 200 u8 save_exclude;
201
202 /*
203 * Some versions of the Katana firmware mistakenly change the vendor
204 * & device id fields in the bridge's pci device (visible via pci
205 * config accesses). This breaks mv64x60_init() because those values
206 * are used to identify the type of bridge that's there. Artesyn
207 * claims that the subsystem vendor/device id's will have the correct
208 * Marvell values so this code puts back the correct values from there.
209 */
210 memset(&hose, 0, sizeof(hose));
211 vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
212 setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
213 vaddr + MV64x60_PCI0_CONFIG_DATA);
214 save_exclude = mv64x60_pci_exclude_bridge;
215 mv64x60_pci_exclude_bridge = 0;
216
217 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
218
219 if (val != PCI_VENDOR_ID_MARVELL) {
220 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
221 PCI_SUBSYSTEM_VENDOR_ID, &val);
222 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
223 PCI_VENDOR_ID, val);
224 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
225 PCI_SUBSYSTEM_ID, &val);
226 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
227 PCI_DEVICE_ID, val);
228 }
229
f4c6cc8d
MG		 230 /*
231 * While we're in here, set the hotswap register correctly.
232 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
233 */
234 early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
235 MV64360_PCICFG_CPCI_HOTSWAP, &v);
236 v &= ~(1<<19);
237 v |= ((1<<17) | (1<<22) | (1<<23));
238 early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
239 MV64360_PCICFG_CPCI_HOTSWAP, v);
240
241 /* While we're at it, grab the bridge type for later */
242 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
243
1da177e4
LT		 244 mv64x60_pci_exclude_bridge = save_exclude;
245 iounmap(vaddr);
246
247 memset(&si, 0, sizeof(si));
248
249 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
250
251 si.pci_1.enable_bus = 1;
252 si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
253 si.pci_1.pci_io.pci_base_hi = 0;
254 si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
255 si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
256 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
257 si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
258 si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
259 si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
260 si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
261 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
262 si.pci_1.pci_cmd_bits = 0;
263 si.pci_1.latency_timer = 0x80;
264
265 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
266#if defined(CONFIG_NOT_COHERENT_CACHE)
267 si.cpu_prot_options[i] = 0;
268 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
269 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
270 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
271
272 si.pci_1.acc_cntl_options[i] =
f4c6cc8d
MG		 273 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
274 MV64360_PCI_ACC_CNTL_SWAP_NONE |
275 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
276 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1da177e4
LT		 277#else
278 si.cpu_prot_options[i] = 0;
f4c6cc8d
MG		 279 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
280 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
281 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
1da177e4
LT		 282
283 si.pci_1.acc_cntl_options[i] =
f4c6cc8d
MG		 284 MV64360_PCI_ACC_CNTL_SNOOP_WB |
285 MV64360_PCI_ACC_CNTL_SWAP_NONE |
286 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
287 ((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
288 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
289 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
1da177e4
LT		 290#endif
291 }
292
293 /* Lookup PCI host bridges */
294 if (mv64x60_init(&bh, &si))
295 printk(KERN_WARNING "Bridge initialization failed.\n");
296
297 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
298 ppc_md.pci_swizzle = common_swizzle;
299 ppc_md.pci_map_irq = katana_map_irq;
300 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
301
302 mv64x60_set_bus(&bh, 1, 0);
303 bh.hose_b->first_busno = 0;
304 bh.hose_b->last_busno = 0xff;
f4c6cc8d
MG		 305
306 /*
307 * Need to access hotswap reg which is in the pci config area of the
308 * bridge's hose 0. Note that pcibios_alloc_controller() can't be used
309 * to alloc hose_a b/c that would make hose 0 known to the generic
310 * pci code which we don't want.
311 */
312 bh.hose_a = &katana_hose_a;
313 setup_indirect_pci_nomap(bh.hose_a,
314 bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
315 bh.v_base + MV64x60_PCI0_CONFIG_DATA);
1da177e4
LT		 316}
317
318/* Bridge & platform setup routines */
319void __init
320katana_intr_setup(void)
321{
f4c6cc8d
MG		 322 if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
323 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
324
1da177e4
LT		 325 /* MPP 8, 9, and 10 */
326 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
327
328 /* MPP 14 */
329 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
330 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
331
332 /*
333 * Define GPP 8,9,and 10 interrupt polarity as active low
334 * input signal and level triggered
335 */
336 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
337 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
338
339 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
340 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
341 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
342 }
343
344 /* Config GPP intr ctlr to respond to level trigger */
345 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
346
f4c6cc8d
MG		 347 if (bh.type == MV64x60_TYPE_MV64360) {
348 /* Erratum FEr PCI-#9 */
349 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
350 (1<<4) | (1<<5) | (1<<6) | (1<<7));
351 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
352 } else {
353 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
354 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
355 (1<<4) | (1<<5) | (1<<8) | (1<<9));
356 }
1da177e4
LT		 357
358 /*
359 * Dismiss and then enable interrupt on GPP interrupt cause
360 * for CPU #0
361 */
362 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
363 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
364
365 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
366 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
367 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
368 }
369
370 /*
371 * Dismiss and then enable interrupt on CPU #0 high cause reg
372 * BIT25 summarizes GPP interrupts 8-15
373 */
374 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
375}
376
377void __init
378katana_setup_peripherals(void)
379{
380 u32 base;
381
382 /* Set up windows for boot CS, soldered & socketed flash, and CPLD */
383 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
384 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
385 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
386
387 /* Assume firmware set up window sizes correctly for dev 0 & 1 */
388 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
389 &katana_flash_size_0);
390
391 if (katana_flash_size_0 > 0) {
392 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
393 KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
394 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
395 }
396
397 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
398 &katana_flash_size_1);
399
400 if (katana_flash_size_1 > 0) {
401 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
402 (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
403 katana_flash_size_1, 0);
404 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
405 }
406
407 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
408 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
409 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
410
411 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
412 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
413 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
414 cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
415
416 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
417 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
418 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
419 sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
420
421 /* Set up Enet->SRAM window */
422 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
423 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
424 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
425
426 /* Give enet r/w access to memory region */
427 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
428 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
429 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
430
431 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
432 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
433 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
434
435 /* Must wait until window set up before retrieving board id */
436 katana_get_board_id();
437
438 /* Enumerate pci bus (must know board id before getting proc number) */
439 if (katana_get_proc_num() == 0)
440 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
441
442#if defined(CONFIG_NOT_COHERENT_CACHE)
443 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
444#else
445 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
446#endif
447
448 /*
449 * Setting the SRAM to 0. Note that this generates parity errors on
450 * internal data path in SRAM since it's first time accessing it
451 * while after reset it's not configured.
452 */
453 memset(sram_base, 0, MV64360_SRAM_SIZE);
454
455 /* Only processor zero [on 3750] is an PCI interrupt controller */
456 if (katana_get_proc_num() == 0)
457 katana_intr_setup();
458}
459
460static void __init
461katana_enable_ipmi(void)
462{
463 u8 reset_out;
464
465 /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
466 reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
467 reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
468 out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
469}
470
471static void __init
472katana_setup_arch(void)
473{
474 if (ppc_md.progress)
475 ppc_md.progress("katana_setup_arch: enter", 0);
476
477 set_tb(0, 0);
478
479#ifdef CONFIG_BLK_DEV_INITRD
480 if (initrd_start)
481 ROOT_DEV = Root_RAM0;
482 else
483#endif
484#ifdef CONFIG_ROOT_NFS
485 ROOT_DEV = Root_NFS;
486#else
487 ROOT_DEV = Root_SDA2;
488#endif
489
490 /*
491 * Set up the L2CR register.
492 *
493 * 750FX has only L2E, L2PE (bits 2-8 are reserved)
494 * DD2.0 has bug that requires the L2 to be in WRT mode
495 * avoid dirty data in cache
496 */
497 if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
498 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
499 "to Writethrough mode\n");
500 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
501 } else
502 _set_L2CR(L2CR_L2E | L2CR_L2PE);
503
504 if (ppc_md.progress)
505 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
506
507 katana_setup_bridge();
508 katana_setup_peripherals();
509 katana_enable_ipmi();
510
511 katana_bus_frequency = katana_bus_freq(cpld_base);
512
513 printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
514 if (ppc_md.progress)
515 ppc_md.progress("katana_setup_arch: exit", 0);
516}
517
f4c6cc8d
MG		 518void
519katana_fixup_resources(struct pci_dev *dev)
520{
521 u16 v16;
522
7dffb720 523 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2);
f4c6cc8d
MG		 524
525 pci_read_config_word(dev, PCI_COMMAND, &v16);
526 v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
527 pci_write_config_word(dev, PCI_COMMAND, v16);
528}
529
530static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
531 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
532 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
533};
534
535static int
536katana_get_cpu_freq(void)
537{
538 unsigned long pll_cfg;
539
540 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
541 return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
542}
543
1da177e4
LT		 544/* Platform device data fixup routines. */
545#if defined(CONFIG_SERIAL_MPSC)
546static void __init
547katana_fixup_mpsc_pdata(struct platform_device *pdev)
548{
f4c6cc8d
MG		 549 struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
550 bd_t *bdp = (bd_t *)__res;
1da177e4 551
f4c6cc8d
MG		 552 if (bdp->bi_baudrate)
553 pdata->default_baud = bdp->bi_baudrate;
554 else
555 pdata->default_baud = KATANA_DEFAULT_BAUD;
1da177e4
LT		 556
557 pdata->max_idle = 40;
1da177e4
LT		 558 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
559 /*
560 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
561 * TCLK == SysCLK but on 64460, they are separate pins.
562 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
563 */
564 pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
565}
566#endif
567
568#if defined(CONFIG_MV643XX_ETH)
569static void __init
570katana_fixup_eth_pdata(struct platform_device *pdev)
571{
572 struct mv643xx_eth_platform_data *eth_pd;
573 static u16 phy_addr[] = {
574 KATANA_ETH0_PHY_ADDR,
575 KATANA_ETH1_PHY_ADDR,
576 KATANA_ETH2_PHY_ADDR,
577 };
578
579 eth_pd = pdev->dev.platform_data;
580 eth_pd->force_phy_addr = 1;
581 eth_pd->phy_addr = phy_addr[pdev->id];
582 eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
583 eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
584}
585#endif
586
f4c6cc8d
MG		 587#if defined(CONFIG_SYSFS)
588static void __init
589katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
590{
591 struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
592 pdev->dev.platform_data;
593
594 /* Katana supports the mv64xxx hotswap register */
595 pdata->hs_reg_valid = 1;
596}
597#endif
598
bbbe1212 599static int
1da177e4
LT		 600katana_platform_notify(struct device *dev)
601{
602 static struct {
603 char *bus_id;
604 void ((*rtn)(struct platform_device *pdev));
605 } dev_map[] = {
606#if defined(CONFIG_SERIAL_MPSC)
607 { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
608 { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
609#endif
610#if defined(CONFIG_MV643XX_ETH)
611 { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
612 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
613 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
f4c6cc8d
MG		 614#endif
615#if defined(CONFIG_SYSFS)
616 { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
1da177e4
LT		 617#endif
618 };
619 struct platform_device *pdev;
620 int i;
621
622 if (dev && dev->bus_id)
623 for (i=0; i<ARRAY_SIZE(dev_map); i++)
624 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
f4c6cc8d 625 BUS_ID_SIZE)) {
1da177e4
LT		 626 pdev = container_of(dev,
627 struct platform_device, dev);
628 dev_map[i].rtn(pdev);
629 }
630
631 return 0;
632}
633
634#ifdef CONFIG_MTD_PHYSMAP
635
636#ifndef MB
637#define MB (1 << 20)
638#endif
639
640/*
641 * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
642 *
643 * FLASH Amount: 128 64 32 16
644 * ------------- --- -- -- --
645 * Monitor: 1 1 1 1
646 * Primary Kernel: 1.5 1.5 1.5 1.5
647 * Primary fs: 30 30 <end> <end>
648 * Secondary Kernel: 1.5 1.5 N/A N/A
649 * Secondary fs: <end> <end> N/A N/A
650 * User: <overlays entire FLASH except for "Monitor" section>
651 */
652static int __init
653katana_setup_mtd(void)
654{
655 u32 size;
656 int ptbl_entries;
657 static struct mtd_partition *ptbl;
658
659 size = katana_flash_size_0 + katana_flash_size_1;
660 if (!size)
661 return -ENOMEM;
662
663 ptbl_entries = (size >= (64*MB)) ? 6 : 4;
664
d116fe5a 665 if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition),
f4c6cc8d 666 GFP_KERNEL)) == NULL) {
1da177e4
LT		 667 printk(KERN_WARNING "Can't alloc MTD partition table\n");
668 return -ENOMEM;
669 }
1da177e4
LT		 670
671 ptbl[0].name = "Monitor";
672 ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
673 ptbl[1].name = "Primary Kernel";
674 ptbl[1].offset = MTDPART_OFS_NXTBLK;
675 ptbl[1].size = 0x00180000; /* 1.5 MB */
676 ptbl[2].name = "Primary Filesystem";
677 ptbl[2].offset = MTDPART_OFS_APPEND;
678 ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
679 ptbl[ptbl_entries-1].name = "User FLASH";
680 ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
681 ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
682
683 if (size >= (64*MB)) {
684 ptbl[2].size = 30*MB;
685 ptbl[3].name = "Secondary Kernel";
686 ptbl[3].offset = MTDPART_OFS_NXTBLK;
687 ptbl[3].size = 0x00180000; /* 1.5 MB */
688 ptbl[4].name = "Secondary Filesystem";
689 ptbl[4].offset = MTDPART_OFS_APPEND;
690 ptbl[4].size = MTDPART_SIZ_FULL;
691 }
692
693 physmap_map.size = size;
694 physmap_set_partitions(ptbl, ptbl_entries);
695 return 0;
696}
1da177e4
LT		 697arch_initcall(katana_setup_mtd);
698#endif
699
700static void
701katana_restart(char *cmd)
702{
703 ulong i = 10000000;
704
705 /* issue hard reset to the reset command register */
706 out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
707
708 while (i-- > 0) ;
709 panic("restart failed\n");
710}
711
712static void
713katana_halt(void)
714{
715 u8 v;
716
f4c6cc8d
MG		 717 /* Turn on blue LED to indicate its okay to remove */
718 if (katana_id == KATANA_ID_750I) {
719 u32 v;
720 u8 save_exclude;
721
722 /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
723 save_exclude = mv64x60_pci_exclude_bridge;
724 mv64x60_pci_exclude_bridge = 0;
725 early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
726 MV64360_PCICFG_CPCI_HOTSWAP, &v);
727 v &= 0xff;
728 v |= (1 << 19);
729 early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
730 MV64360_PCICFG_CPCI_HOTSWAP, v);
731 mv64x60_pci_exclude_bridge = save_exclude;
732 } else if (katana_id == KATANA_ID_752I) {
1da177e4
LT		 733 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
734 v |= HSL_PLD_HOT_SWAP_LED_BIT;
735 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
736 }
737
738 while (1) ;
739 /* NOTREACHED */
740}
741
742static void
743katana_power_off(void)
744{
745 katana_halt();
746 /* NOTREACHED */
747}
748
749static int
750katana_show_cpuinfo(struct seq_file *m)
751{
f4c6cc8d
MG		 752 char *s;
753
754 seq_printf(m, "cpu freq\t: %dMHz\n",
755 (katana_get_cpu_freq() + 500000) / 1000000);
756 seq_printf(m, "bus freq\t: %ldMHz\n",
757 ((long)katana_bus_frequency + 500000) / 1000000);
1da177e4
LT		 758 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
759
760 seq_printf(m, "board\t\t: ");
1da177e4
LT		 761 switch (katana_id) {
762 case KATANA_ID_3750:
f4c6cc8d 763 seq_printf(m, "Katana 3750");
1da177e4
LT		 764 break;
765
766 case KATANA_ID_750I:
f4c6cc8d 767 seq_printf(m, "Katana 750i");
1da177e4
LT		 768 break;
769
770 case KATANA_ID_752I:
f4c6cc8d 771 seq_printf(m, "Katana 752i");
1da177e4
LT		 772 break;
773
774 default:
f4c6cc8d 775 seq_printf(m, "Unknown");
1da177e4
LT		 776 break;
777 }
f4c6cc8d 778 seq_printf(m, " (product id: 0x%x)\n",
1da177e4 779 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
f4c6cc8d
MG		 780
781 seq_printf(m, "pci mode\t: %sMonarch\n",
782 katana_is_monarch()? "" : "Non-");
1da177e4
LT		 783 seq_printf(m, "hardware rev\t: 0x%x\n",
784 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
f4c6cc8d 785 seq_printf(m, "pld rev\t\t: 0x%x\n",
1da177e4 786 in_8(cpld_base + KATANA_CPLD_PLD_VER));
f4c6cc8d
MG		 787
788 switch(bh.type) {
789 case MV64x60_TYPE_GT64260A:
790 s = "gt64260a";
791 break;
792 case MV64x60_TYPE_GT64260B:
793 s = "gt64260b";
794 break;
795 case MV64x60_TYPE_MV64360:
796 s = "mv64360";
797 break;
798 case MV64x60_TYPE_MV64460:
799 s = "mv64460";
800 break;
801 default:
802 s = "Unknown";
803 }
804 seq_printf(m, "bridge type\t: %s\n", s);
805 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
806#if defined(CONFIG_NOT_COHERENT_CACHE)
807 seq_printf(m, "coherency\t: %s\n", "off");
808#else
809 seq_printf(m, "coherency\t: %s\n", "on");
810#endif
1da177e4
LT		 811
812 return 0;
813}
814
815static void __init
816katana_calibrate_decr(void)
817{
818 u32 freq;
819
820 freq = katana_bus_frequency / 4;
821
822 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
823 (long)freq / 1000000, (long)freq % 1000000);
824
825 tb_ticks_per_jiffy = freq / HZ;
826 tb_to_us = mulhwu_scale_factor(freq, 1000000);
827}
828
f4c6cc8d
MG		 829/*
830 * The katana supports both uImage and zImage. If uImage, get the mem size
831 * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in
832 * the bi_rec data which is sucked out and put into boot_mem_size by
833 * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem
834 * size and not call this routine. The only way this will fail is when a uImage
835 * is used but the fw doesn't pass in a valid bi_memsize. This should never
836 * happen, though.
837 */
1da177e4
LT		 838unsigned long __init
839katana_find_end_of_memory(void)
840{
f4c6cc8d
MG		 841 bd_t *bdp = (bd_t *)__res;
842 return bdp->bi_memsize;
1da177e4
LT		 843}
844
845#if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
846extern ulong m41t00_get_rtc_time(void);
847extern int m41t00_set_rtc_time(ulong);
848
849static int __init
850katana_rtc_hookup(void)
851{
852 struct timespec tv;
853
854 ppc_md.get_rtc_time = m41t00_get_rtc_time;
855 ppc_md.set_rtc_time = m41t00_set_rtc_time;
856
857 tv.tv_nsec = 0;
858 tv.tv_sec = (ppc_md.get_rtc_time)();
859 do_settimeofday(&tv);
860
861 return 0;
862}
863late_initcall(katana_rtc_hookup);
864#endif
865
1da177e4
LT		 866#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
867static void __init
868katana_map_io(void)
869{
870 io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
871}
872#endif
873
874void __init
875platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
876 unsigned long r6, unsigned long r7)
877{
878 parse_bootinfo(find_bootinfo());
879
880 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
881 * are non-zero, then we should use the board info from the bd_t
882 * structure and the cmdline pointed to by r6 instead of the
883 * information from birecs, if any. Otherwise, use the information
884 * from birecs as discovered by the preceeding call to
885 * parse_bootinfo(). This rule should work with both PPCBoot, which
886 * uses a bd_t board info structure, and the kernel boot wrapper,
887 * which uses birecs.
888 */
889 if (r3 && r6) {
890 /* copy board info structure */
f4c6cc8d 891 memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
1da177e4
LT		 892 /* copy command line */
893 *(char *)(r7+KERNELBASE) = 0;
894 strcpy(cmd_line, (char *)(r6+KERNELBASE));
895 }
896
f4c6cc8d
MG		 897#ifdef CONFIG_BLK_DEV_INITRD
898 /* take care of initrd if we have one */
899 if (r4) {
900 initrd_start = r4 + KERNELBASE;
901 initrd_end = r5 + KERNELBASE;
902 }
903#endif /* CONFIG_BLK_DEV_INITRD */
904
1da177e4
LT		 905 isa_mem_base = 0;
906
907 ppc_md.setup_arch = katana_setup_arch;
f4c6cc8d 908 ppc_md.pcibios_fixup_resources = katana_fixup_resources;
1da177e4
LT		 909 ppc_md.show_cpuinfo = katana_show_cpuinfo;
910 ppc_md.init_IRQ = mv64360_init_irq;
911 ppc_md.get_irq = mv64360_get_irq;
912 ppc_md.restart = katana_restart;
913 ppc_md.power_off = katana_power_off;
914 ppc_md.halt = katana_halt;
915 ppc_md.find_end_of_memory = katana_find_end_of_memory;
916 ppc_md.calibrate_decr = katana_calibrate_decr;
917
918#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
919 ppc_md.setup_io_mappings = katana_map_io;
920 ppc_md.progress = mv64x60_mpsc_progress;
921 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
922#endif
923
924#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
925 platform_notify = katana_platform_notify;
926#endif
1da177e4 927}
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