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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/ppc/platforms/mcpn765.c | |
3 | * | |
4 | * Board setup routines for the Motorola MCG MCPN765 cPCI Board. | |
5 | * | |
6 | * Author: Mark A. Greer | |
7 | * mgreer@mvista.com | |
8 | * | |
9 | * Modified by Randy Vinson (rvinson@mvista.com) | |
10 | * | |
11 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | |
12 | * the terms of the GNU General Public License version 2. This program | |
13 | * is licensed "as is" without any warranty of any kind, whether express | |
14 | * or implied. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * This file adds support for the Motorola MCG MCPN765. | |
19 | */ | |
20 | #include <linux/config.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/reboot.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/kdev_t.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/initrd.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/root_dev.h> | |
35 | #include <linux/serial.h> | |
36 | #include <linux/tty.h> /* for linux/serial_core.h */ | |
37 | #include <linux/serial_core.h> | |
38 | #include <linux/slab.h> | |
39 | ||
40 | #include <asm/system.h> | |
41 | #include <asm/pgtable.h> | |
42 | #include <asm/page.h> | |
43 | #include <asm/time.h> | |
44 | #include <asm/dma.h> | |
45 | #include <asm/byteorder.h> | |
46 | #include <asm/io.h> | |
47 | #include <asm/machdep.h> | |
48 | #include <asm/prom.h> | |
49 | #include <asm/smp.h> | |
50 | #include <asm/open_pic.h> | |
51 | #include <asm/i8259.h> | |
52 | #include <asm/todc.h> | |
53 | #include <asm/pci-bridge.h> | |
54 | #include <asm/irq.h> | |
55 | #include <asm/uaccess.h> | |
56 | #include <asm/bootinfo.h> | |
57 | #include <asm/hawk.h> | |
58 | #include <asm/kgdb.h> | |
59 | ||
60 | #include "mcpn765.h" | |
61 | ||
62 | static u_char mcpn765_openpic_initsenses[] __initdata = { | |
63 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE),/* 16: i8259 cascade */ | |
64 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 17: COM1,2,3,4 */ | |
65 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 18: Enet 1 (front) */ | |
66 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 19: HAWK WDT XXXX */ | |
67 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 20: 21554 bridge */ | |
68 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 21: cPCI INTA# */ | |
69 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 22: cPCI INTB# */ | |
70 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 23: cPCI INTC# */ | |
71 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 24: cPCI INTD# */ | |
72 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 25: PMC1 INTA#,PMC2 INTB#*/ | |
73 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 26: PMC1 INTB#,PMC2 INTC#*/ | |
74 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 27: PMC1 INTC#,PMC2 INTD#*/ | |
75 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 28: PMC1 INTD#,PMC2 INTA#*/ | |
76 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 29: Enet 2 (J3) */ | |
77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 30: Abort Switch */ | |
78 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 31: RTC Alarm */ | |
79 | }; | |
80 | ||
81 | extern void mcpn765_set_VIA_IDE_native(void); | |
82 | ||
83 | extern u_int openpic_irq(void); | |
84 | extern char cmd_line[]; | |
85 | ||
86 | extern void gen550_progress(char *, unsigned short); | |
87 | extern void gen550_init(int, struct uart_port *); | |
88 | ||
89 | int use_of_interrupt_tree = 0; | |
90 | ||
91 | static void mcpn765_halt(void); | |
92 | ||
93 | TODC_ALLOC(); | |
94 | ||
95 | /* | |
96 | * Motorola MCG MCPN765 interrupt routing. | |
97 | */ | |
98 | static inline int | |
99 | mcpn765_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
100 | { | |
101 | static char pci_irq_table[][4] = | |
102 | /* | |
103 | * PCI IDSEL/INTPIN->INTLINE | |
104 | * A B C D | |
105 | */ | |
106 | { | |
107 | { 14, 0, 0, 0 }, /* IDSEL 11 - have to manually set */ | |
108 | { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ | |
109 | { 0, 0, 0, 0 }, /* IDSEL 13 - unused */ | |
110 | { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */ | |
111 | { 0, 0, 0, 0 }, /* IDSEL 15 - unused */ | |
112 | { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */ | |
113 | { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */ | |
114 | { 0, 0, 0, 0 }, /* IDSEL 18 - PMC 2B Connector XXXX */ | |
115 | { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 1 */ | |
116 | { 20, 0, 0, 0 }, /* IDSEL 20 - 21554 cPCI bridge */ | |
117 | }; | |
118 | ||
119 | const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4; | |
120 | return PCI_IRQ_TABLE_LOOKUP; | |
121 | } | |
122 | ||
123 | void __init | |
124 | mcpn765_set_VIA_IDE_legacy(void) | |
125 | { | |
126 | unsigned short vend, dev; | |
127 | ||
128 | early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend); | |
129 | early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev); | |
130 | ||
131 | if ((vend == PCI_VENDOR_ID_VIA) && | |
132 | (dev == PCI_DEVICE_ID_VIA_82C586_1)) { | |
133 | ||
134 | unsigned char temp; | |
135 | ||
136 | /* put back original "standard" port base addresses */ | |
137 | early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), | |
138 | PCI_BASE_ADDRESS_0, 0x1f1); | |
139 | early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), | |
140 | PCI_BASE_ADDRESS_1, 0x3f5); | |
141 | early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), | |
142 | PCI_BASE_ADDRESS_2, 0x171); | |
143 | early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), | |
144 | PCI_BASE_ADDRESS_3, 0x375); | |
145 | early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), | |
146 | PCI_BASE_ADDRESS_4, 0xcc01); | |
147 | ||
148 | /* put into legacy mode */ | |
149 | early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, | |
150 | &temp); | |
151 | temp &= ~0x05; | |
152 | early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, | |
153 | temp); | |
154 | } | |
155 | } | |
156 | ||
157 | void | |
158 | mcpn765_set_VIA_IDE_native(void) | |
159 | { | |
160 | unsigned short vend, dev; | |
161 | ||
162 | early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend); | |
163 | early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev); | |
164 | ||
165 | if ((vend == PCI_VENDOR_ID_VIA) && | |
166 | (dev == PCI_DEVICE_ID_VIA_82C586_1)) { | |
167 | ||
168 | unsigned char temp; | |
169 | ||
170 | /* put into native mode */ | |
171 | early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, | |
172 | &temp); | |
173 | temp |= 0x05; | |
174 | early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, | |
175 | temp); | |
176 | } | |
177 | } | |
178 | ||
179 | /* | |
180 | * Initialize the VIA 82c586b. | |
181 | */ | |
182 | static void __init | |
183 | mcpn765_setup_via_82c586b(void) | |
184 | { | |
185 | struct pci_dev *dev; | |
186 | u_char c; | |
187 | ||
188 | if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, | |
189 | PCI_DEVICE_ID_VIA_82C586_0, | |
190 | NULL)) == NULL) { | |
191 | printk("No VIA ISA bridge found\n"); | |
192 | mcpn765_halt(); | |
193 | /* NOTREACHED */ | |
194 | } | |
195 | ||
196 | /* | |
197 | * If the firmware left the EISA 4d0/4d1 ports enabled, make sure | |
198 | * IRQ 14 is set for edge. | |
199 | */ | |
200 | pci_read_config_byte(dev, 0x47, &c); | |
201 | ||
202 | if (c & (1<<5)) { | |
203 | c = inb(0x4d1); | |
204 | c &= ~(1<<6); | |
205 | outb(c, 0x4d1); | |
206 | } | |
207 | ||
208 | /* Disable PNP IRQ routing since we use the Hawk's MPIC */ | |
209 | pci_write_config_dword(dev, 0x54, 0); | |
210 | pci_write_config_byte(dev, 0x58, 0); | |
211 | ||
212 | pci_dev_put(dev); | |
213 | if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, | |
214 | PCI_DEVICE_ID_VIA_82C586_1, | |
215 | NULL)) == NULL) { | |
216 | printk("No VIA ISA bridge found\n"); | |
217 | mcpn765_halt(); | |
218 | /* NOTREACHED */ | |
219 | } | |
220 | ||
221 | /* | |
222 | * PPCBug doesn't set the enable bits for the IDE device. | |
223 | * Turn them on now. | |
224 | */ | |
225 | pci_read_config_byte(dev, 0x40, &c); | |
226 | c |= 0x03; | |
227 | pci_write_config_byte(dev, 0x40, c); | |
228 | pci_dev_put(dev); | |
229 | ||
230 | return; | |
231 | } | |
232 | ||
233 | void __init | |
234 | mcpn765_pcibios_fixup(void) | |
235 | { | |
236 | /* Do MCPN765 board specific initialization. */ | |
237 | mcpn765_setup_via_82c586b(); | |
238 | } | |
239 | ||
240 | void __init | |
241 | mcpn765_find_bridges(void) | |
242 | { | |
243 | struct pci_controller *hose; | |
244 | ||
245 | hose = pcibios_alloc_controller(); | |
246 | ||
247 | if (!hose) | |
248 | return; | |
249 | ||
250 | hose->first_busno = 0; | |
251 | hose->last_busno = 0xff; | |
252 | hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET; | |
253 | ||
254 | pci_init_resource(&hose->io_resource, | |
255 | MCPN765_PCI_IO_START, | |
256 | MCPN765_PCI_IO_END, | |
257 | IORESOURCE_IO, | |
258 | "PCI host bridge"); | |
259 | ||
260 | pci_init_resource(&hose->mem_resources[0], | |
261 | MCPN765_PCI_MEM_START, | |
262 | MCPN765_PCI_MEM_END, | |
263 | IORESOURCE_MEM, | |
264 | "PCI host bridge"); | |
265 | ||
266 | hose->io_space.start = MCPN765_PCI_IO_START; | |
267 | hose->io_space.end = MCPN765_PCI_IO_END; | |
268 | hose->mem_space.start = MCPN765_PCI_MEM_START; | |
269 | hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE; | |
270 | ||
271 | if (hawk_init(hose, | |
272 | MCPN765_HAWK_PPC_REG_BASE, | |
273 | MCPN765_PROC_PCI_MEM_START, | |
274 | MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE, | |
275 | MCPN765_PROC_PCI_IO_START, | |
276 | MCPN765_PROC_PCI_IO_END, | |
277 | MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) { | |
278 | printk("Could not initialize HAWK bridge\n"); | |
279 | } | |
280 | ||
281 | /* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config | |
282 | * will reassign the bars outside of 16-bit I/O space, which will | |
283 | * "break" things. To prevent this, we'll set the IDE chip into | |
284 | * legacy mode and seed the bars with their legacy addresses (in 16-bit | |
285 | * I/O space). The Auto Config code will skip the IDE contoller in | |
286 | * legacy mode, so our bar values will stick. | |
287 | */ | |
288 | mcpn765_set_VIA_IDE_legacy(); | |
289 | ||
290 | hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); | |
291 | ||
292 | /* Now that we've got 16-bit addresses in the bars, we can switch the | |
293 | * IDE controller back into native mode so we can do "modern" resource | |
294 | * and interrupt management. | |
295 | */ | |
296 | mcpn765_set_VIA_IDE_native(); | |
297 | ||
298 | ppc_md.pcibios_fixup = mcpn765_pcibios_fixup; | |
299 | ppc_md.pcibios_fixup_bus = NULL; | |
300 | ppc_md.pci_swizzle = common_swizzle; | |
301 | ppc_md.pci_map_irq = mcpn765_map_irq; | |
302 | ||
303 | return; | |
304 | } | |
305 | static void __init | |
306 | mcpn765_setup_arch(void) | |
307 | { | |
308 | struct pci_controller *hose; | |
309 | ||
310 | if ( ppc_md.progress ) | |
311 | ppc_md.progress("mcpn765_setup_arch: enter", 0); | |
312 | ||
313 | loops_per_jiffy = 50000000 / HZ; | |
314 | ||
315 | #ifdef CONFIG_BLK_DEV_INITRD | |
316 | if (initrd_start) | |
317 | ROOT_DEV = Root_RAM0; | |
318 | else | |
319 | #endif | |
320 | #ifdef CONFIG_ROOT_NFS | |
321 | ROOT_DEV = Root_NFS; | |
322 | #else | |
323 | ROOT_DEV = Root_SDA2; | |
324 | #endif | |
325 | ||
326 | if ( ppc_md.progress ) | |
327 | ppc_md.progress("mcpn765_setup_arch: find_bridges", 0); | |
328 | ||
329 | /* Lookup PCI host bridges */ | |
330 | mcpn765_find_bridges(); | |
331 | ||
332 | hose = pci_bus_to_hose(0); | |
333 | isa_io_base = (ulong)hose->io_base_virt; | |
334 | ||
335 | TODC_INIT(TODC_TYPE_MK48T37, | |
336 | (MCPN765_PHYS_NVRAM_AS0 - isa_io_base), | |
337 | (MCPN765_PHYS_NVRAM_AS1 - isa_io_base), | |
338 | (MCPN765_PHYS_NVRAM_DATA - isa_io_base), | |
339 | 8); | |
340 | ||
341 | OpenPIC_InitSenses = mcpn765_openpic_initsenses; | |
342 | OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses); | |
343 | ||
344 | printk("Motorola MCG MCPN765 cPCI Non-System Board\n"); | |
345 | printk("MCPN765 port (MontaVista Software, Inc. (source@mvista.com))\n"); | |
346 | ||
347 | if ( ppc_md.progress ) | |
348 | ppc_md.progress("mcpn765_setup_arch: exit", 0); | |
349 | ||
350 | return; | |
351 | } | |
352 | ||
353 | static void __init | |
354 | mcpn765_init2(void) | |
355 | { | |
356 | ||
357 | request_region(0x00,0x20,"dma1"); | |
358 | request_region(0x20,0x20,"pic1"); | |
359 | request_region(0x40,0x20,"timer"); | |
360 | request_region(0x80,0x10,"dma page reg"); | |
361 | request_region(0xa0,0x20,"pic2"); | |
362 | request_region(0xc0,0x20,"dma2"); | |
363 | ||
364 | return; | |
365 | } | |
366 | ||
367 | /* | |
368 | * Interrupt setup and service. | |
369 | * Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC. | |
370 | */ | |
371 | static void __init | |
372 | mcpn765_init_IRQ(void) | |
373 | { | |
374 | int i; | |
375 | ||
376 | if ( ppc_md.progress ) | |
377 | ppc_md.progress("init_irq: enter", 0); | |
378 | ||
379 | openpic_init(NUM_8259_INTERRUPTS); | |
380 | openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", | |
381 | i8259_irq); | |
382 | ||
383 | for(i=0; i < NUM_8259_INTERRUPTS; i++) | |
384 | irq_desc[i].handler = &i8259_pic; | |
385 | ||
386 | i8259_init(0); | |
387 | ||
388 | if ( ppc_md.progress ) | |
389 | ppc_md.progress("init_irq: exit", 0); | |
390 | ||
391 | return; | |
392 | } | |
393 | ||
394 | static u32 | |
395 | mcpn765_irq_canonicalize(u32 irq) | |
396 | { | |
397 | if (irq == 2) | |
398 | return 9; | |
399 | else | |
400 | return irq; | |
401 | } | |
402 | ||
403 | static unsigned long __init | |
404 | mcpn765_find_end_of_memory(void) | |
405 | { | |
406 | return hawk_get_mem_size(MCPN765_HAWK_SMC_BASE); | |
407 | } | |
408 | ||
409 | static void __init | |
410 | mcpn765_map_io(void) | |
411 | { | |
412 | io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO); | |
413 | } | |
414 | ||
415 | static void | |
416 | mcpn765_reset_board(void) | |
417 | { | |
418 | local_irq_disable(); | |
419 | ||
420 | /* set VIA IDE controller into native mode */ | |
421 | mcpn765_set_VIA_IDE_native(); | |
422 | ||
423 | /* Set exception prefix high - to the firmware */ | |
424 | _nmask_and_or_msr(0, MSR_IP); | |
425 | ||
426 | out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01); | |
427 | ||
428 | return; | |
429 | } | |
430 | ||
431 | static void | |
432 | mcpn765_restart(char *cmd) | |
433 | { | |
434 | volatile ulong i = 10000000; | |
435 | ||
436 | mcpn765_reset_board(); | |
437 | ||
438 | while (i-- > 0); | |
439 | panic("restart failed\n"); | |
440 | } | |
441 | ||
442 | static void | |
443 | mcpn765_power_off(void) | |
444 | { | |
445 | mcpn765_halt(); | |
446 | /* NOTREACHED */ | |
447 | } | |
448 | ||
449 | static void | |
450 | mcpn765_halt(void) | |
451 | { | |
452 | local_irq_disable(); | |
453 | while (1); | |
454 | /* NOTREACHED */ | |
455 | } | |
456 | ||
457 | static int | |
458 | mcpn765_show_cpuinfo(struct seq_file *m) | |
459 | { | |
460 | seq_printf(m, "vendor\t\t: Motorola MCG\n"); | |
461 | seq_printf(m, "machine\t\t: MCPN765\n"); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | /* | |
467 | * Set BAT 3 to map 0xf0000000 to end of physical memory space. | |
468 | */ | |
469 | static __inline__ void | |
470 | mcpn765_set_bat(void) | |
471 | { | |
472 | mb(); | |
473 | mtspr(SPRN_DBAT1U, 0xfe8000fe); | |
474 | mtspr(SPRN_DBAT1L, 0xfe80002a); | |
475 | mb(); | |
476 | } | |
477 | ||
478 | void __init | |
479 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
480 | unsigned long r6, unsigned long r7) | |
481 | { | |
482 | parse_bootinfo(find_bootinfo()); | |
483 | ||
484 | /* Map in board regs, etc. */ | |
485 | mcpn765_set_bat(); | |
486 | ||
487 | isa_mem_base = MCPN765_ISA_MEM_BASE; | |
488 | pci_dram_offset = MCPN765_PCI_DRAM_OFFSET; | |
489 | ISA_DMA_THRESHOLD = 0x00ffffff; | |
490 | DMA_MODE_READ = 0x44; | |
491 | DMA_MODE_WRITE = 0x48; | |
492 | ||
493 | ppc_md.setup_arch = mcpn765_setup_arch; | |
494 | ppc_md.show_cpuinfo = mcpn765_show_cpuinfo; | |
495 | ppc_md.irq_canonicalize = mcpn765_irq_canonicalize; | |
496 | ppc_md.init_IRQ = mcpn765_init_IRQ; | |
497 | ppc_md.get_irq = openpic_get_irq; | |
498 | ppc_md.init = mcpn765_init2; | |
499 | ||
500 | ppc_md.restart = mcpn765_restart; | |
501 | ppc_md.power_off = mcpn765_power_off; | |
502 | ppc_md.halt = mcpn765_halt; | |
503 | ||
504 | ppc_md.find_end_of_memory = mcpn765_find_end_of_memory; | |
505 | ppc_md.setup_io_mappings = mcpn765_map_io; | |
506 | ||
507 | ppc_md.time_init = todc_time_init; | |
508 | ppc_md.set_rtc_time = todc_set_rtc_time; | |
509 | ppc_md.get_rtc_time = todc_get_rtc_time; | |
510 | ppc_md.calibrate_decr = todc_calibrate_decr; | |
511 | ||
512 | ppc_md.nvram_read_val = todc_m48txx_read_val; | |
513 | ppc_md.nvram_write_val = todc_m48txx_write_val; | |
514 | ||
515 | ppc_md.heartbeat = NULL; | |
516 | ppc_md.heartbeat_reset = 0; | |
517 | ppc_md.heartbeat_count = 0; | |
518 | ||
519 | #ifdef CONFIG_SERIAL_TEXT_DEBUG | |
520 | ppc_md.progress = gen550_progress; | |
521 | #endif | |
522 | #ifdef CONFIG_KGDB | |
523 | ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; | |
524 | #endif | |
525 | ||
526 | return; | |
527 | } |