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1da177e4 LT |
1 | /* |
2 | * Support for PCI bridges found on Power Macintoshes. | |
3 | * At present the "bandit" and "chaos" bridges are supported. | |
4 | * Fortunately you access configuration space in the same | |
5 | * way with either bridge. | |
6 | * | |
7 | * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
21 | ||
22 | #include <asm/sections.h> | |
23 | #include <asm/io.h> | |
24 | #include <asm/prom.h> | |
25 | #include <asm/pci-bridge.h> | |
26 | #include <asm/machdep.h> | |
27 | #include <asm/pmac_feature.h> | |
28 | ||
29 | #undef DEBUG | |
30 | ||
31 | #ifdef DEBUG | |
32 | #ifdef CONFIG_XMON | |
33 | extern void xmon_printf(const char *fmt, ...); | |
34 | #define DBG(x...) xmon_printf(x) | |
35 | #else | |
36 | #define DBG(x...) printk(x) | |
37 | #endif | |
38 | #else | |
39 | #define DBG(x...) | |
40 | #endif | |
41 | ||
42 | static int add_bridge(struct device_node *dev); | |
43 | extern void pmac_check_ht_link(void); | |
44 | ||
45 | /* XXX Could be per-controller, but I don't think we risk anything by | |
46 | * assuming we won't have both UniNorth and Bandit */ | |
47 | static int has_uninorth; | |
48 | #ifdef CONFIG_POWER4 | |
49 | static struct pci_controller *u3_agp; | |
50 | #endif /* CONFIG_POWER4 */ | |
51 | ||
52 | extern u8 pci_cache_line_size; | |
53 | extern int pcibios_assign_bus_offset; | |
54 | ||
55 | struct device_node *k2_skiplist[2]; | |
56 | ||
57 | /* | |
58 | * Magic constants for enabling cache coherency in the bandit/PSX bridge. | |
59 | */ | |
60 | #define BANDIT_DEVID_2 8 | |
61 | #define BANDIT_REVID 3 | |
62 | ||
63 | #define BANDIT_DEVNUM 11 | |
64 | #define BANDIT_MAGIC 0x50 | |
65 | #define BANDIT_COHERENT 0x40 | |
66 | ||
67 | static int __init | |
68 | fixup_one_level_bus_range(struct device_node *node, int higher) | |
69 | { | |
70 | for (; node != 0;node = node->sibling) { | |
71 | int * bus_range; | |
72 | unsigned int *class_code; | |
73 | int len; | |
74 | ||
75 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
76 | class_code = (unsigned int *) get_property(node, "class-code", NULL); | |
77 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && | |
78 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
79 | continue; | |
80 | bus_range = (int *) get_property(node, "bus-range", &len); | |
81 | if (bus_range != NULL && len > 2 * sizeof(int)) { | |
82 | if (bus_range[1] > higher) | |
83 | higher = bus_range[1]; | |
84 | } | |
85 | higher = fixup_one_level_bus_range(node->child, higher); | |
86 | } | |
87 | return higher; | |
88 | } | |
89 | ||
90 | /* This routine fixes the "bus-range" property of all bridges in the | |
91 | * system since they tend to have their "last" member wrong on macs | |
92 | * | |
93 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
94 | * are not Linux bus numbers. | |
95 | */ | |
96 | static void __init | |
97 | fixup_bus_range(struct device_node *bridge) | |
98 | { | |
99 | int * bus_range; | |
100 | int len; | |
101 | ||
102 | /* Lookup the "bus-range" property for the hose */ | |
103 | bus_range = (int *) get_property(bridge, "bus-range", &len); | |
104 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
105 | printk(KERN_WARNING "Can't get bus-range for %s\n", | |
106 | bridge->full_name); | |
107 | return; | |
108 | } | |
109 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); | |
110 | } | |
111 | ||
112 | /* | |
113 | * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. | |
114 | * | |
115 | * The "Bandit" version is present in all early PCI PowerMacs, | |
116 | * and up to the first ones using Grackle. Some machines may | |
117 | * have 2 bandit controllers (2 PCI busses). | |
118 | * | |
119 | * "Chaos" is used in some "Bandit"-type machines as a bridge | |
120 | * for the separate display bus. It is accessed the same | |
121 | * way as bandit, but cannot be probed for devices. It therefore | |
122 | * has its own config access functions. | |
123 | * | |
124 | * The "UniNorth" version is present in all Core99 machines | |
125 | * (iBook, G4, new IMacs, and all the recent Apple machines). | |
126 | * It contains 3 controllers in one ASIC. | |
127 | * | |
128 | * The U3 is the bridge used on G5 machines. It contains an | |
129 | * AGP bus which is dealt with the old UniNorth access routines | |
130 | * and a HyperTransport bus which uses its own set of access | |
131 | * functions. | |
132 | */ | |
133 | ||
134 | #define MACRISC_CFA0(devfn, off) \ | |
135 | ((1 << (unsigned long)PCI_SLOT(dev_fn)) \ | |
136 | | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \ | |
137 | | (((unsigned long)(off)) & 0xFCUL)) | |
138 | ||
139 | #define MACRISC_CFA1(bus, devfn, off) \ | |
140 | ((((unsigned long)(bus)) << 16) \ | |
141 | |(((unsigned long)(devfn)) << 8) \ | |
142 | |(((unsigned long)(off)) & 0xFCUL) \ | |
143 | |1UL) | |
144 | ||
145 | static void volatile __iomem * __pmac | |
146 | macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) | |
147 | { | |
148 | unsigned int caddr; | |
149 | ||
150 | if (bus == hose->first_busno) { | |
151 | if (dev_fn < (11 << 3)) | |
152 | return NULL; | |
153 | caddr = MACRISC_CFA0(dev_fn, offset); | |
154 | } else | |
155 | caddr = MACRISC_CFA1(bus, dev_fn, offset); | |
156 | ||
157 | /* Uninorth will return garbage if we don't read back the value ! */ | |
158 | do { | |
159 | out_le32(hose->cfg_addr, caddr); | |
160 | } while (in_le32(hose->cfg_addr) != caddr); | |
161 | ||
162 | offset &= has_uninorth ? 0x07 : 0x03; | |
163 | return hose->cfg_data + offset; | |
164 | } | |
165 | ||
166 | static int __pmac | |
167 | macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
168 | int len, u32 *val) | |
169 | { | |
170 | struct pci_controller *hose = bus->sysdata; | |
171 | void volatile __iomem *addr; | |
172 | ||
173 | addr = macrisc_cfg_access(hose, bus->number, devfn, offset); | |
174 | if (!addr) | |
175 | return PCIBIOS_DEVICE_NOT_FOUND; | |
176 | /* | |
177 | * Note: the caller has already checked that offset is | |
178 | * suitably aligned and that len is 1, 2 or 4. | |
179 | */ | |
180 | switch (len) { | |
181 | case 1: | |
182 | *val = in_8(addr); | |
183 | break; | |
184 | case 2: | |
185 | *val = in_le16(addr); | |
186 | break; | |
187 | default: | |
188 | *val = in_le32(addr); | |
189 | break; | |
190 | } | |
191 | return PCIBIOS_SUCCESSFUL; | |
192 | } | |
193 | ||
194 | static int __pmac | |
195 | macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
196 | int len, u32 val) | |
197 | { | |
198 | struct pci_controller *hose = bus->sysdata; | |
199 | void volatile __iomem *addr; | |
200 | ||
201 | addr = macrisc_cfg_access(hose, bus->number, devfn, offset); | |
202 | if (!addr) | |
203 | return PCIBIOS_DEVICE_NOT_FOUND; | |
204 | /* | |
205 | * Note: the caller has already checked that offset is | |
206 | * suitably aligned and that len is 1, 2 or 4. | |
207 | */ | |
208 | switch (len) { | |
209 | case 1: | |
210 | out_8(addr, val); | |
211 | (void) in_8(addr); | |
212 | break; | |
213 | case 2: | |
214 | out_le16(addr, val); | |
215 | (void) in_le16(addr); | |
216 | break; | |
217 | default: | |
218 | out_le32(addr, val); | |
219 | (void) in_le32(addr); | |
220 | break; | |
221 | } | |
222 | return PCIBIOS_SUCCESSFUL; | |
223 | } | |
224 | ||
225 | static struct pci_ops macrisc_pci_ops = | |
226 | { | |
227 | macrisc_read_config, | |
228 | macrisc_write_config | |
229 | }; | |
230 | ||
231 | /* | |
232 | * Verifiy that a specific (bus, dev_fn) exists on chaos | |
233 | */ | |
234 | static int __pmac | |
235 | chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) | |
236 | { | |
237 | struct device_node *np; | |
238 | u32 *vendor, *device; | |
239 | ||
240 | np = pci_busdev_to_OF_node(bus, devfn); | |
241 | if (np == NULL) | |
242 | return PCIBIOS_DEVICE_NOT_FOUND; | |
243 | ||
244 | vendor = (u32 *)get_property(np, "vendor-id", NULL); | |
245 | device = (u32 *)get_property(np, "device-id", NULL); | |
246 | if (vendor == NULL || device == NULL) | |
247 | return PCIBIOS_DEVICE_NOT_FOUND; | |
248 | ||
249 | if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) | |
250 | && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) | |
251 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
252 | ||
253 | return PCIBIOS_SUCCESSFUL; | |
254 | } | |
255 | ||
256 | static int __pmac | |
257 | chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
258 | int len, u32 *val) | |
259 | { | |
260 | int result = chaos_validate_dev(bus, devfn, offset); | |
261 | if (result == PCIBIOS_BAD_REGISTER_NUMBER) | |
262 | *val = ~0U; | |
263 | if (result != PCIBIOS_SUCCESSFUL) | |
264 | return result; | |
265 | return macrisc_read_config(bus, devfn, offset, len, val); | |
266 | } | |
267 | ||
268 | static int __pmac | |
269 | chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
270 | int len, u32 val) | |
271 | { | |
272 | int result = chaos_validate_dev(bus, devfn, offset); | |
273 | if (result != PCIBIOS_SUCCESSFUL) | |
274 | return result; | |
275 | return macrisc_write_config(bus, devfn, offset, len, val); | |
276 | } | |
277 | ||
278 | static struct pci_ops chaos_pci_ops = | |
279 | { | |
280 | chaos_read_config, | |
281 | chaos_write_config | |
282 | }; | |
283 | ||
284 | #ifdef CONFIG_POWER4 | |
285 | ||
286 | /* | |
287 | * These versions of U3 HyperTransport config space access ops do not | |
288 | * implement self-view of the HT host yet | |
289 | */ | |
290 | ||
291 | #define U3_HT_CFA0(devfn, off) \ | |
292 | ((((unsigned long)devfn) << 8) | offset) | |
293 | #define U3_HT_CFA1(bus, devfn, off) \ | |
294 | (U3_HT_CFA0(devfn, off) \ | |
295 | + (((unsigned long)bus) << 16) \ | |
296 | + 0x01000000UL) | |
297 | ||
298 | static void volatile __iomem * __pmac | |
299 | u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) | |
300 | { | |
301 | if (bus == hose->first_busno) { | |
302 | /* For now, we don't self probe U3 HT bridge */ | |
303 | if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 || | |
304 | PCI_SLOT(devfn) < 1) | |
305 | return 0; | |
306 | return hose->cfg_data + U3_HT_CFA0(devfn, offset); | |
307 | } else | |
308 | return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); | |
309 | } | |
310 | ||
311 | static int __pmac | |
312 | u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
313 | int len, u32 *val) | |
314 | { | |
315 | struct pci_controller *hose = bus->sysdata; | |
316 | void volatile __iomem *addr; | |
317 | int i; | |
318 | ||
319 | struct device_node *np = pci_busdev_to_OF_node(bus, devfn); | |
320 | if (np == NULL) | |
321 | return PCIBIOS_DEVICE_NOT_FOUND; | |
322 | ||
323 | /* | |
324 | * When a device in K2 is powered down, we die on config | |
325 | * cycle accesses. Fix that here. | |
326 | */ | |
327 | for (i=0; i<2; i++) | |
328 | if (k2_skiplist[i] == np) { | |
329 | switch (len) { | |
330 | case 1: | |
331 | *val = 0xff; break; | |
332 | case 2: | |
333 | *val = 0xffff; break; | |
334 | default: | |
335 | *val = 0xfffffffful; break; | |
336 | } | |
337 | return PCIBIOS_SUCCESSFUL; | |
338 | } | |
339 | ||
340 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); | |
341 | if (!addr) | |
342 | return PCIBIOS_DEVICE_NOT_FOUND; | |
343 | /* | |
344 | * Note: the caller has already checked that offset is | |
345 | * suitably aligned and that len is 1, 2 or 4. | |
346 | */ | |
347 | switch (len) { | |
348 | case 1: | |
349 | *val = in_8(addr); | |
350 | break; | |
351 | case 2: | |
352 | *val = in_le16(addr); | |
353 | break; | |
354 | default: | |
355 | *val = in_le32(addr); | |
356 | break; | |
357 | } | |
358 | return PCIBIOS_SUCCESSFUL; | |
359 | } | |
360 | ||
361 | static int __pmac | |
362 | u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
363 | int len, u32 val) | |
364 | { | |
365 | struct pci_controller *hose = bus->sysdata; | |
366 | void volatile __iomem *addr; | |
367 | int i; | |
368 | ||
369 | struct device_node *np = pci_busdev_to_OF_node(bus, devfn); | |
370 | if (np == NULL) | |
371 | return PCIBIOS_DEVICE_NOT_FOUND; | |
372 | /* | |
373 | * When a device in K2 is powered down, we die on config | |
374 | * cycle accesses. Fix that here. | |
375 | */ | |
376 | for (i=0; i<2; i++) | |
377 | if (k2_skiplist[i] == np) | |
378 | return PCIBIOS_SUCCESSFUL; | |
379 | ||
380 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); | |
381 | if (!addr) | |
382 | return PCIBIOS_DEVICE_NOT_FOUND; | |
383 | /* | |
384 | * Note: the caller has already checked that offset is | |
385 | * suitably aligned and that len is 1, 2 or 4. | |
386 | */ | |
387 | switch (len) { | |
388 | case 1: | |
389 | out_8(addr, val); | |
390 | (void) in_8(addr); | |
391 | break; | |
392 | case 2: | |
393 | out_le16(addr, val); | |
394 | (void) in_le16(addr); | |
395 | break; | |
396 | default: | |
397 | out_le32(addr, val); | |
398 | (void) in_le32(addr); | |
399 | break; | |
400 | } | |
401 | return PCIBIOS_SUCCESSFUL; | |
402 | } | |
403 | ||
404 | static struct pci_ops u3_ht_pci_ops = | |
405 | { | |
406 | u3_ht_read_config, | |
407 | u3_ht_write_config | |
408 | }; | |
409 | ||
410 | #endif /* CONFIG_POWER4 */ | |
411 | ||
412 | /* | |
413 | * For a bandit bridge, turn on cache coherency if necessary. | |
414 | * N.B. we could clean this up using the hose ops directly. | |
415 | */ | |
416 | static void __init | |
417 | init_bandit(struct pci_controller *bp) | |
418 | { | |
419 | unsigned int vendev, magic; | |
420 | int rev; | |
421 | ||
422 | /* read the word at offset 0 in config space for device 11 */ | |
423 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); | |
424 | udelay(2); | |
425 | vendev = in_le32(bp->cfg_data); | |
426 | if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + | |
427 | PCI_VENDOR_ID_APPLE) { | |
428 | /* read the revision id */ | |
429 | out_le32(bp->cfg_addr, | |
430 | (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); | |
431 | udelay(2); | |
432 | rev = in_8(bp->cfg_data); | |
433 | if (rev != BANDIT_REVID) | |
434 | printk(KERN_WARNING | |
435 | "Unknown revision %d for bandit\n", rev); | |
436 | } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { | |
437 | printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); | |
438 | return; | |
439 | } | |
440 | ||
441 | /* read the word at offset 0x50 */ | |
442 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); | |
443 | udelay(2); | |
444 | magic = in_le32(bp->cfg_data); | |
445 | if ((magic & BANDIT_COHERENT) != 0) | |
446 | return; | |
447 | magic |= BANDIT_COHERENT; | |
448 | udelay(2); | |
449 | out_le32(bp->cfg_data, magic); | |
450 | printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); | |
451 | } | |
452 | ||
453 | ||
454 | /* | |
455 | * Tweak the PCI-PCI bridge chip on the blue & white G3s. | |
456 | */ | |
457 | static void __init | |
458 | init_p2pbridge(void) | |
459 | { | |
460 | struct device_node *p2pbridge; | |
461 | struct pci_controller* hose; | |
462 | u8 bus, devfn; | |
463 | u16 val; | |
464 | ||
465 | /* XXX it would be better here to identify the specific | |
466 | PCI-PCI bridge chip we have. */ | |
467 | if ((p2pbridge = find_devices("pci-bridge")) == 0 | |
468 | || p2pbridge->parent == NULL | |
469 | || strcmp(p2pbridge->parent->name, "pci") != 0) | |
470 | return; | |
471 | if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { | |
472 | DBG("Can't find PCI infos for PCI<->PCI bridge\n"); | |
473 | return; | |
474 | } | |
475 | /* Warning: At this point, we have not yet renumbered all busses. | |
476 | * So we must use OF walking to find out hose | |
477 | */ | |
478 | hose = pci_find_hose_for_OF_device(p2pbridge); | |
479 | if (!hose) { | |
480 | DBG("Can't find hose for PCI<->PCI bridge\n"); | |
481 | return; | |
482 | } | |
483 | if (early_read_config_word(hose, bus, devfn, | |
484 | PCI_BRIDGE_CONTROL, &val) < 0) { | |
485 | printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n"); | |
486 | return; | |
487 | } | |
488 | val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; | |
489 | early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); | |
490 | } | |
491 | ||
492 | /* | |
493 | * Some Apple desktop machines have a NEC PD720100A USB2 controller | |
494 | * on the motherboard. Open Firmware, on these, will disable the | |
495 | * EHCI part of it so it behaves like a pair of OHCI's. This fixup | |
496 | * code re-enables it ;) | |
497 | */ | |
498 | static void __init | |
499 | fixup_nec_usb2(void) | |
500 | { | |
501 | struct device_node *nec; | |
502 | ||
503 | for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { | |
504 | struct pci_controller *hose; | |
505 | u32 data, *prop; | |
506 | u8 bus, devfn; | |
507 | ||
508 | prop = (u32 *)get_property(nec, "vendor-id", NULL); | |
509 | if (prop == NULL) | |
510 | continue; | |
511 | if (0x1033 != *prop) | |
512 | continue; | |
513 | prop = (u32 *)get_property(nec, "device-id", NULL); | |
514 | if (prop == NULL) | |
515 | continue; | |
516 | if (0x0035 != *prop) | |
517 | continue; | |
518 | prop = (u32 *)get_property(nec, "reg", NULL); | |
519 | if (prop == NULL) | |
520 | continue; | |
521 | devfn = (prop[0] >> 8) & 0xff; | |
522 | bus = (prop[0] >> 16) & 0xff; | |
523 | if (PCI_FUNC(devfn) != 0) | |
524 | continue; | |
525 | hose = pci_find_hose_for_OF_device(nec); | |
526 | if (!hose) | |
527 | continue; | |
528 | early_read_config_dword(hose, bus, devfn, 0xe4, &data); | |
529 | if (data & 1UL) { | |
530 | printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n"); | |
531 | data &= ~1UL; | |
532 | early_write_config_dword(hose, bus, devfn, 0xe4, data); | |
533 | early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE, | |
534 | nec->intrs[0].line); | |
535 | } | |
536 | } | |
537 | } | |
538 | ||
539 | void __init | |
540 | pmac_find_bridges(void) | |
541 | { | |
542 | struct device_node *np, *root; | |
543 | struct device_node *ht = NULL; | |
544 | ||
545 | root = of_find_node_by_path("/"); | |
546 | if (root == NULL) { | |
547 | printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n"); | |
548 | return; | |
549 | } | |
550 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { | |
551 | if (np->name == NULL) | |
552 | continue; | |
553 | if (strcmp(np->name, "bandit") == 0 | |
554 | || strcmp(np->name, "chaos") == 0 | |
555 | || strcmp(np->name, "pci") == 0) { | |
556 | if (add_bridge(np) == 0) | |
557 | of_node_get(np); | |
558 | } | |
559 | if (strcmp(np->name, "ht") == 0) { | |
560 | of_node_get(np); | |
561 | ht = np; | |
562 | } | |
563 | } | |
564 | of_node_put(root); | |
565 | ||
566 | /* Probe HT last as it relies on the agp resources to be already | |
567 | * setup | |
568 | */ | |
569 | if (ht && add_bridge(ht) != 0) | |
570 | of_node_put(ht); | |
571 | ||
572 | init_p2pbridge(); | |
573 | fixup_nec_usb2(); | |
574 | ||
575 | /* We are still having some issues with the Xserve G4, enabling | |
576 | * some offset between bus number and domains for now when we | |
577 | * assign all busses should help for now | |
578 | */ | |
579 | if (pci_assign_all_busses) | |
580 | pcibios_assign_bus_offset = 0x10; | |
581 | ||
582 | #ifdef CONFIG_POWER4 | |
583 | /* There is something wrong with DMA on U3/HT. I haven't figured out | |
584 | * the details yet, but if I set the cache line size to 128 bytes like | |
585 | * it should, I'm getting memory corruption caused by devices like | |
586 | * sungem (even without the MWI bit set, but maybe sungem doesn't | |
587 | * care). Right now, it appears that setting up a 64 bytes line size | |
588 | * works properly, 64 bytes beeing the max transfer size of HT, I | |
589 | * suppose this is related the way HT/PCI are hooked together. I still | |
590 | * need to dive into more specs though to be really sure of what's | |
591 | * going on. --BenH. | |
592 | * | |
593 | * Ok, apparently, it's just that HT can't do more than 64 bytes | |
594 | * transactions. MWI seem to be meaningless there as well, it may | |
595 | * be worth nop'ing out pci_set_mwi too though I haven't done that | |
596 | * yet. | |
597 | * | |
598 | * Note that it's a bit different for whatever is in the AGP slot. | |
599 | * For now, I don't care, but this can become a real issue, we | |
600 | * should probably hook pci_set_mwi anyway to make sure it sets | |
601 | * the real cache line size in there. | |
602 | */ | |
603 | if (machine_is_compatible("MacRISC4")) | |
604 | pci_cache_line_size = 16; /* 64 bytes */ | |
605 | ||
606 | pmac_check_ht_link(); | |
607 | #endif /* CONFIG_POWER4 */ | |
608 | } | |
609 | ||
610 | #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \ | |
611 | | (((o) & ~3) << 24)) | |
612 | ||
613 | #define GRACKLE_PICR1_STG 0x00000040 | |
614 | #define GRACKLE_PICR1_LOOPSNOOP 0x00000010 | |
615 | ||
616 | /* N.B. this is called before bridges is initialized, so we can't | |
617 | use grackle_pcibios_{read,write}_config_dword. */ | |
618 | static inline void grackle_set_stg(struct pci_controller* bp, int enable) | |
619 | { | |
620 | unsigned int val; | |
621 | ||
622 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); | |
623 | val = in_le32(bp->cfg_data); | |
624 | val = enable? (val | GRACKLE_PICR1_STG) : | |
625 | (val & ~GRACKLE_PICR1_STG); | |
626 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); | |
627 | out_le32(bp->cfg_data, val); | |
628 | (void)in_le32(bp->cfg_data); | |
629 | } | |
630 | ||
631 | static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) | |
632 | { | |
633 | unsigned int val; | |
634 | ||
635 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); | |
636 | val = in_le32(bp->cfg_data); | |
637 | val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) : | |
638 | (val & ~GRACKLE_PICR1_LOOPSNOOP); | |
639 | out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); | |
640 | out_le32(bp->cfg_data, val); | |
641 | (void)in_le32(bp->cfg_data); | |
642 | } | |
643 | ||
644 | static int __init | |
645 | setup_uninorth(struct pci_controller* hose, struct reg_property* addr) | |
646 | { | |
647 | pci_assign_all_busses = 1; | |
648 | has_uninorth = 1; | |
649 | hose->ops = ¯isc_pci_ops; | |
650 | hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); | |
651 | hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); | |
652 | /* We "know" that the bridge at f2000000 has the PCI slots. */ | |
653 | return addr->address == 0xf2000000; | |
654 | } | |
655 | ||
656 | static void __init | |
657 | setup_bandit(struct pci_controller* hose, struct reg_property* addr) | |
658 | { | |
659 | hose->ops = ¯isc_pci_ops; | |
660 | hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); | |
661 | hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); | |
662 | init_bandit(hose); | |
663 | } | |
664 | ||
665 | static void __init | |
666 | setup_chaos(struct pci_controller* hose, struct reg_property* addr) | |
667 | { | |
668 | /* assume a `chaos' bridge */ | |
669 | hose->ops = &chaos_pci_ops; | |
670 | hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); | |
671 | hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); | |
672 | } | |
673 | ||
674 | #ifdef CONFIG_POWER4 | |
675 | ||
676 | static void __init | |
677 | setup_u3_agp(struct pci_controller* hose, struct reg_property* addr) | |
678 | { | |
679 | /* On G5, we move AGP up to high bus number so we don't need | |
680 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
681 | * on AGP, we'll have to move pci_assign_all_busses to the | |
682 | * pci_controller structure so we enable it for AGP and not for | |
683 | * HT childs. | |
684 | * We hard code the address because of the different size of | |
685 | * the reg address cell, we shall fix that by killing struct | |
686 | * reg_property and using some accessor functions instead | |
687 | */ | |
688 | hose->first_busno = 0xf0; | |
689 | hose->last_busno = 0xff; | |
690 | has_uninorth = 1; | |
691 | hose->ops = ¯isc_pci_ops; | |
692 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
693 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
694 | ||
695 | u3_agp = hose; | |
696 | } | |
697 | ||
698 | static void __init | |
699 | setup_u3_ht(struct pci_controller* hose, struct reg_property *addr) | |
700 | { | |
701 | struct device_node *np = (struct device_node *)hose->arch_data; | |
702 | int i, cur; | |
703 | ||
704 | hose->ops = &u3_ht_pci_ops; | |
705 | ||
706 | /* We hard code the address because of the different size of | |
707 | * the reg address cell, we shall fix that by killing struct | |
708 | * reg_property and using some accessor functions instead | |
709 | */ | |
710 | hose->cfg_data = ioremap(0xf2000000, 0x02000000); | |
711 | ||
712 | /* | |
713 | * /ht node doesn't expose a "ranges" property, so we "remove" regions that | |
714 | * have been allocated to AGP. So far, this version of the code doesn't assign | |
715 | * any of the 0xfxxxxxxx "fine" memory regions to /ht. | |
716 | * We need to fix that sooner or later by either parsing all child "ranges" | |
717 | * properties or figuring out the U3 address space decoding logic and | |
718 | * then read its configuration register (if any). | |
719 | */ | |
720 | hose->io_base_phys = 0xf4000000; | |
721 | hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000); | |
722 | isa_io_base = (unsigned long) hose->io_base_virt; | |
723 | hose->io_resource.name = np->full_name; | |
724 | hose->io_resource.start = 0; | |
725 | hose->io_resource.end = 0x003fffff; | |
726 | hose->io_resource.flags = IORESOURCE_IO; | |
727 | hose->pci_mem_offset = 0; | |
728 | hose->first_busno = 0; | |
729 | hose->last_busno = 0xef; | |
730 | hose->mem_resources[0].name = np->full_name; | |
731 | hose->mem_resources[0].start = 0x80000000; | |
732 | hose->mem_resources[0].end = 0xefffffff; | |
733 | hose->mem_resources[0].flags = IORESOURCE_MEM; | |
734 | ||
735 | if (u3_agp == NULL) { | |
736 | DBG("U3 has no AGP, using full resource range\n"); | |
737 | return; | |
738 | } | |
739 | ||
740 | /* We "remove" the AGP resources from the resources allocated to HT, that | |
741 | * is we create "holes". However, that code does assumptions that so far | |
742 | * happen to be true (cross fingers...), typically that resources in the | |
743 | * AGP node are properly ordered | |
744 | */ | |
745 | cur = 0; | |
746 | for (i=0; i<3; i++) { | |
747 | struct resource *res = &u3_agp->mem_resources[i]; | |
748 | if (res->flags != IORESOURCE_MEM) | |
749 | continue; | |
750 | /* We don't care about "fine" resources */ | |
751 | if (res->start >= 0xf0000000) | |
752 | continue; | |
753 | /* Check if it's just a matter of "shrinking" us in one direction */ | |
754 | if (hose->mem_resources[cur].start == res->start) { | |
755 | DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", | |
756 | cur, hose->mem_resources[cur].start, res->end + 1); | |
757 | hose->mem_resources[cur].start = res->end + 1; | |
758 | continue; | |
759 | } | |
760 | if (hose->mem_resources[cur].end == res->end) { | |
761 | DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", | |
762 | cur, hose->mem_resources[cur].end, res->start - 1); | |
763 | hose->mem_resources[cur].end = res->start - 1; | |
764 | continue; | |
765 | } | |
766 | /* No, it's not the case, we need a hole */ | |
767 | if (cur == 2) { | |
768 | /* not enough resources to make a hole, we drop part of the range */ | |
769 | printk(KERN_WARNING "Running out of resources for /ht host !\n"); | |
770 | hose->mem_resources[cur].end = res->start - 1; | |
771 | continue; | |
772 | } | |
773 | cur++; | |
774 | DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", | |
775 | cur-1, res->start - 1, cur, res->end + 1); | |
776 | hose->mem_resources[cur].name = np->full_name; | |
777 | hose->mem_resources[cur].flags = IORESOURCE_MEM; | |
778 | hose->mem_resources[cur].start = res->end + 1; | |
779 | hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; | |
780 | hose->mem_resources[cur-1].end = res->start - 1; | |
781 | } | |
782 | } | |
783 | ||
784 | #endif /* CONFIG_POWER4 */ | |
785 | ||
786 | void __init | |
787 | setup_grackle(struct pci_controller *hose) | |
788 | { | |
789 | setup_indirect_pci(hose, 0xfec00000, 0xfee00000); | |
790 | if (machine_is_compatible("AAPL,PowerBook1998")) | |
791 | grackle_set_loop_snoop(hose, 1); | |
792 | #if 0 /* Disabled for now, HW problems ??? */ | |
793 | grackle_set_stg(hose, 1); | |
794 | #endif | |
795 | } | |
796 | ||
797 | /* | |
798 | * We assume that if we have a G3 powermac, we have one bridge called | |
799 | * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, | |
800 | * if we have one or more bandit or chaos bridges, we don't have a MPC106. | |
801 | */ | |
802 | static int __init | |
803 | add_bridge(struct device_node *dev) | |
804 | { | |
805 | int len; | |
806 | struct pci_controller *hose; | |
807 | struct reg_property *addr; | |
808 | char* disp_name; | |
809 | int *bus_range; | |
810 | int primary = 1; | |
811 | ||
812 | DBG("Adding PCI host bridge %s\n", dev->full_name); | |
813 | ||
814 | addr = (struct reg_property *) get_property(dev, "reg", &len); | |
815 | if (addr == NULL || len < sizeof(*addr)) { | |
816 | printk(KERN_WARNING "Can't use %s: no address\n", | |
817 | dev->full_name); | |
818 | return -ENODEV; | |
819 | } | |
820 | bus_range = (int *) get_property(dev, "bus-range", &len); | |
821 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
822 | printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", | |
823 | dev->full_name); | |
824 | } | |
825 | ||
826 | hose = pcibios_alloc_controller(); | |
827 | if (!hose) | |
828 | return -ENOMEM; | |
829 | hose->arch_data = dev; | |
830 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
831 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
832 | ||
833 | disp_name = NULL; | |
834 | #ifdef CONFIG_POWER4 | |
835 | if (device_is_compatible(dev, "u3-agp")) { | |
836 | setup_u3_agp(hose, addr); | |
837 | disp_name = "U3-AGP"; | |
838 | primary = 0; | |
839 | } else if (device_is_compatible(dev, "u3-ht")) { | |
840 | setup_u3_ht(hose, addr); | |
841 | disp_name = "U3-HT"; | |
842 | primary = 1; | |
843 | } else | |
844 | #endif /* CONFIG_POWER4 */ | |
845 | if (device_is_compatible(dev, "uni-north")) { | |
846 | primary = setup_uninorth(hose, addr); | |
847 | disp_name = "UniNorth"; | |
848 | } else if (strcmp(dev->name, "pci") == 0) { | |
849 | /* XXX assume this is a mpc106 (grackle) */ | |
850 | setup_grackle(hose); | |
851 | disp_name = "Grackle (MPC106)"; | |
852 | } else if (strcmp(dev->name, "bandit") == 0) { | |
853 | setup_bandit(hose, addr); | |
854 | disp_name = "Bandit"; | |
855 | } else if (strcmp(dev->name, "chaos") == 0) { | |
856 | setup_chaos(hose, addr); | |
857 | disp_name = "Chaos"; | |
858 | primary = 0; | |
859 | } | |
860 | printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n", | |
861 | disp_name, addr->address, hose->first_busno, hose->last_busno); | |
862 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", | |
863 | hose, hose->cfg_addr, hose->cfg_data); | |
864 | ||
865 | /* Interpret the "ranges" property */ | |
866 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
867 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
868 | ||
869 | /* Fixup "bus-range" OF property */ | |
870 | fixup_bus_range(dev); | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
875 | static void __init | |
876 | pcibios_fixup_OF_interrupts(void) | |
877 | { | |
878 | struct pci_dev* dev = NULL; | |
879 | ||
880 | /* | |
881 | * Open Firmware often doesn't initialize the | |
882 | * PCI_INTERRUPT_LINE config register properly, so we | |
883 | * should find the device node and apply the interrupt | |
884 | * obtained from the OF device-tree | |
885 | */ | |
886 | for_each_pci_dev(dev) { | |
887 | struct device_node *node; | |
888 | node = pci_device_to_OF_node(dev); | |
889 | /* this is the node, see if it has interrupts */ | |
890 | if (node && node->n_intrs > 0) | |
891 | dev->irq = node->intrs[0].line; | |
892 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | |
893 | } | |
894 | } | |
895 | ||
896 | void __init | |
897 | pmac_pcibios_fixup(void) | |
898 | { | |
899 | /* Fixup interrupts according to OF tree */ | |
900 | pcibios_fixup_OF_interrupts(); | |
901 | } | |
902 | ||
903 | int __pmac | |
904 | pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) | |
905 | { | |
906 | struct device_node* node; | |
907 | int updatecfg = 0; | |
908 | int uninorth_child; | |
909 | ||
910 | node = pci_device_to_OF_node(dev); | |
911 | ||
912 | /* We don't want to enable USB controllers absent from the OF tree | |
913 | * (iBook second controller) | |
914 | */ | |
915 | if (dev->vendor == PCI_VENDOR_ID_APPLE | |
916 | && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) | |
917 | && !node) { | |
918 | printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", | |
919 | pci_name(dev)); | |
920 | return -EINVAL; | |
921 | } | |
922 | ||
923 | if (!node) | |
924 | return 0; | |
925 | ||
926 | uninorth_child = node->parent && | |
927 | device_is_compatible(node->parent, "uni-north"); | |
928 | ||
929 | /* Firewire & GMAC were disabled after PCI probe, the driver is | |
930 | * claiming them, we must re-enable them now. | |
931 | */ | |
932 | if (uninorth_child && !strcmp(node->name, "firewire") && | |
933 | (device_is_compatible(node, "pci106b,18") || | |
934 | device_is_compatible(node, "pci106b,30") || | |
935 | device_is_compatible(node, "pci11c1,5811"))) { | |
936 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); | |
937 | pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); | |
938 | updatecfg = 1; | |
939 | } | |
940 | if (uninorth_child && !strcmp(node->name, "ethernet") && | |
941 | device_is_compatible(node, "gmac")) { | |
942 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); | |
943 | updatecfg = 1; | |
944 | } | |
945 | ||
946 | if (updatecfg) { | |
947 | u16 cmd; | |
948 | ||
949 | /* | |
950 | * Make sure PCI is correctly configured | |
951 | * | |
952 | * We use old pci_bios versions of the function since, by | |
953 | * default, gmac is not powered up, and so will be absent | |
954 | * from the kernel initial PCI lookup. | |
955 | * | |
956 | * Should be replaced by 2.4 new PCI mechanisms and really | |
957 | * register the device. | |
958 | */ | |
959 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
960 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; | |
961 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
962 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); | |
963 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | /* We power down some devices after they have been probed. They'll | |
970 | * be powered back on later on | |
971 | */ | |
972 | void __init | |
973 | pmac_pcibios_after_init(void) | |
974 | { | |
975 | struct device_node* nd; | |
976 | ||
977 | #ifdef CONFIG_BLK_DEV_IDE | |
978 | struct pci_dev *dev = NULL; | |
979 | ||
980 | /* OF fails to initialize IDE controllers on macs | |
981 | * (and maybe other machines) | |
982 | * | |
983 | * Ideally, this should be moved to the IDE layer, but we need | |
984 | * to check specifically with Andre Hedrick how to do it cleanly | |
985 | * since the common IDE code seem to care about the fact that the | |
986 | * BIOS may have disabled a controller. | |
987 | * | |
988 | * -- BenH | |
989 | */ | |
990 | for_each_pci_dev(dev) { | |
991 | if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) | |
992 | pci_enable_device(dev); | |
993 | } | |
994 | #endif /* CONFIG_BLK_DEV_IDE */ | |
995 | ||
996 | nd = find_devices("firewire"); | |
997 | while (nd) { | |
998 | if (nd->parent && (device_is_compatible(nd, "pci106b,18") || | |
999 | device_is_compatible(nd, "pci106b,30") || | |
1000 | device_is_compatible(nd, "pci11c1,5811")) | |
1001 | && device_is_compatible(nd->parent, "uni-north")) { | |
1002 | pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); | |
1003 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); | |
1004 | } | |
1005 | nd = nd->next; | |
1006 | } | |
1007 | nd = find_devices("ethernet"); | |
1008 | while (nd) { | |
1009 | if (nd->parent && device_is_compatible(nd, "gmac") | |
1010 | && device_is_compatible(nd->parent, "uni-north")) | |
1011 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); | |
1012 | nd = nd->next; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | void pmac_pci_fixup_cardbus(struct pci_dev* dev) | |
1017 | { | |
1018 | if (_machine != _MACH_Pmac) | |
1019 | return; | |
1020 | /* | |
1021 | * Fix the interrupt routing on the various cardbus bridges | |
1022 | * used on powerbooks | |
1023 | */ | |
1024 | if (dev->vendor != PCI_VENDOR_ID_TI) | |
1025 | return; | |
1026 | if (dev->device == PCI_DEVICE_ID_TI_1130 || | |
1027 | dev->device == PCI_DEVICE_ID_TI_1131) { | |
1028 | u8 val; | |
1029 | /* Enable PCI interrupt */ | |
1030 | if (pci_read_config_byte(dev, 0x91, &val) == 0) | |
1031 | pci_write_config_byte(dev, 0x91, val | 0x30); | |
1032 | /* Disable ISA interrupt mode */ | |
1033 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1034 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1035 | } | |
1036 | if (dev->device == PCI_DEVICE_ID_TI_1210 || | |
1037 | dev->device == PCI_DEVICE_ID_TI_1211 || | |
1038 | dev->device == PCI_DEVICE_ID_TI_1410 || | |
1039 | dev->device == PCI_DEVICE_ID_TI_1510) { | |
1040 | u8 val; | |
1041 | /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA | |
1042 | signal out the MFUNC0 pin */ | |
1043 | if (pci_read_config_byte(dev, 0x8c, &val) == 0) | |
1044 | pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); | |
1045 | /* Disable ISA interrupt mode */ | |
1046 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1047 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); | |
1052 | ||
1053 | void pmac_pci_fixup_pciata(struct pci_dev* dev) | |
1054 | { | |
1055 | u8 progif = 0; | |
1056 | ||
1057 | /* | |
1058 | * On PowerMacs, we try to switch any PCI ATA controller to | |
1059 | * fully native mode | |
1060 | */ | |
1061 | if (_machine != _MACH_Pmac) | |
1062 | return; | |
1063 | /* Some controllers don't have the class IDE */ | |
1064 | if (dev->vendor == PCI_VENDOR_ID_PROMISE) | |
1065 | switch(dev->device) { | |
1066 | case PCI_DEVICE_ID_PROMISE_20246: | |
1067 | case PCI_DEVICE_ID_PROMISE_20262: | |
1068 | case PCI_DEVICE_ID_PROMISE_20263: | |
1069 | case PCI_DEVICE_ID_PROMISE_20265: | |
1070 | case PCI_DEVICE_ID_PROMISE_20267: | |
1071 | case PCI_DEVICE_ID_PROMISE_20268: | |
1072 | case PCI_DEVICE_ID_PROMISE_20269: | |
1073 | case PCI_DEVICE_ID_PROMISE_20270: | |
1074 | case PCI_DEVICE_ID_PROMISE_20271: | |
1075 | case PCI_DEVICE_ID_PROMISE_20275: | |
1076 | case PCI_DEVICE_ID_PROMISE_20276: | |
1077 | case PCI_DEVICE_ID_PROMISE_20277: | |
1078 | goto good; | |
1079 | } | |
1080 | /* Others, check PCI class */ | |
1081 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
1082 | return; | |
1083 | good: | |
1084 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1085 | if ((progif & 5) != 5) { | |
1086 | printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev)); | |
1087 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
1088 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
1089 | (progif & 5) != 5) | |
1090 | printk(KERN_ERR "Rewrite of PROGIF failed !\n"); | |
1091 | } | |
1092 | } | |
1093 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); | |
1094 | ||
1095 | ||
1096 | /* | |
1097 | * Disable second function on K2-SATA, it's broken | |
1098 | * and disable IO BARs on first one | |
1099 | */ | |
1100 | void __pmac pmac_pci_fixup_k2_sata(struct pci_dev* dev) | |
1101 | { | |
1102 | int i; | |
1103 | u16 cmd; | |
1104 | ||
1105 | if (PCI_FUNC(dev->devfn) > 0) { | |
1106 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1107 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
1108 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1109 | for (i = 0; i < 6; i++) { | |
1110 | dev->resource[i].start = dev->resource[i].end = 0; | |
1111 | dev->resource[i].flags = 0; | |
1112 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); | |
1113 | } | |
1114 | } else { | |
1115 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1116 | cmd &= ~PCI_COMMAND_IO; | |
1117 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1118 | for (i = 0; i < 5; i++) { | |
1119 | dev->resource[i].start = dev->resource[i].end = 0; | |
1120 | dev->resource[i].flags = 0; | |
1121 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); | |
1122 | } | |
1123 | } | |
1124 | } | |
1125 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, pmac_pci_fixup_k2_sata); |