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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Board setup routines for the Radstone PPC7D boards. |
3 | * | |
4 | * Author: James Chapman <jchapman@katalix.com> | |
5 | * | |
6 | * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il | |
7 | * Based on code done by - Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
15 | /* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs, | |
16 | * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse, | |
17 | * 4 serial ports, 2 high speed serial ports (MPSCs) and optional | |
18 | * SCSI / VGA. | |
19 | */ | |
20 | ||
1da177e4 LT |
21 | #include <linux/stddef.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/reboot.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/kdev_t.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/initrd.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/delay.h> | |
1da177e4 LT |
32 | #include <linux/seq_file.h> |
33 | #include <linux/root_dev.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/tty.h> /* for linux/serial_core.h */ | |
36 | #include <linux/serial_core.h> | |
b187f180 | 37 | #include <linux/serial_8250.h> |
1da177e4 LT |
38 | #include <linux/mv643xx.h> |
39 | #include <linux/netdevice.h> | |
d052d1be | 40 | #include <linux/platform_device.h> |
1da177e4 LT |
41 | |
42 | #include <asm/system.h> | |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/page.h> | |
45 | #include <asm/time.h> | |
46 | #include <asm/dma.h> | |
47 | #include <asm/io.h> | |
48 | #include <asm/machdep.h> | |
49 | #include <asm/prom.h> | |
50 | #include <asm/smp.h> | |
51 | #include <asm/vga.h> | |
52 | #include <asm/open_pic.h> | |
53 | #include <asm/i8259.h> | |
54 | #include <asm/todc.h> | |
55 | #include <asm/bootinfo.h> | |
56 | #include <asm/mpc10x.h> | |
57 | #include <asm/pci-bridge.h> | |
58 | #include <asm/mv64x60.h> | |
1da177e4 LT |
59 | |
60 | #include "radstone_ppc7d.h" | |
61 | ||
62 | #undef DEBUG | |
63 | ||
64 | #define PPC7D_RST_PIN 17 /* GPP17 */ | |
65 | ||
66 | extern u32 mv64360_irq_base; | |
a497aa20 | 67 | extern spinlock_t rtc_lock; |
1da177e4 LT |
68 | |
69 | static struct mv64x60_handle bh; | |
70 | static int ppc7d_has_alma; | |
71 | ||
72 | extern void gen550_progress(char *, unsigned short); | |
73 | extern void gen550_init(int, struct uart_port *); | |
74 | ||
a497aa20 CE |
75 | /* FIXME - move to h file */ |
76 | extern int ds1337_do_command(int id, int cmd, void *arg); | |
77 | #define DS1337_GET_DATE 0 | |
78 | #define DS1337_SET_DATE 1 | |
79 | ||
1da177e4 LT |
80 | /* residual data */ |
81 | unsigned char __res[sizeof(bd_t)]; | |
82 | ||
83 | /***************************************************************************** | |
84 | * Serial port code | |
85 | *****************************************************************************/ | |
86 | ||
87 | #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) | |
88 | static void __init ppc7d_early_serial_map(void) | |
89 | { | |
90 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
91 | mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); | |
92 | #elif defined(CONFIG_SERIAL_8250) | |
93 | struct uart_port serial_req; | |
94 | ||
95 | /* Setup serial port access */ | |
96 | memset(&serial_req, 0, sizeof(serial_req)); | |
97 | serial_req.uartclk = UART_CLK; | |
98 | serial_req.irq = 4; | |
99 | serial_req.flags = STD_COM_FLAGS; | |
9b4a1617 | 100 | serial_req.iotype = UPIO_MEM; |
1da177e4 LT |
101 | serial_req.membase = (u_char *) PPC7D_SERIAL_0; |
102 | ||
103 | gen550_init(0, &serial_req); | |
104 | if (early_serial_setup(&serial_req) != 0) | |
105 | printk(KERN_ERR "Early serial init of port 0 failed\n"); | |
106 | ||
107 | /* Assume early_serial_setup() doesn't modify serial_req */ | |
108 | serial_req.line = 1; | |
109 | serial_req.irq = 3; | |
110 | serial_req.membase = (u_char *) PPC7D_SERIAL_1; | |
111 | ||
112 | gen550_init(1, &serial_req); | |
113 | if (early_serial_setup(&serial_req) != 0) | |
114 | printk(KERN_ERR "Early serial init of port 1 failed\n"); | |
115 | #else | |
116 | #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX | |
117 | #endif | |
118 | } | |
119 | #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */ | |
120 | ||
121 | /***************************************************************************** | |
122 | * Low-level board support code | |
123 | *****************************************************************************/ | |
124 | ||
125 | static unsigned long __init ppc7d_find_end_of_memory(void) | |
126 | { | |
127 | bd_t *bp = (bd_t *) __res; | |
128 | ||
129 | if (bp->bi_memsize) | |
130 | return bp->bi_memsize; | |
131 | ||
132 | return (256 * 1024 * 1024); | |
133 | } | |
134 | ||
135 | static void __init ppc7d_map_io(void) | |
136 | { | |
137 | /* remove temporary mapping */ | |
138 | mtspr(SPRN_DBAT3U, 0x00000000); | |
139 | mtspr(SPRN_DBAT3L, 0x00000000); | |
140 | ||
141 | io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO); | |
142 | io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); | |
143 | } | |
144 | ||
145 | static void ppc7d_restart(char *cmd) | |
146 | { | |
147 | u32 data; | |
148 | ||
149 | /* Disable GPP17 interrupt */ | |
150 | data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
151 | data &= ~(1 << PPC7D_RST_PIN); | |
152 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data); | |
153 | ||
154 | /* Configure MPP17 as GPP */ | |
155 | data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); | |
156 | data &= ~(0x0000000f << 4); | |
157 | mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); | |
158 | ||
159 | /* Enable pin GPP17 for output */ | |
160 | data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL); | |
161 | data |= (1 << PPC7D_RST_PIN); | |
162 | mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data); | |
163 | ||
164 | /* Toggle GPP9 pin to reset the board */ | |
165 | mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN); | |
166 | mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN); | |
167 | ||
168 | for (;;) ; /* Spin until reset happens */ | |
169 | /* NOTREACHED */ | |
170 | } | |
171 | ||
172 | static void ppc7d_power_off(void) | |
173 | { | |
174 | u32 data; | |
175 | ||
176 | local_irq_disable(); | |
177 | ||
178 | /* Ensure that internal MV643XX watchdog is disabled. | |
179 | * The Disco watchdog uses MPP17 on this hardware. | |
180 | */ | |
181 | data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); | |
182 | data &= ~(0x0000000f << 4); | |
183 | mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); | |
184 | ||
185 | data = mv64x60_read(&bh, MV64x60_WDT_WDC); | |
186 | if (data & 0x80000000) { | |
187 | mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24); | |
188 | mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24); | |
189 | } | |
190 | ||
191 | for (;;) ; /* No way to shut power off with software */ | |
192 | /* NOTREACHED */ | |
193 | } | |
194 | ||
195 | static void ppc7d_halt(void) | |
196 | { | |
197 | ppc7d_power_off(); | |
198 | /* NOTREACHED */ | |
199 | } | |
200 | ||
201 | static unsigned long ppc7d_led_no_pulse; | |
202 | ||
203 | static int __init ppc7d_led_pulse_disable(char *str) | |
204 | { | |
205 | ppc7d_led_no_pulse = 1; | |
206 | return 1; | |
207 | } | |
208 | ||
209 | /* This kernel option disables the heartbeat pulsing of a board LED */ | |
210 | __setup("ledoff", ppc7d_led_pulse_disable); | |
211 | ||
212 | static void ppc7d_heartbeat(void) | |
213 | { | |
214 | u32 data32; | |
215 | u8 data8; | |
216 | static int max706_wdog = 0; | |
217 | ||
218 | /* Unfortunately we can't access the LED control registers | |
219 | * during early init because they're on the CPLD which is the | |
220 | * other side of a PCI bridge which goes unreachable during | |
221 | * PCI scan. So write the LEDs only if the MV64360 watchdog is | |
222 | * enabled (i.e. userspace apps are running so kernel is up).. | |
223 | */ | |
224 | data32 = mv64x60_read(&bh, MV64x60_WDT_WDC); | |
225 | if (data32 & 0x80000000) { | |
226 | /* Enable MAX706 watchdog if not done already */ | |
227 | if (!max706_wdog) { | |
228 | outb(3, PPC7D_CPLD_RESET); | |
229 | max706_wdog = 1; | |
230 | } | |
231 | ||
232 | /* Hit the MAX706 watchdog */ | |
233 | outb(0, PPC7D_CPLD_WATCHDOG_TRIG); | |
234 | ||
235 | /* Pulse LED DS219 if not disabled */ | |
236 | if (!ppc7d_led_no_pulse) { | |
237 | static int led_on = 0; | |
238 | ||
239 | data8 = inb(PPC7D_CPLD_LEDS); | |
240 | if (led_on) | |
241 | data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK; | |
242 | else | |
243 | data8 |= PPC7D_CPLD_LEDS_DS219_MASK; | |
244 | ||
245 | outb(data8, PPC7D_CPLD_LEDS); | |
246 | led_on = !led_on; | |
247 | } | |
248 | } | |
249 | ppc_md.heartbeat_count = ppc_md.heartbeat_reset; | |
250 | } | |
251 | ||
252 | static int ppc7d_show_cpuinfo(struct seq_file *m) | |
253 | { | |
254 | u8 val; | |
255 | u8 val1, val2; | |
256 | static int flash_sizes[4] = { 64, 32, 0, 16 }; | |
257 | static int flash_banks[4] = { 4, 3, 2, 1 }; | |
630710e3 CE |
258 | static int sdram_bank_sizes[4] = { 128, 256, 512, 1 }; |
259 | int sdram_num_banks = 2; | |
1da177e4 LT |
260 | static char *pci_modes[] = { "PCI33", "PCI66", |
261 | "Unknown", "Unknown", | |
262 | "PCIX33", "PCIX66", | |
263 | "PCIX100", "PCIX133" | |
264 | }; | |
265 | ||
266 | seq_printf(m, "vendor\t\t: Radstone Technology\n"); | |
267 | seq_printf(m, "machine\t\t: PPC7D\n"); | |
268 | ||
269 | val = inb(PPC7D_CPLD_BOARD_REVISION); | |
270 | val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5; | |
271 | val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK); | |
272 | seq_printf(m, "revision\t: %hd%c%c\n", | |
273 | val1, | |
274 | (val2 <= 0x18) ? 'A' + val2 : 'Y', | |
275 | (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' '); | |
276 | ||
277 | val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE); | |
278 | val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK; | |
279 | val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK | | |
280 | PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK); | |
281 | seq_printf(m, "bus speed\t: %dMHz\n", | |
282 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 : | |
283 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 : | |
284 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0); | |
285 | ||
630710e3 CE |
286 | val = inb(PPC7D_CPLD_MEM_CONFIG); |
287 | if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--; | |
288 | ||
1da177e4 | 289 | val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND); |
630710e3 CE |
290 | val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6; |
291 | seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c", | |
292 | sdram_num_banks, | |
293 | sdram_bank_sizes[val1], | |
294 | (sdram_bank_sizes[val1] < 128) ? 'G' : 'M', | |
295 | sdram_num_banks * sdram_bank_sizes[val1], | |
296 | (sdram_bank_sizes[val1] < 128) ? 'G' : 'M'); | |
1da177e4 LT |
297 | if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) { |
298 | seq_printf(m, " [ECC %sabled]", | |
299 | (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" : | |
300 | "dis"); | |
301 | } | |
302 | seq_printf(m, "\n"); | |
303 | ||
304 | val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK); | |
305 | val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2; | |
306 | seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n", | |
307 | flash_banks[val2], flash_sizes[val1], | |
308 | flash_banks[val2] * flash_sizes[val1]); | |
309 | ||
310 | val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL); | |
311 | val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); | |
312 | seq_printf(m, " write links\t: %s%s%s%s\n", | |
313 | (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "", | |
314 | (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "", | |
315 | (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "", | |
316 | (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK | | |
317 | PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK | | |
318 | PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) == | |
319 | 0 ? "NONE" : ""); | |
320 | seq_printf(m, " write sector h/w enables: %s%s%s%s%s\n", | |
321 | (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " : | |
322 | "", | |
323 | (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "", | |
324 | (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "", | |
325 | (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " : | |
326 | "", | |
327 | (((val & | |
328 | (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK | | |
329 | PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK | | |
330 | PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0) | |
331 | && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) == | |
332 | 0)) ? "NONE" : ""); | |
333 | val1 = | |
334 | inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) & | |
335 | (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK | | |
336 | PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK); | |
337 | seq_printf(m, " software sector enables: %s%s%s\n", | |
338 | (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT " | |
339 | : "", | |
340 | (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "", | |
341 | (val1 == 0) ? "NONE " : ""); | |
342 | ||
343 | seq_printf(m, "Boot options\t: %s%s%s%s\n", | |
344 | (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ? | |
345 | "ALTERNATE " : "", | |
346 | (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " : | |
347 | "", | |
348 | (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY " | |
349 | : "", | |
350 | ((val & | |
351 | (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK | | |
352 | PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK | | |
353 | PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) == | |
354 | 0) ? "NONE" : ""); | |
355 | ||
356 | val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1); | |
357 | seq_printf(m, "Fitted modules\t: %s%s%s%s\n", | |
358 | (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ", | |
359 | (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ", | |
360 | (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "", | |
361 | ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK | | |
362 | PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK | | |
363 | PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) == | |
364 | (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK | | |
365 | PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : ""); | |
366 | ||
367 | if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) { | |
368 | static const char *ids[] = { | |
369 | "unknown", | |
370 | "1553 (Dual Channel)", | |
371 | "1553 (Single Channel)", | |
372 | "8-bit SCSI + VGA", | |
373 | "16-bit SCSI + VGA", | |
374 | "1553 (Single Channel with sideband)", | |
375 | "1553 (Dual Channel with sideband)", | |
376 | NULL | |
377 | }; | |
378 | u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03); | |
379 | seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id, | |
380 | id < 7 ? ids[id] : "unknown"); | |
381 | } | |
382 | ||
383 | val = inb(PPC7D_CPLD_PCI_CONFIG); | |
384 | val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4; | |
385 | val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK); | |
386 | seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n", | |
387 | pci_modes[val1], pci_modes[val2]); | |
388 | ||
389 | val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2); | |
390 | seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n", | |
391 | (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v", | |
392 | (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v"); | |
393 | seq_printf(m, "PMC power source: %s\n", | |
394 | (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" : | |
395 | "internal"); | |
396 | ||
397 | val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4); | |
398 | val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2); | |
399 | seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n", | |
400 | (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "", | |
401 | (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "", | |
402 | (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "", | |
403 | (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "", | |
404 | (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "", | |
405 | (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "", | |
406 | (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " : | |
407 | ""); | |
408 | ||
409 | val = inb(PPC7D_CPLD_ID_LINK); | |
410 | val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK | | |
411 | PPC7D_CPLD_ID_LINK_E7_MASK | | |
412 | PPC7D_CPLD_ID_LINK_E12_MASK | | |
413 | PPC7D_CPLD_ID_LINK_E13_MASK); | |
414 | ||
415 | val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) & | |
416 | (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK | | |
417 | PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK | | |
418 | PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK); | |
419 | ||
420 | seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n", | |
421 | (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "", | |
422 | (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "", | |
423 | (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "", | |
424 | (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "", | |
425 | (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "", | |
426 | (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "", | |
427 | (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "", | |
428 | ((val == 0) && (val1 == 0)) ? "NONE" : ""); | |
429 | ||
430 | val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK); | |
431 | seq_printf(m, "Front panel reset switch: %sabled\n", | |
432 | (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en"); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static void __init ppc7d_calibrate_decr(void) | |
438 | { | |
439 | ulong freq; | |
440 | ||
441 | freq = 100000000 / 4; | |
442 | ||
443 | pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n", | |
444 | freq / 1000000, freq % 1000000); | |
445 | ||
446 | tb_ticks_per_jiffy = freq / HZ; | |
447 | tb_to_us = mulhwu_scale_factor(freq, 1000000); | |
448 | } | |
449 | ||
450 | /***************************************************************************** | |
451 | * Interrupt stuff | |
452 | *****************************************************************************/ | |
453 | ||
39e3eb72 | 454 | static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id) |
1da177e4 LT |
455 | { |
456 | u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); | |
457 | if (temp & (1 << 28)) { | |
39e3eb72 | 458 | i8259_irq(); |
1da177e4 LT |
459 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28))); |
460 | return IRQ_HANDLED; | |
461 | } | |
462 | ||
463 | return IRQ_NONE; | |
464 | } | |
465 | ||
466 | /* | |
467 | * Each interrupt cause is assigned an IRQ number. | |
468 | * Southbridge has 16*2 (two 8259's) interrupts. | |
469 | * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32). | |
470 | * If multiple interrupts are pending, get_irq() returns the | |
471 | * lowest pending irq number first. | |
472 | * | |
473 | * | |
474 | * IRQ # Source Trig Active | |
475 | * ============================================================= | |
476 | * | |
477 | * Southbridge | |
478 | * ----------- | |
479 | * IRQ # Source Trig | |
480 | * ============================================================= | |
481 | * 0 ISA High Resolution Counter Edge | |
482 | * 1 Keyboard Edge | |
483 | * 2 Cascade From (IRQ 8-15) Edge | |
484 | * 3 Com 2 (Uart 2) Edge | |
485 | * 4 Com 1 (Uart 1) Edge | |
486 | * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level | |
487 | * 6 GPIO Level | |
488 | * 7 LPT Edge | |
489 | * 8 RTC Alarm Edge | |
490 | * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level | |
491 | * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level | |
492 | * 11 USB2 Level | |
493 | * 12 Mouse Edge | |
494 | * 13 Reserved internally by Ali M1535+ | |
495 | * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level | |
496 | * 15 COM 5/6 Level | |
497 | * | |
498 | * 16..112 Discovery-II... | |
499 | * | |
500 | * MPP28 Southbridge Edge High | |
501 | * | |
502 | * | |
503 | * Interrupts are cascaded through to the Discovery-II. | |
504 | * | |
505 | * PCI --- | |
506 | * \ | |
507 | * CPLD --> ALI1535 -------> DISCOVERY-II | |
508 | * INTF MPP28 | |
509 | */ | |
510 | static void __init ppc7d_init_irq(void) | |
511 | { | |
512 | int irq; | |
513 | ||
514 | pr_debug("%s\n", __FUNCTION__); | |
f9bd170a | 515 | i8259_init(0, 0); |
1da177e4 LT |
516 | mv64360_init_irq(); |
517 | ||
1da177e4 LT |
518 | /* IRQs 5,6,9,10,11,14,15 are level sensitive */ |
519 | irq_desc[5].status |= IRQ_LEVEL; | |
520 | irq_desc[6].status |= IRQ_LEVEL; | |
521 | irq_desc[9].status |= IRQ_LEVEL; | |
522 | irq_desc[10].status |= IRQ_LEVEL; | |
523 | irq_desc[11].status |= IRQ_LEVEL; | |
524 | irq_desc[14].status |= IRQ_LEVEL; | |
525 | irq_desc[15].status |= IRQ_LEVEL; | |
526 | ||
527 | /* GPP28 is edge triggered */ | |
528 | irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL; | |
529 | } | |
530 | ||
531 | static u32 ppc7d_irq_canonicalize(u32 irq) | |
532 | { | |
533 | if ((irq >= 16) && (irq < (16 + 96))) | |
534 | irq -= 16; | |
535 | ||
536 | return irq; | |
537 | } | |
538 | ||
39e3eb72 | 539 | static int ppc7d_get_irq(void) |
1da177e4 LT |
540 | { |
541 | int irq; | |
542 | ||
39e3eb72 | 543 | irq = mv64360_get_irq(); |
1da177e4 | 544 | if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28)) |
39e3eb72 | 545 | irq = i8259_irq(); |
1da177e4 LT |
546 | return irq; |
547 | } | |
548 | ||
549 | /* | |
550 | * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level | |
551 | * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level | |
552 | * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level | |
553 | * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level | |
554 | */ | |
555 | static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel, | |
556 | unsigned char pin) | |
557 | { | |
558 | static const char pci_irq_table[][4] = | |
559 | /* | |
560 | * PCI IDSEL/INTPIN->INTLINE | |
561 | * A B C D | |
562 | */ | |
563 | { | |
564 | {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */ | |
565 | {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */ | |
566 | {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */ | |
567 | {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */ | |
568 | }; | |
569 | const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4; | |
570 | ||
571 | pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__, | |
572 | dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin); | |
573 | ||
574 | return PCI_IRQ_TABLE_LOOKUP; | |
575 | } | |
576 | ||
577 | void __init ppc7d_intr_setup(void) | |
578 | { | |
579 | u32 data; | |
580 | ||
581 | /* | |
582 | * Define GPP 28 interrupt polarity as active high | |
583 | * input signal and level triggered | |
584 | */ | |
585 | data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL); | |
586 | data &= ~(1 << 28); | |
587 | mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data); | |
588 | data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL); | |
589 | data &= ~(1 << 28); | |
590 | mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data); | |
591 | ||
592 | /* Config GPP intr ctlr to respond to level trigger */ | |
593 | data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL); | |
594 | data |= (1 << 10); | |
595 | mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data); | |
596 | ||
597 | /* XXXX Erranum FEr PCI-#8 */ | |
598 | data = mv64x60_read(&bh, MV64x60_PCI0_CMD); | |
599 | data &= ~((1 << 5) | (1 << 9)); | |
600 | mv64x60_write(&bh, MV64x60_PCI0_CMD, data); | |
601 | data = mv64x60_read(&bh, MV64x60_PCI1_CMD); | |
602 | data &= ~((1 << 5) | (1 << 9)); | |
603 | mv64x60_write(&bh, MV64x60_PCI1_CMD, data); | |
604 | ||
605 | /* | |
606 | * Dismiss and then enable interrupt on GPP interrupt cause | |
607 | * for CPU #0 | |
608 | */ | |
609 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28)); | |
610 | data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
611 | data |= (1 << 28); | |
612 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data); | |
613 | ||
614 | /* | |
615 | * Dismiss and then enable interrupt on CPU #0 high cause reg | |
616 | * BIT27 summarizes GPP interrupts 23-31 | |
617 | */ | |
618 | mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27)); | |
619 | data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI); | |
620 | data |= (1 << 27); | |
621 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data); | |
622 | } | |
623 | ||
624 | /***************************************************************************** | |
625 | * Platform device data fixup routines. | |
626 | *****************************************************************************/ | |
627 | ||
628 | #if defined(CONFIG_SERIAL_MPSC) | |
629 | static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev) | |
630 | { | |
631 | struct mpsc_pdata *pdata; | |
632 | ||
633 | pdata = (struct mpsc_pdata *)pdev->dev.platform_data; | |
634 | ||
635 | pdata->max_idle = 40; | |
636 | pdata->default_baud = PPC7D_DEFAULT_BAUD; | |
637 | pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC; | |
638 | pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ; | |
639 | ||
640 | return; | |
641 | } | |
642 | #endif | |
643 | ||
644 | #if defined(CONFIG_MV643XX_ETH) | |
645 | static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev) | |
646 | { | |
647 | struct mv643xx_eth_platform_data *eth_pd; | |
648 | static u16 phy_addr[] = { | |
649 | PPC7D_ETH0_PHY_ADDR, | |
650 | PPC7D_ETH1_PHY_ADDR, | |
651 | PPC7D_ETH2_PHY_ADDR, | |
652 | }; | |
653 | int i; | |
654 | ||
655 | eth_pd = pdev->dev.platform_data; | |
656 | eth_pd->force_phy_addr = 1; | |
657 | eth_pd->phy_addr = phy_addr[pdev->id]; | |
658 | eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE; | |
659 | eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE; | |
660 | ||
661 | /* Adjust IRQ by mv64360_irq_base */ | |
662 | for (i = 0; i < pdev->num_resources; i++) { | |
663 | struct resource *r = &pdev->resource[i]; | |
664 | ||
665 | if (r->flags & IORESOURCE_IRQ) { | |
666 | r->start += mv64360_irq_base; | |
667 | r->end += mv64360_irq_base; | |
668 | pr_debug("%s, uses IRQ %d\n", pdev->name, | |
669 | (int)r->start); | |
670 | } | |
671 | } | |
672 | ||
673 | } | |
674 | #endif | |
675 | ||
676 | #if defined(CONFIG_I2C_MV64XXX) | |
677 | static void __init | |
678 | ppc7d_fixup_i2c_pdata(struct platform_device *pdev) | |
679 | { | |
680 | struct mv64xxx_i2c_pdata *pdata; | |
681 | int i; | |
682 | ||
683 | pdata = pdev->dev.platform_data; | |
684 | if (pdata == NULL) { | |
d116fe5a | 685 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
1da177e4 LT |
686 | if (pdata == NULL) |
687 | return; | |
688 | ||
1da177e4 LT |
689 | pdev->dev.platform_data = pdata; |
690 | } | |
691 | ||
692 | /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */ | |
693 | pdata->freq_m = 8; | |
694 | pdata->freq_n = 3; | |
695 | pdata->timeout = 500; | |
696 | pdata->retries = 3; | |
697 | ||
698 | /* Adjust IRQ by mv64360_irq_base */ | |
699 | for (i = 0; i < pdev->num_resources; i++) { | |
700 | struct resource *r = &pdev->resource[i]; | |
701 | ||
702 | if (r->flags & IORESOURCE_IRQ) { | |
703 | r->start += mv64360_irq_base; | |
704 | r->end += mv64360_irq_base; | |
705 | pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start); | |
706 | } | |
707 | } | |
708 | } | |
709 | #endif | |
710 | ||
bbbe1212 | 711 | static int ppc7d_platform_notify(struct device *dev) |
1da177e4 LT |
712 | { |
713 | static struct { | |
714 | char *bus_id; | |
715 | void ((*rtn) (struct platform_device * pdev)); | |
716 | } dev_map[] = { | |
717 | #if defined(CONFIG_SERIAL_MPSC) | |
718 | { MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata }, | |
719 | { MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata }, | |
720 | #endif | |
721 | #if defined(CONFIG_MV643XX_ETH) | |
722 | { MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata }, | |
723 | { MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata }, | |
724 | { MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata }, | |
725 | #endif | |
726 | #if defined(CONFIG_I2C_MV64XXX) | |
727 | { MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata }, | |
728 | #endif | |
729 | }; | |
730 | struct platform_device *pdev; | |
731 | int i; | |
732 | ||
733 | if (dev && dev->bus_id) | |
734 | for (i = 0; i < ARRAY_SIZE(dev_map); i++) | |
735 | if (!strncmp(dev->bus_id, dev_map[i].bus_id, | |
736 | BUS_ID_SIZE)) { | |
737 | ||
738 | pdev = container_of(dev, | |
739 | struct platform_device, | |
740 | dev); | |
741 | dev_map[i].rtn(pdev); | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | /***************************************************************************** | |
748 | * PCI device fixups. | |
749 | * These aren't really fixups per se. They are used to init devices as they | |
750 | * are found during PCI scan. | |
751 | * | |
752 | * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI | |
753 | * scan in order to find other devices on its secondary side. | |
754 | *****************************************************************************/ | |
755 | ||
756 | static void __init ppc7d_fixup_hb8(struct pci_dev *dev) | |
757 | { | |
758 | u16 val16; | |
759 | ||
760 | if (dev->bus->number == 0) { | |
761 | pr_debug("PCI: HB8 init\n"); | |
762 | ||
763 | pci_write_config_byte(dev, 0x1c, | |
764 | ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000) | |
765 | >> 8) | 0x01); | |
766 | pci_write_config_byte(dev, 0x1d, | |
767 | (((PPC7D_PCI0_IO_START_PCI_ADDR + | |
768 | PPC7D_PCI0_IO_SIZE - | |
769 | 1) & 0xf000) >> 8) | 0x01); | |
770 | pci_write_config_word(dev, 0x30, | |
771 | PPC7D_PCI0_IO_START_PCI_ADDR >> 16); | |
772 | pci_write_config_word(dev, 0x32, | |
773 | ((PPC7D_PCI0_IO_START_PCI_ADDR + | |
774 | PPC7D_PCI0_IO_SIZE - | |
775 | 1) >> 16) & 0xffff); | |
776 | ||
777 | pci_write_config_word(dev, 0x20, | |
778 | PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16); | |
779 | pci_write_config_word(dev, 0x22, | |
780 | ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + | |
781 | PPC7D_PCI0_MEM0_SIZE - | |
782 | 1) >> 16) & 0xffff); | |
783 | pci_write_config_word(dev, 0x24, 0); | |
784 | pci_write_config_word(dev, 0x26, 0); | |
785 | pci_write_config_dword(dev, 0x28, 0); | |
786 | pci_write_config_dword(dev, 0x2c, 0); | |
787 | ||
788 | pci_read_config_word(dev, 0x3e, &val16); | |
789 | val16 |= ((1 << 5) | (1 << 1)); /* signal master aborts and | |
790 | * SERR to primary | |
791 | */ | |
792 | val16 &= ~(1 << 2); /* ISA disable, so all ISA | |
793 | * ports forwarded to secondary | |
794 | */ | |
795 | pci_write_config_word(dev, 0x3e, val16); | |
796 | } | |
797 | } | |
798 | ||
799 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8); | |
800 | ||
801 | /* This should perhaps be a separate driver as we're actually initializing | |
802 | * the chip for this board here. It's hardly a fixup... | |
803 | */ | |
804 | static void __init ppc7d_fixup_ali1535(struct pci_dev *dev) | |
805 | { | |
806 | pr_debug("PCI: ALI1535 init\n"); | |
807 | ||
808 | if (dev->bus->number == 1) { | |
809 | /* Configure the ISA Port Settings */ | |
810 | pci_write_config_byte(dev, 0x43, 0x00); | |
811 | ||
812 | /* Disable PCI Interrupt polling mode */ | |
813 | pci_write_config_byte(dev, 0x45, 0x00); | |
814 | ||
815 | /* Multifunction pin select INTFJ -> INTF */ | |
816 | pci_write_config_byte(dev, 0x78, 0x00); | |
817 | ||
818 | /* Set PCI INT -> IRQ Routing control in for external | |
819 | * pins south bridge. | |
820 | */ | |
821 | pci_write_config_byte(dev, 0x48, 0x31); /* [7-4] INT B -> IRQ10 | |
822 | * [3-0] INT A -> IRQ9 | |
823 | */ | |
824 | pci_write_config_byte(dev, 0x49, 0x5D); /* [7-4] INT D -> IRQ5 | |
825 | * [3-0] INT C -> IRQ14 | |
826 | */ | |
827 | ||
828 | /* PPC7D setup */ | |
829 | /* NEC USB device on IRQ 11 (INTE) - INTF disabled */ | |
830 | pci_write_config_byte(dev, 0x4A, 0x09); | |
831 | ||
832 | /* GPIO on IRQ 6 */ | |
833 | pci_write_config_byte(dev, 0x76, 0x07); | |
834 | ||
835 | /* SIRQ I (COMS 5/6) use IRQ line 15. | |
836 | * Positive (not subtractive) address decode. | |
837 | */ | |
838 | pci_write_config_byte(dev, 0x44, 0x0f); | |
839 | ||
840 | /* SIRQ II disabled */ | |
841 | pci_write_config_byte(dev, 0x75, 0x0); | |
842 | ||
843 | /* On board USB and RTC disabled */ | |
844 | pci_write_config_word(dev, 0x52, (1 << 14)); | |
845 | pci_write_config_byte(dev, 0x74, 0x00); | |
846 | ||
847 | /* On board IDE disabled */ | |
848 | pci_write_config_byte(dev, 0x58, 0x00); | |
849 | ||
850 | /* Decode 32-bit addresses */ | |
851 | pci_write_config_byte(dev, 0x5b, 0); | |
852 | ||
853 | /* Disable docking IO */ | |
854 | pci_write_config_word(dev, 0x5c, 0x0000); | |
855 | ||
856 | /* Disable modem, enable sound */ | |
857 | pci_write_config_byte(dev, 0x77, (1 << 6)); | |
858 | ||
859 | /* Disable hot-docking mode */ | |
860 | pci_write_config_byte(dev, 0x7d, 0x00); | |
861 | } | |
862 | } | |
863 | ||
864 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535); | |
865 | ||
866 | static int ppc7d_pci_exclude_device(u8 bus, u8 devfn) | |
867 | { | |
868 | /* Early versions of this board were fitted with IBM ALMA | |
869 | * PCI-VME bridge chips. The PCI config space of these devices | |
870 | * was not set up correctly and causes PCI scan problems. | |
871 | */ | |
872 | if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma) | |
873 | return PCIBIOS_DEVICE_NOT_FOUND; | |
874 | ||
875 | return mv64x60_pci_exclude_device(bus, devfn); | |
876 | } | |
877 | ||
878 | /* This hook is called when each PCI bus is probed. | |
879 | */ | |
880 | static void ppc7d_pci_fixup_bus(struct pci_bus *bus) | |
881 | { | |
882 | pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n", | |
883 | bus->number, | |
884 | bus->resource[0] ? bus->resource[0]->start : 0, | |
885 | bus->resource[0] ? bus->resource[0]->end : 0, | |
886 | bus->resource[1] ? bus->resource[1]->start : 0, | |
887 | bus->resource[1] ? bus->resource[1]->end : 0, | |
888 | bus->resource[2] ? bus->resource[2]->start : 0, | |
889 | bus->resource[2] ? bus->resource[2]->end : 0, | |
890 | bus->resource[3] ? bus->resource[3]->start : 0, | |
891 | bus->resource[3] ? bus->resource[3]->end : 0); | |
892 | ||
893 | if ((bus->number == 1) && (bus->resource[2] != NULL)) { | |
894 | /* Hide PCI window 2 of Bus 1 which is used only to | |
895 | * map legacy ISA memory space. | |
896 | */ | |
897 | bus->resource[2]->start = 0; | |
898 | bus->resource[2]->end = 0; | |
899 | bus->resource[2]->flags = 0; | |
900 | } | |
901 | } | |
902 | ||
903 | /***************************************************************************** | |
904 | * Board device setup code | |
905 | *****************************************************************************/ | |
906 | ||
907 | void __init ppc7d_setup_peripherals(void) | |
908 | { | |
909 | u32 val32; | |
910 | ||
911 | /* Set up windows for boot CS */ | |
912 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, | |
913 | PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE, | |
914 | 0); | |
915 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); | |
916 | ||
917 | /* Boot firmware configures the following DevCS addresses. | |
918 | * DevCS0 - board control/status | |
919 | * DevCS1 - test registers | |
920 | * DevCS2 - AFIX port/address registers (for identifying) | |
921 | * DevCS3 - FLASH | |
922 | * | |
923 | * We don't use DevCS0, DevCS1. | |
924 | */ | |
925 | val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE); | |
926 | val32 |= ((1 << 4) | (1 << 5)); | |
927 | mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32); | |
928 | mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0); | |
929 | mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0); | |
930 | mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0); | |
931 | mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0); | |
932 | ||
933 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, | |
934 | PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0); | |
935 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); | |
936 | ||
937 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, | |
938 | PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0); | |
939 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); | |
940 | ||
941 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, | |
942 | PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, | |
943 | 0); | |
944 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); | |
945 | ||
946 | /* Set up Enet->SRAM window */ | |
947 | mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, | |
948 | PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, | |
949 | 0x2); | |
950 | bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); | |
951 | ||
952 | /* Give enet r/w access to memory region */ | |
953 | val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0); | |
954 | val32 |= (0x3 << (4 << 1)); | |
955 | mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32); | |
956 | val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1); | |
957 | val32 |= (0x3 << (4 << 1)); | |
958 | mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32); | |
959 | val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2); | |
960 | val32 |= (0x3 << (4 << 1)); | |
961 | mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32); | |
962 | ||
963 | val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL); | |
964 | val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)); | |
965 | mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32); | |
966 | ||
967 | /* Enumerate pci bus. | |
968 | * | |
969 | * We scan PCI#0 first (the bus with the HB8 and other | |
970 | * on-board peripherals). We must configure the 64360 before | |
971 | * each scan, according to the bus number assignments. Busses | |
972 | * are assigned incrementally, starting at 0. PCI#0 is | |
973 | * usually assigned bus#0, the secondary side of the HB8 gets | |
974 | * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if | |
975 | * any PMC card has a PCI bridge, these bus assignments will | |
976 | * change. | |
977 | */ | |
978 | ||
979 | /* Turn off PCI retries */ | |
980 | val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
981 | val32 |= (1 << 17); | |
982 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32); | |
983 | ||
984 | /* Scan PCI#0 */ | |
985 | mv64x60_set_bus(&bh, 0, 0); | |
986 | bh.hose_a->first_busno = 0; | |
987 | bh.hose_a->last_busno = 0xff; | |
988 | bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); | |
989 | printk(KERN_INFO "PCI#0: first=%d last=%d\n", | |
990 | bh.hose_a->first_busno, bh.hose_a->last_busno); | |
991 | ||
992 | /* Scan PCI#1 */ | |
993 | bh.hose_b->first_busno = bh.hose_a->last_busno + 1; | |
994 | mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); | |
995 | bh.hose_b->last_busno = 0xff; | |
996 | bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, | |
997 | bh.hose_b->first_busno); | |
998 | printk(KERN_INFO "PCI#1: first=%d last=%d\n", | |
999 | bh.hose_b->first_busno, bh.hose_b->last_busno); | |
1000 | ||
1001 | /* Turn on PCI retries */ | |
1002 | val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
1003 | val32 &= ~(1 << 17); | |
1004 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32); | |
1005 | ||
1006 | /* Setup interrupts */ | |
1007 | ppc7d_intr_setup(); | |
1008 | } | |
1009 | ||
1010 | static void __init ppc7d_setup_bridge(void) | |
1011 | { | |
1012 | struct mv64x60_setup_info si; | |
1013 | int i; | |
1014 | u32 temp; | |
1015 | ||
1016 | mv64360_irq_base = 16; /* first 16 intrs are 2 x 8259's */ | |
1017 | ||
1018 | memset(&si, 0, sizeof(si)); | |
1019 | ||
1020 | si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; | |
1021 | ||
1022 | si.pci_0.enable_bus = 1; | |
1023 | si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR; | |
1024 | si.pci_0.pci_io.pci_base_hi = 0; | |
1025 | si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR; | |
1026 | si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE; | |
1027 | si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1028 | si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR; | |
1029 | si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR; | |
1030 | si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR; | |
1031 | si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE; | |
1032 | si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1033 | si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR; | |
1034 | si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR; | |
1035 | si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR; | |
1036 | si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE; | |
1037 | si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1038 | si.pci_0.pci_cmd_bits = 0; | |
1039 | si.pci_0.latency_timer = 0x80; | |
1040 | ||
1041 | si.pci_1.enable_bus = 1; | |
1042 | si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR; | |
1043 | si.pci_1.pci_io.pci_base_hi = 0; | |
1044 | si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR; | |
1045 | si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE; | |
1046 | si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1047 | si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR; | |
1048 | si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR; | |
1049 | si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR; | |
1050 | si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE; | |
1051 | si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1052 | si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR; | |
1053 | si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR; | |
1054 | si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR; | |
1055 | si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE; | |
1056 | si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1057 | si.pci_1.pci_cmd_bits = 0; | |
1058 | si.pci_1.latency_timer = 0x80; | |
1059 | ||
1060 | /* Don't clear the SRAM window since we use it for debug */ | |
1061 | si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN); | |
1062 | ||
1063 | printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n", | |
1064 | si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size); | |
1065 | printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n", | |
1066 | si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size); | |
1067 | ||
1068 | for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { | |
1069 | #if defined(CONFIG_NOT_COHERENT_CACHE) | |
1070 | si.cpu_prot_options[i] = 0; | |
1071 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; | |
1072 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; | |
1073 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; | |
1074 | ||
1075 | si.pci_0.acc_cntl_options[i] = | |
1076 | MV64360_PCI_ACC_CNTL_SNOOP_NONE | | |
1077 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1078 | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | | |
1079 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; | |
1080 | ||
1081 | si.pci_1.acc_cntl_options[i] = | |
1082 | MV64360_PCI_ACC_CNTL_SNOOP_NONE | | |
1083 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1084 | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | | |
1085 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; | |
1086 | #else | |
1087 | si.cpu_prot_options[i] = 0; | |
1088 | /* All PPC7D hardware uses B0 or newer MV64360 silicon which | |
1089 | * does not have snoop bugs. | |
1090 | */ | |
1091 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; | |
1092 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; | |
1093 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; | |
1094 | ||
1095 | si.pci_0.acc_cntl_options[i] = | |
1096 | MV64360_PCI_ACC_CNTL_SNOOP_WB | | |
1097 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1098 | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | | |
1099 | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; | |
1100 | ||
1101 | si.pci_1.acc_cntl_options[i] = | |
1102 | MV64360_PCI_ACC_CNTL_SNOOP_WB | | |
1103 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1104 | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | | |
1105 | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; | |
1106 | #endif | |
1107 | } | |
1108 | ||
1109 | /* Lookup PCI host bridges */ | |
1110 | if (mv64x60_init(&bh, &si)) | |
1111 | printk(KERN_ERR "MV64360 initialization failed.\n"); | |
1112 | ||
1113 | pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base); | |
1114 | ||
1115 | /* Enable WB Cache coherency on SRAM */ | |
1116 | temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG); | |
1117 | pr_debug("SRAM_CONFIG: %x\n", temp); | |
1118 | #if defined(CONFIG_NOT_COHERENT_CACHE) | |
1119 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2); | |
1120 | #else | |
1121 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2); | |
1122 | #endif | |
1123 | /* If system operates with internal bus arbiter (CPU master | |
1124 | * control bit8) clear AACK Delay bit [25] in CPU | |
1125 | * configuration register. | |
1126 | */ | |
1127 | temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL); | |
1128 | if (temp & (1 << 8)) { | |
1129 | temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
1130 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25))); | |
1131 | } | |
1132 | ||
1133 | /* Data and address parity is enabled */ | |
1134 | temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
1135 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, | |
1136 | (temp | (1 << 26) | (1 << 19))); | |
1137 | ||
1138 | pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ | |
1139 | ppc_md.pci_swizzle = common_swizzle; | |
1140 | ppc_md.pci_map_irq = ppc7d_map_irq; | |
1141 | ppc_md.pci_exclude_device = ppc7d_pci_exclude_device; | |
1142 | ||
1143 | mv64x60_set_bus(&bh, 0, 0); | |
1144 | bh.hose_a->first_busno = 0; | |
1145 | bh.hose_a->last_busno = 0xff; | |
1146 | bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR; | |
1147 | bh.hose_a->mem_space.end = | |
1148 | PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE; | |
1149 | ||
1150 | /* These will be set later, as a result of PCI0 scan */ | |
1151 | bh.hose_b->first_busno = 0; | |
1152 | bh.hose_b->last_busno = 0xff; | |
1153 | bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR; | |
1154 | bh.hose_b->mem_space.end = | |
1155 | PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE; | |
1156 | ||
1157 | pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n", | |
1158 | mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50), | |
1159 | mv64x60_read(&bh, 0xf0)); | |
1160 | } | |
1161 | ||
1162 | static void __init ppc7d_setup_arch(void) | |
1163 | { | |
1164 | int port; | |
1165 | ||
1166 | loops_per_jiffy = 100000000 / HZ; | |
1167 | ||
1168 | #ifdef CONFIG_BLK_DEV_INITRD | |
1169 | if (initrd_start) | |
1170 | ROOT_DEV = Root_RAM0; | |
1171 | else | |
1172 | #endif | |
1173 | #ifdef CONFIG_ROOT_NFS | |
1174 | ROOT_DEV = Root_NFS; | |
1175 | #else | |
1176 | ROOT_DEV = Root_HDA1; | |
1177 | #endif | |
1178 | ||
400d2212 KG |
1179 | if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) || |
1180 | (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)) | |
1da177e4 LT |
1181 | /* 745x is different. We only want to pass along enable. */ |
1182 | _set_L2CR(L2CR_L2E); | |
400d2212 | 1183 | else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR) |
1da177e4 LT |
1184 | /* All modules have 1MB of L2. We also assume that an |
1185 | * L2 divisor of 3 will work. | |
1186 | */ | |
1187 | _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 | |
1188 | | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); | |
1189 | ||
400d2212 | 1190 | if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR) |
1da177e4 LT |
1191 | /* No L3 cache */ |
1192 | _set_L3CR(0); | |
1193 | ||
1194 | #ifdef CONFIG_DUMMY_CONSOLE | |
1195 | conswitchp = &dummy_con; | |
1196 | #endif | |
1197 | ||
1198 | /* Lookup PCI host bridges */ | |
1199 | if (ppc_md.progress) | |
1200 | ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0); | |
1201 | ||
1202 | ppc7d_setup_bridge(); | |
1203 | ppc7d_setup_peripherals(); | |
1204 | ||
1205 | /* Disable ethernet. It might have been setup by the bootrom */ | |
1206 | for (port = 0; port < 3; port++) | |
1207 | mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port), | |
1208 | 0x0000ff00); | |
1209 | ||
1210 | /* Clear queue pointers to ensure they are all initialized, | |
1211 | * otherwise since queues 1-7 are unused, they have random | |
1212 | * pointers which look strange in register dumps. Don't bother | |
1213 | * with queue 0 since it will be initialized later. | |
1214 | */ | |
1215 | for (port = 0; port < 3; port++) { | |
1216 | mv64x60_write(&bh, | |
1217 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port), | |
1218 | 0x00000000); | |
1219 | mv64x60_write(&bh, | |
1220 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port), | |
1221 | 0x00000000); | |
1222 | mv64x60_write(&bh, | |
1223 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port), | |
1224 | 0x00000000); | |
1225 | mv64x60_write(&bh, | |
1226 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port), | |
1227 | 0x00000000); | |
1228 | mv64x60_write(&bh, | |
1229 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port), | |
1230 | 0x00000000); | |
1231 | mv64x60_write(&bh, | |
1232 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port), | |
1233 | 0x00000000); | |
1234 | mv64x60_write(&bh, | |
1235 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port), | |
1236 | 0x00000000); | |
1237 | } | |
1238 | ||
1239 | printk(KERN_INFO "Radstone Technology PPC7D\n"); | |
1240 | if (ppc_md.progress) | |
1241 | ppc_md.progress("ppc7d_setup_arch: exit", 0); | |
a497aa20 CE |
1242 | |
1243 | } | |
1244 | ||
1245 | /* Real Time Clock support. | |
1246 | * PPC7D has a DS1337 accessed by I2C. | |
1247 | */ | |
1248 | static ulong ppc7d_get_rtc_time(void) | |
1249 | { | |
1250 | struct rtc_time tm; | |
1251 | int result; | |
1252 | ||
1253 | spin_lock(&rtc_lock); | |
1254 | result = ds1337_do_command(0, DS1337_GET_DATE, &tm); | |
1255 | spin_unlock(&rtc_lock); | |
1256 | ||
1257 | if (result == 0) | |
1258 | result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); | |
1259 | ||
1260 | return result; | |
1261 | } | |
1262 | ||
1263 | static int ppc7d_set_rtc_time(unsigned long nowtime) | |
1264 | { | |
1265 | struct rtc_time tm; | |
1266 | int result; | |
1267 | ||
1268 | spin_lock(&rtc_lock); | |
1269 | to_tm(nowtime, &tm); | |
1270 | result = ds1337_do_command(0, DS1337_SET_DATE, &tm); | |
1271 | spin_unlock(&rtc_lock); | |
1272 | ||
1273 | return result; | |
1da177e4 LT |
1274 | } |
1275 | ||
1276 | /* This kernel command line parameter can be used to have the target | |
1277 | * wait for a JTAG debugger to attach. Of course, a JTAG debugger | |
1278 | * with hardware breakpoint support can have the target stop at any | |
1279 | * location during init, but this is a convenience feature that makes | |
1280 | * it easier in the common case of loading the code using the ppcboot | |
1281 | * bootloader.. | |
1282 | */ | |
1283 | static unsigned long ppc7d_wait_debugger; | |
1284 | ||
1285 | static int __init ppc7d_waitdbg(char *str) | |
1286 | { | |
1287 | ppc7d_wait_debugger = 1; | |
1288 | return 1; | |
1289 | } | |
1290 | ||
1291 | __setup("waitdbg", ppc7d_waitdbg); | |
1292 | ||
1293 | /* Second phase board init, called after other (architecture common) | |
1294 | * low-level services have been initialized. | |
1295 | */ | |
1296 | static void ppc7d_init2(void) | |
1297 | { | |
1298 | unsigned long flags; | |
1299 | u32 data; | |
1300 | u8 data8; | |
1301 | ||
1302 | pr_debug("%s: enter\n", __FUNCTION__); | |
1303 | ||
1304 | /* Wait for debugger? */ | |
1305 | if (ppc7d_wait_debugger) { | |
1306 | printk("Waiting for debugger...\n"); | |
1307 | ||
1308 | while (readl(&ppc7d_wait_debugger)) ; | |
1309 | } | |
1310 | ||
1311 | /* Hook up i8259 interrupt which is connected to GPP28 */ | |
1312 | request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr, | |
bc59d280 | 1313 | IRQF_DISABLED, "I8259 (GPP28) interrupt", (void *)0); |
1da177e4 LT |
1314 | |
1315 | /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */ | |
1316 | spin_lock_irqsave(&mv64x60_lock, flags); | |
1317 | data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); | |
1318 | data &= ~(0x0000000f << 0); | |
1319 | data |= (0x00000004 << 0); | |
1320 | data &= ~(0x0000000f << 4); | |
1321 | data |= (0x00000004 << 4); | |
1322 | mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); | |
1323 | spin_unlock_irqrestore(&mv64x60_lock, flags); | |
1324 | ||
1325 | /* All LEDs off */ | |
1326 | data8 = inb(PPC7D_CPLD_LEDS); | |
1327 | data8 &= ~0x08; | |
1328 | data8 |= 0x07; | |
1329 | outb(data8, PPC7D_CPLD_LEDS); | |
1330 | ||
a497aa20 CE |
1331 | /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */ |
1332 | ppc_md.set_rtc_time = ppc7d_set_rtc_time; | |
1333 | ppc_md.get_rtc_time = ppc7d_get_rtc_time; | |
1334 | ||
1da177e4 LT |
1335 | pr_debug("%s: exit\n", __FUNCTION__); |
1336 | } | |
1337 | ||
1338 | /* Called from machine_init(), early, before any of the __init functions | |
1339 | * have run. We must init software-configurable pins before other functions | |
1340 | * such as interrupt controllers are initialised. | |
1341 | */ | |
1342 | void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
1343 | unsigned long r6, unsigned long r7) | |
1344 | { | |
1345 | u8 val8; | |
1346 | u8 rev_num; | |
1347 | ||
1348 | /* Map 0xe0000000-0xffffffff early because we need access to SRAM | |
1349 | * and the ISA memory space (for serial port) here. This mapping | |
1350 | * is redone properly in ppc7d_map_io() later. | |
1351 | */ | |
1352 | mtspr(SPRN_DBAT3U, 0xe0003fff); | |
1353 | mtspr(SPRN_DBAT3L, 0xe000002a); | |
1354 | ||
1355 | /* | |
1356 | * Zero SRAM. Note that this generates parity errors on | |
1357 | * internal data path in SRAM if it's first time accessing it | |
1358 | * after reset. | |
1359 | * | |
1360 | * We do this ASAP to avoid parity errors when reading | |
1361 | * uninitialized SRAM. | |
1362 | */ | |
1363 | memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE); | |
1364 | ||
1365 | pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n", | |
1366 | r3, r4, r5, r6, r7); | |
1367 | ||
1368 | parse_bootinfo(find_bootinfo()); | |
1369 | ||
1370 | /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) | |
1371 | * are non-zero, then we should use the board info from the bd_t | |
1372 | * structure and the cmdline pointed to by r6 instead of the | |
1373 | * information from birecs, if any. Otherwise, use the information | |
a8de5ce9 | 1374 | * from birecs as discovered by the preceding call to |
1da177e4 LT |
1375 | * parse_bootinfo(). This rule should work with both PPCBoot, which |
1376 | * uses a bd_t board info structure, and the kernel boot wrapper, | |
1377 | * which uses birecs. | |
1378 | */ | |
1379 | if (r3 && r6) { | |
1380 | bd_t *bp = (bd_t *) __res; | |
1381 | ||
1382 | /* copy board info structure */ | |
1383 | memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t)); | |
1384 | /* copy command line */ | |
1385 | *(char *)(r7 + KERNELBASE) = 0; | |
1386 | strcpy(cmd_line, (char *)(r6 + KERNELBASE)); | |
1387 | ||
1388 | printk(KERN_INFO "Board info data:-\n"); | |
1389 | printk(KERN_INFO " Internal freq: %lu MHz, bus freq: %lu MHz\n", | |
1390 | bp->bi_intfreq, bp->bi_busfreq); | |
1391 | printk(KERN_INFO " Memory: %lx, size %lx\n", bp->bi_memstart, | |
1392 | bp->bi_memsize); | |
1393 | printk(KERN_INFO " Console baudrate: %lu\n", bp->bi_baudrate); | |
1394 | printk(KERN_INFO " Ethernet address: " | |
1395 | "%02x:%02x:%02x:%02x:%02x:%02x\n", | |
1396 | bp->bi_enetaddr[0], bp->bi_enetaddr[1], | |
1397 | bp->bi_enetaddr[2], bp->bi_enetaddr[3], | |
1398 | bp->bi_enetaddr[4], bp->bi_enetaddr[5]); | |
1399 | } | |
1400 | #ifdef CONFIG_BLK_DEV_INITRD | |
1401 | /* take care of initrd if we have one */ | |
1402 | if (r4) { | |
1403 | initrd_start = r4 + KERNELBASE; | |
1404 | initrd_end = r5 + KERNELBASE; | |
1405 | printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end); | |
1406 | } | |
1407 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
1408 | ||
1409 | /* Map in board regs, etc. */ | |
1410 | isa_io_base = 0xe8000000; | |
1411 | isa_mem_base = 0xe8000000; | |
1412 | pci_dram_offset = 0x00000000; | |
1413 | ISA_DMA_THRESHOLD = 0x00ffffff; | |
1414 | DMA_MODE_READ = 0x44; | |
1415 | DMA_MODE_WRITE = 0x48; | |
1416 | ||
1417 | ppc_md.setup_arch = ppc7d_setup_arch; | |
1418 | ppc_md.init = ppc7d_init2; | |
1419 | ppc_md.show_cpuinfo = ppc7d_show_cpuinfo; | |
35d81a4b | 1420 | /* XXX this is broken... */ |
1da177e4 LT |
1421 | ppc_md.irq_canonicalize = ppc7d_irq_canonicalize; |
1422 | ppc_md.init_IRQ = ppc7d_init_irq; | |
1423 | ppc_md.get_irq = ppc7d_get_irq; | |
1424 | ||
1425 | ppc_md.restart = ppc7d_restart; | |
1426 | ppc_md.power_off = ppc7d_power_off; | |
1427 | ppc_md.halt = ppc7d_halt; | |
1428 | ||
1429 | ppc_md.find_end_of_memory = ppc7d_find_end_of_memory; | |
1430 | ppc_md.setup_io_mappings = ppc7d_map_io; | |
1431 | ||
1432 | ppc_md.time_init = NULL; | |
1433 | ppc_md.set_rtc_time = NULL; | |
1434 | ppc_md.get_rtc_time = NULL; | |
1435 | ppc_md.calibrate_decr = ppc7d_calibrate_decr; | |
1436 | ppc_md.nvram_read_val = NULL; | |
1437 | ppc_md.nvram_write_val = NULL; | |
1438 | ||
1439 | ppc_md.heartbeat = ppc7d_heartbeat; | |
1440 | ppc_md.heartbeat_reset = HZ; | |
1441 | ppc_md.heartbeat_count = ppc_md.heartbeat_reset; | |
1442 | ||
1443 | ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus; | |
1444 | ||
1445 | #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \ | |
1446 | defined(CONFIG_I2C_MV64XXX) | |
1447 | platform_notify = ppc7d_platform_notify; | |
1448 | #endif | |
1449 | ||
1450 | #ifdef CONFIG_SERIAL_MPSC | |
1451 | /* On PPC7D, we must configure MPSC support via CPLD control | |
1452 | * registers. | |
1453 | */ | |
1454 | outb(PPC7D_CPLD_RTS_COM4_SCLK | | |
1455 | PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS); | |
1456 | outb(PPC7D_CPLD_COMS_COM3_TCLKEN | | |
1457 | PPC7D_CPLD_COMS_COM3_TXEN | | |
1458 | PPC7D_CPLD_COMS_COM4_TCLKEN | | |
1459 | PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS); | |
1460 | #endif /* CONFIG_SERIAL_MPSC */ | |
1461 | ||
1462 | #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) | |
1463 | ppc7d_early_serial_map(); | |
1464 | #ifdef CONFIG_SERIAL_TEXT_DEBUG | |
1465 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
1466 | ppc_md.progress = mv64x60_mpsc_progress; | |
1467 | #elif defined(CONFIG_SERIAL_8250) | |
1468 | ppc_md.progress = gen550_progress; | |
1469 | #else | |
1470 | #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX | |
1471 | #endif /* CONFIG_SERIAL_8250 */ | |
1472 | #endif /* CONFIG_SERIAL_TEXT_DEBUG */ | |
1473 | #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */ | |
1474 | ||
1475 | /* Enable write access to user flash. This is necessary for | |
1476 | * flash probe. | |
1477 | */ | |
1478 | val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); | |
1479 | writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED & | |
1480 | PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK), | |
1481 | (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); | |
1482 | ||
1483 | /* Determine if this board has IBM ALMA VME devices */ | |
1484 | val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION); | |
1485 | rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5; | |
1486 | if (rev_num <= 1) | |
1487 | ppc7d_has_alma = 1; | |
1488 | ||
1489 | #ifdef DEBUG | |
1490 | console_printk[0] = 8; | |
1491 | #endif | |
1492 | } |