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1da177e4 LT |
1 | /* |
2 | * arch/ppc/platforms/radstone_ppc7d.c | |
3 | * | |
4 | * Board setup routines for the Radstone PPC7D boards. | |
5 | * | |
6 | * Author: James Chapman <jchapman@katalix.com> | |
7 | * | |
8 | * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il | |
9 | * Based on code done by - Mark A. Greer <mgreer@mvista.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | /* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs, | |
18 | * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse, | |
19 | * 4 serial ports, 2 high speed serial ports (MPSCs) and optional | |
20 | * SCSI / VGA. | |
21 | */ | |
22 | ||
23 | #include <linux/config.h> | |
24 | #include <linux/stddef.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/reboot.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/kdev_t.h> | |
31 | #include <linux/major.h> | |
32 | #include <linux/initrd.h> | |
33 | #include <linux/console.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/irq.h> | |
36 | #include <linux/ide.h> | |
37 | #include <linux/seq_file.h> | |
38 | #include <linux/root_dev.h> | |
39 | #include <linux/serial.h> | |
40 | #include <linux/tty.h> /* for linux/serial_core.h */ | |
41 | #include <linux/serial_core.h> | |
42 | #include <linux/mv643xx.h> | |
43 | #include <linux/netdevice.h> | |
44 | ||
45 | #include <asm/system.h> | |
46 | #include <asm/pgtable.h> | |
47 | #include <asm/page.h> | |
48 | #include <asm/time.h> | |
49 | #include <asm/dma.h> | |
50 | #include <asm/io.h> | |
51 | #include <asm/machdep.h> | |
52 | #include <asm/prom.h> | |
53 | #include <asm/smp.h> | |
54 | #include <asm/vga.h> | |
55 | #include <asm/open_pic.h> | |
56 | #include <asm/i8259.h> | |
57 | #include <asm/todc.h> | |
58 | #include <asm/bootinfo.h> | |
59 | #include <asm/mpc10x.h> | |
60 | #include <asm/pci-bridge.h> | |
61 | #include <asm/mv64x60.h> | |
62 | #include <asm/i8259.h> | |
63 | ||
64 | #include "radstone_ppc7d.h" | |
65 | ||
66 | #undef DEBUG | |
67 | ||
68 | #define PPC7D_RST_PIN 17 /* GPP17 */ | |
69 | ||
70 | extern u32 mv64360_irq_base; | |
a497aa20 | 71 | extern spinlock_t rtc_lock; |
1da177e4 LT |
72 | |
73 | static struct mv64x60_handle bh; | |
74 | static int ppc7d_has_alma; | |
75 | ||
76 | extern void gen550_progress(char *, unsigned short); | |
77 | extern void gen550_init(int, struct uart_port *); | |
78 | ||
a497aa20 CE |
79 | /* FIXME - move to h file */ |
80 | extern int ds1337_do_command(int id, int cmd, void *arg); | |
81 | #define DS1337_GET_DATE 0 | |
82 | #define DS1337_SET_DATE 1 | |
83 | ||
1da177e4 LT |
84 | /* residual data */ |
85 | unsigned char __res[sizeof(bd_t)]; | |
86 | ||
87 | /***************************************************************************** | |
88 | * Serial port code | |
89 | *****************************************************************************/ | |
90 | ||
91 | #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) | |
92 | static void __init ppc7d_early_serial_map(void) | |
93 | { | |
94 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
95 | mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); | |
96 | #elif defined(CONFIG_SERIAL_8250) | |
97 | struct uart_port serial_req; | |
98 | ||
99 | /* Setup serial port access */ | |
100 | memset(&serial_req, 0, sizeof(serial_req)); | |
101 | serial_req.uartclk = UART_CLK; | |
102 | serial_req.irq = 4; | |
103 | serial_req.flags = STD_COM_FLAGS; | |
104 | serial_req.iotype = SERIAL_IO_MEM; | |
105 | serial_req.membase = (u_char *) PPC7D_SERIAL_0; | |
106 | ||
107 | gen550_init(0, &serial_req); | |
108 | if (early_serial_setup(&serial_req) != 0) | |
109 | printk(KERN_ERR "Early serial init of port 0 failed\n"); | |
110 | ||
111 | /* Assume early_serial_setup() doesn't modify serial_req */ | |
112 | serial_req.line = 1; | |
113 | serial_req.irq = 3; | |
114 | serial_req.membase = (u_char *) PPC7D_SERIAL_1; | |
115 | ||
116 | gen550_init(1, &serial_req); | |
117 | if (early_serial_setup(&serial_req) != 0) | |
118 | printk(KERN_ERR "Early serial init of port 1 failed\n"); | |
119 | #else | |
120 | #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX | |
121 | #endif | |
122 | } | |
123 | #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */ | |
124 | ||
125 | /***************************************************************************** | |
126 | * Low-level board support code | |
127 | *****************************************************************************/ | |
128 | ||
129 | static unsigned long __init ppc7d_find_end_of_memory(void) | |
130 | { | |
131 | bd_t *bp = (bd_t *) __res; | |
132 | ||
133 | if (bp->bi_memsize) | |
134 | return bp->bi_memsize; | |
135 | ||
136 | return (256 * 1024 * 1024); | |
137 | } | |
138 | ||
139 | static void __init ppc7d_map_io(void) | |
140 | { | |
141 | /* remove temporary mapping */ | |
142 | mtspr(SPRN_DBAT3U, 0x00000000); | |
143 | mtspr(SPRN_DBAT3L, 0x00000000); | |
144 | ||
145 | io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO); | |
146 | io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); | |
147 | } | |
148 | ||
149 | static void ppc7d_restart(char *cmd) | |
150 | { | |
151 | u32 data; | |
152 | ||
153 | /* Disable GPP17 interrupt */ | |
154 | data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
155 | data &= ~(1 << PPC7D_RST_PIN); | |
156 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data); | |
157 | ||
158 | /* Configure MPP17 as GPP */ | |
159 | data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); | |
160 | data &= ~(0x0000000f << 4); | |
161 | mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); | |
162 | ||
163 | /* Enable pin GPP17 for output */ | |
164 | data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL); | |
165 | data |= (1 << PPC7D_RST_PIN); | |
166 | mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data); | |
167 | ||
168 | /* Toggle GPP9 pin to reset the board */ | |
169 | mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN); | |
170 | mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN); | |
171 | ||
172 | for (;;) ; /* Spin until reset happens */ | |
173 | /* NOTREACHED */ | |
174 | } | |
175 | ||
176 | static void ppc7d_power_off(void) | |
177 | { | |
178 | u32 data; | |
179 | ||
180 | local_irq_disable(); | |
181 | ||
182 | /* Ensure that internal MV643XX watchdog is disabled. | |
183 | * The Disco watchdog uses MPP17 on this hardware. | |
184 | */ | |
185 | data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); | |
186 | data &= ~(0x0000000f << 4); | |
187 | mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); | |
188 | ||
189 | data = mv64x60_read(&bh, MV64x60_WDT_WDC); | |
190 | if (data & 0x80000000) { | |
191 | mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24); | |
192 | mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24); | |
193 | } | |
194 | ||
195 | for (;;) ; /* No way to shut power off with software */ | |
196 | /* NOTREACHED */ | |
197 | } | |
198 | ||
199 | static void ppc7d_halt(void) | |
200 | { | |
201 | ppc7d_power_off(); | |
202 | /* NOTREACHED */ | |
203 | } | |
204 | ||
205 | static unsigned long ppc7d_led_no_pulse; | |
206 | ||
207 | static int __init ppc7d_led_pulse_disable(char *str) | |
208 | { | |
209 | ppc7d_led_no_pulse = 1; | |
210 | return 1; | |
211 | } | |
212 | ||
213 | /* This kernel option disables the heartbeat pulsing of a board LED */ | |
214 | __setup("ledoff", ppc7d_led_pulse_disable); | |
215 | ||
216 | static void ppc7d_heartbeat(void) | |
217 | { | |
218 | u32 data32; | |
219 | u8 data8; | |
220 | static int max706_wdog = 0; | |
221 | ||
222 | /* Unfortunately we can't access the LED control registers | |
223 | * during early init because they're on the CPLD which is the | |
224 | * other side of a PCI bridge which goes unreachable during | |
225 | * PCI scan. So write the LEDs only if the MV64360 watchdog is | |
226 | * enabled (i.e. userspace apps are running so kernel is up).. | |
227 | */ | |
228 | data32 = mv64x60_read(&bh, MV64x60_WDT_WDC); | |
229 | if (data32 & 0x80000000) { | |
230 | /* Enable MAX706 watchdog if not done already */ | |
231 | if (!max706_wdog) { | |
232 | outb(3, PPC7D_CPLD_RESET); | |
233 | max706_wdog = 1; | |
234 | } | |
235 | ||
236 | /* Hit the MAX706 watchdog */ | |
237 | outb(0, PPC7D_CPLD_WATCHDOG_TRIG); | |
238 | ||
239 | /* Pulse LED DS219 if not disabled */ | |
240 | if (!ppc7d_led_no_pulse) { | |
241 | static int led_on = 0; | |
242 | ||
243 | data8 = inb(PPC7D_CPLD_LEDS); | |
244 | if (led_on) | |
245 | data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK; | |
246 | else | |
247 | data8 |= PPC7D_CPLD_LEDS_DS219_MASK; | |
248 | ||
249 | outb(data8, PPC7D_CPLD_LEDS); | |
250 | led_on = !led_on; | |
251 | } | |
252 | } | |
253 | ppc_md.heartbeat_count = ppc_md.heartbeat_reset; | |
254 | } | |
255 | ||
256 | static int ppc7d_show_cpuinfo(struct seq_file *m) | |
257 | { | |
258 | u8 val; | |
259 | u8 val1, val2; | |
260 | static int flash_sizes[4] = { 64, 32, 0, 16 }; | |
261 | static int flash_banks[4] = { 4, 3, 2, 1 }; | |
630710e3 CE |
262 | static int sdram_bank_sizes[4] = { 128, 256, 512, 1 }; |
263 | int sdram_num_banks = 2; | |
1da177e4 LT |
264 | static char *pci_modes[] = { "PCI33", "PCI66", |
265 | "Unknown", "Unknown", | |
266 | "PCIX33", "PCIX66", | |
267 | "PCIX100", "PCIX133" | |
268 | }; | |
269 | ||
270 | seq_printf(m, "vendor\t\t: Radstone Technology\n"); | |
271 | seq_printf(m, "machine\t\t: PPC7D\n"); | |
272 | ||
273 | val = inb(PPC7D_CPLD_BOARD_REVISION); | |
274 | val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5; | |
275 | val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK); | |
276 | seq_printf(m, "revision\t: %hd%c%c\n", | |
277 | val1, | |
278 | (val2 <= 0x18) ? 'A' + val2 : 'Y', | |
279 | (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' '); | |
280 | ||
281 | val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE); | |
282 | val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK; | |
283 | val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK | | |
284 | PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK); | |
285 | seq_printf(m, "bus speed\t: %dMHz\n", | |
286 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 : | |
287 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 : | |
288 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0); | |
289 | ||
630710e3 CE |
290 | val = inb(PPC7D_CPLD_MEM_CONFIG); |
291 | if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--; | |
292 | ||
1da177e4 | 293 | val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND); |
630710e3 CE |
294 | val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6; |
295 | seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c", | |
296 | sdram_num_banks, | |
297 | sdram_bank_sizes[val1], | |
298 | (sdram_bank_sizes[val1] < 128) ? 'G' : 'M', | |
299 | sdram_num_banks * sdram_bank_sizes[val1], | |
300 | (sdram_bank_sizes[val1] < 128) ? 'G' : 'M'); | |
1da177e4 LT |
301 | if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) { |
302 | seq_printf(m, " [ECC %sabled]", | |
303 | (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" : | |
304 | "dis"); | |
305 | } | |
306 | seq_printf(m, "\n"); | |
307 | ||
308 | val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK); | |
309 | val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2; | |
310 | seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n", | |
311 | flash_banks[val2], flash_sizes[val1], | |
312 | flash_banks[val2] * flash_sizes[val1]); | |
313 | ||
314 | val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL); | |
315 | val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); | |
316 | seq_printf(m, " write links\t: %s%s%s%s\n", | |
317 | (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "", | |
318 | (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "", | |
319 | (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "", | |
320 | (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK | | |
321 | PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK | | |
322 | PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) == | |
323 | 0 ? "NONE" : ""); | |
324 | seq_printf(m, " write sector h/w enables: %s%s%s%s%s\n", | |
325 | (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " : | |
326 | "", | |
327 | (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "", | |
328 | (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "", | |
329 | (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " : | |
330 | "", | |
331 | (((val & | |
332 | (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK | | |
333 | PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK | | |
334 | PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0) | |
335 | && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) == | |
336 | 0)) ? "NONE" : ""); | |
337 | val1 = | |
338 | inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) & | |
339 | (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK | | |
340 | PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK); | |
341 | seq_printf(m, " software sector enables: %s%s%s\n", | |
342 | (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT " | |
343 | : "", | |
344 | (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "", | |
345 | (val1 == 0) ? "NONE " : ""); | |
346 | ||
347 | seq_printf(m, "Boot options\t: %s%s%s%s\n", | |
348 | (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ? | |
349 | "ALTERNATE " : "", | |
350 | (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " : | |
351 | "", | |
352 | (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY " | |
353 | : "", | |
354 | ((val & | |
355 | (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK | | |
356 | PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK | | |
357 | PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) == | |
358 | 0) ? "NONE" : ""); | |
359 | ||
360 | val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1); | |
361 | seq_printf(m, "Fitted modules\t: %s%s%s%s\n", | |
362 | (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ", | |
363 | (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ", | |
364 | (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "", | |
365 | ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK | | |
366 | PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK | | |
367 | PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) == | |
368 | (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK | | |
369 | PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : ""); | |
370 | ||
371 | if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) { | |
372 | static const char *ids[] = { | |
373 | "unknown", | |
374 | "1553 (Dual Channel)", | |
375 | "1553 (Single Channel)", | |
376 | "8-bit SCSI + VGA", | |
377 | "16-bit SCSI + VGA", | |
378 | "1553 (Single Channel with sideband)", | |
379 | "1553 (Dual Channel with sideband)", | |
380 | NULL | |
381 | }; | |
382 | u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03); | |
383 | seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id, | |
384 | id < 7 ? ids[id] : "unknown"); | |
385 | } | |
386 | ||
387 | val = inb(PPC7D_CPLD_PCI_CONFIG); | |
388 | val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4; | |
389 | val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK); | |
390 | seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n", | |
391 | pci_modes[val1], pci_modes[val2]); | |
392 | ||
393 | val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2); | |
394 | seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n", | |
395 | (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v", | |
396 | (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v"); | |
397 | seq_printf(m, "PMC power source: %s\n", | |
398 | (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" : | |
399 | "internal"); | |
400 | ||
401 | val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4); | |
402 | val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2); | |
403 | seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n", | |
404 | (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "", | |
405 | (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "", | |
406 | (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "", | |
407 | (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "", | |
408 | (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "", | |
409 | (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "", | |
410 | (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " : | |
411 | ""); | |
412 | ||
413 | val = inb(PPC7D_CPLD_ID_LINK); | |
414 | val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK | | |
415 | PPC7D_CPLD_ID_LINK_E7_MASK | | |
416 | PPC7D_CPLD_ID_LINK_E12_MASK | | |
417 | PPC7D_CPLD_ID_LINK_E13_MASK); | |
418 | ||
419 | val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) & | |
420 | (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK | | |
421 | PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK | | |
422 | PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK); | |
423 | ||
424 | seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n", | |
425 | (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "", | |
426 | (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "", | |
427 | (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "", | |
428 | (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "", | |
429 | (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "", | |
430 | (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "", | |
431 | (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "", | |
432 | ((val == 0) && (val1 == 0)) ? "NONE" : ""); | |
433 | ||
434 | val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK); | |
435 | seq_printf(m, "Front panel reset switch: %sabled\n", | |
436 | (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en"); | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | static void __init ppc7d_calibrate_decr(void) | |
442 | { | |
443 | ulong freq; | |
444 | ||
445 | freq = 100000000 / 4; | |
446 | ||
447 | pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n", | |
448 | freq / 1000000, freq % 1000000); | |
449 | ||
450 | tb_ticks_per_jiffy = freq / HZ; | |
451 | tb_to_us = mulhwu_scale_factor(freq, 1000000); | |
452 | } | |
453 | ||
454 | /***************************************************************************** | |
455 | * Interrupt stuff | |
456 | *****************************************************************************/ | |
457 | ||
458 | static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id, struct pt_regs *regs) | |
459 | { | |
460 | u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); | |
461 | if (temp & (1 << 28)) { | |
462 | i8259_irq(regs); | |
463 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28))); | |
464 | return IRQ_HANDLED; | |
465 | } | |
466 | ||
467 | return IRQ_NONE; | |
468 | } | |
469 | ||
470 | /* | |
471 | * Each interrupt cause is assigned an IRQ number. | |
472 | * Southbridge has 16*2 (two 8259's) interrupts. | |
473 | * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32). | |
474 | * If multiple interrupts are pending, get_irq() returns the | |
475 | * lowest pending irq number first. | |
476 | * | |
477 | * | |
478 | * IRQ # Source Trig Active | |
479 | * ============================================================= | |
480 | * | |
481 | * Southbridge | |
482 | * ----------- | |
483 | * IRQ # Source Trig | |
484 | * ============================================================= | |
485 | * 0 ISA High Resolution Counter Edge | |
486 | * 1 Keyboard Edge | |
487 | * 2 Cascade From (IRQ 8-15) Edge | |
488 | * 3 Com 2 (Uart 2) Edge | |
489 | * 4 Com 1 (Uart 1) Edge | |
490 | * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level | |
491 | * 6 GPIO Level | |
492 | * 7 LPT Edge | |
493 | * 8 RTC Alarm Edge | |
494 | * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level | |
495 | * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level | |
496 | * 11 USB2 Level | |
497 | * 12 Mouse Edge | |
498 | * 13 Reserved internally by Ali M1535+ | |
499 | * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level | |
500 | * 15 COM 5/6 Level | |
501 | * | |
502 | * 16..112 Discovery-II... | |
503 | * | |
504 | * MPP28 Southbridge Edge High | |
505 | * | |
506 | * | |
507 | * Interrupts are cascaded through to the Discovery-II. | |
508 | * | |
509 | * PCI --- | |
510 | * \ | |
511 | * CPLD --> ALI1535 -------> DISCOVERY-II | |
512 | * INTF MPP28 | |
513 | */ | |
514 | static void __init ppc7d_init_irq(void) | |
515 | { | |
516 | int irq; | |
517 | ||
518 | pr_debug("%s\n", __FUNCTION__); | |
519 | i8259_init(0); | |
520 | mv64360_init_irq(); | |
521 | ||
522 | /* IRQ 0..15 are handled by the cascaded 8259's of the Ali1535 */ | |
523 | for (irq = 0; irq < 16; irq++) { | |
524 | irq_desc[irq].handler = &i8259_pic; | |
525 | } | |
526 | /* IRQs 5,6,9,10,11,14,15 are level sensitive */ | |
527 | irq_desc[5].status |= IRQ_LEVEL; | |
528 | irq_desc[6].status |= IRQ_LEVEL; | |
529 | irq_desc[9].status |= IRQ_LEVEL; | |
530 | irq_desc[10].status |= IRQ_LEVEL; | |
531 | irq_desc[11].status |= IRQ_LEVEL; | |
532 | irq_desc[14].status |= IRQ_LEVEL; | |
533 | irq_desc[15].status |= IRQ_LEVEL; | |
534 | ||
535 | /* GPP28 is edge triggered */ | |
536 | irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL; | |
537 | } | |
538 | ||
539 | static u32 ppc7d_irq_canonicalize(u32 irq) | |
540 | { | |
541 | if ((irq >= 16) && (irq < (16 + 96))) | |
542 | irq -= 16; | |
543 | ||
544 | return irq; | |
545 | } | |
546 | ||
547 | static int ppc7d_get_irq(struct pt_regs *regs) | |
548 | { | |
549 | int irq; | |
550 | ||
551 | irq = mv64360_get_irq(regs); | |
552 | if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28)) | |
553 | irq = i8259_irq(regs); | |
554 | return irq; | |
555 | } | |
556 | ||
557 | /* | |
558 | * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level | |
559 | * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level | |
560 | * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level | |
561 | * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level | |
562 | */ | |
563 | static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel, | |
564 | unsigned char pin) | |
565 | { | |
566 | static const char pci_irq_table[][4] = | |
567 | /* | |
568 | * PCI IDSEL/INTPIN->INTLINE | |
569 | * A B C D | |
570 | */ | |
571 | { | |
572 | {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */ | |
573 | {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */ | |
574 | {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */ | |
575 | {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */ | |
576 | }; | |
577 | const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4; | |
578 | ||
579 | pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__, | |
580 | dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin); | |
581 | ||
582 | return PCI_IRQ_TABLE_LOOKUP; | |
583 | } | |
584 | ||
585 | void __init ppc7d_intr_setup(void) | |
586 | { | |
587 | u32 data; | |
588 | ||
589 | /* | |
590 | * Define GPP 28 interrupt polarity as active high | |
591 | * input signal and level triggered | |
592 | */ | |
593 | data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL); | |
594 | data &= ~(1 << 28); | |
595 | mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data); | |
596 | data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL); | |
597 | data &= ~(1 << 28); | |
598 | mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data); | |
599 | ||
600 | /* Config GPP intr ctlr to respond to level trigger */ | |
601 | data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL); | |
602 | data |= (1 << 10); | |
603 | mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data); | |
604 | ||
605 | /* XXXX Erranum FEr PCI-#8 */ | |
606 | data = mv64x60_read(&bh, MV64x60_PCI0_CMD); | |
607 | data &= ~((1 << 5) | (1 << 9)); | |
608 | mv64x60_write(&bh, MV64x60_PCI0_CMD, data); | |
609 | data = mv64x60_read(&bh, MV64x60_PCI1_CMD); | |
610 | data &= ~((1 << 5) | (1 << 9)); | |
611 | mv64x60_write(&bh, MV64x60_PCI1_CMD, data); | |
612 | ||
613 | /* | |
614 | * Dismiss and then enable interrupt on GPP interrupt cause | |
615 | * for CPU #0 | |
616 | */ | |
617 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28)); | |
618 | data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
619 | data |= (1 << 28); | |
620 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data); | |
621 | ||
622 | /* | |
623 | * Dismiss and then enable interrupt on CPU #0 high cause reg | |
624 | * BIT27 summarizes GPP interrupts 23-31 | |
625 | */ | |
626 | mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27)); | |
627 | data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI); | |
628 | data |= (1 << 27); | |
629 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data); | |
630 | } | |
631 | ||
632 | /***************************************************************************** | |
633 | * Platform device data fixup routines. | |
634 | *****************************************************************************/ | |
635 | ||
636 | #if defined(CONFIG_SERIAL_MPSC) | |
637 | static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev) | |
638 | { | |
639 | struct mpsc_pdata *pdata; | |
640 | ||
641 | pdata = (struct mpsc_pdata *)pdev->dev.platform_data; | |
642 | ||
643 | pdata->max_idle = 40; | |
644 | pdata->default_baud = PPC7D_DEFAULT_BAUD; | |
645 | pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC; | |
646 | pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ; | |
647 | ||
648 | return; | |
649 | } | |
650 | #endif | |
651 | ||
652 | #if defined(CONFIG_MV643XX_ETH) | |
653 | static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev) | |
654 | { | |
655 | struct mv643xx_eth_platform_data *eth_pd; | |
656 | static u16 phy_addr[] = { | |
657 | PPC7D_ETH0_PHY_ADDR, | |
658 | PPC7D_ETH1_PHY_ADDR, | |
659 | PPC7D_ETH2_PHY_ADDR, | |
660 | }; | |
661 | int i; | |
662 | ||
663 | eth_pd = pdev->dev.platform_data; | |
664 | eth_pd->force_phy_addr = 1; | |
665 | eth_pd->phy_addr = phy_addr[pdev->id]; | |
666 | eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE; | |
667 | eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE; | |
668 | ||
669 | /* Adjust IRQ by mv64360_irq_base */ | |
670 | for (i = 0; i < pdev->num_resources; i++) { | |
671 | struct resource *r = &pdev->resource[i]; | |
672 | ||
673 | if (r->flags & IORESOURCE_IRQ) { | |
674 | r->start += mv64360_irq_base; | |
675 | r->end += mv64360_irq_base; | |
676 | pr_debug("%s, uses IRQ %d\n", pdev->name, | |
677 | (int)r->start); | |
678 | } | |
679 | } | |
680 | ||
681 | } | |
682 | #endif | |
683 | ||
684 | #if defined(CONFIG_I2C_MV64XXX) | |
685 | static void __init | |
686 | ppc7d_fixup_i2c_pdata(struct platform_device *pdev) | |
687 | { | |
688 | struct mv64xxx_i2c_pdata *pdata; | |
689 | int i; | |
690 | ||
691 | pdata = pdev->dev.platform_data; | |
692 | if (pdata == NULL) { | |
693 | pdata = kmalloc(sizeof(*pdata), GFP_KERNEL); | |
694 | if (pdata == NULL) | |
695 | return; | |
696 | ||
697 | memset(pdata, 0, sizeof(*pdata)); | |
698 | pdev->dev.platform_data = pdata; | |
699 | } | |
700 | ||
701 | /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */ | |
702 | pdata->freq_m = 8; | |
703 | pdata->freq_n = 3; | |
704 | pdata->timeout = 500; | |
705 | pdata->retries = 3; | |
706 | ||
707 | /* Adjust IRQ by mv64360_irq_base */ | |
708 | for (i = 0; i < pdev->num_resources; i++) { | |
709 | struct resource *r = &pdev->resource[i]; | |
710 | ||
711 | if (r->flags & IORESOURCE_IRQ) { | |
712 | r->start += mv64360_irq_base; | |
713 | r->end += mv64360_irq_base; | |
714 | pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start); | |
715 | } | |
716 | } | |
717 | } | |
718 | #endif | |
719 | ||
720 | static int __init ppc7d_platform_notify(struct device *dev) | |
721 | { | |
722 | static struct { | |
723 | char *bus_id; | |
724 | void ((*rtn) (struct platform_device * pdev)); | |
725 | } dev_map[] = { | |
726 | #if defined(CONFIG_SERIAL_MPSC) | |
727 | { MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata }, | |
728 | { MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata }, | |
729 | #endif | |
730 | #if defined(CONFIG_MV643XX_ETH) | |
731 | { MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata }, | |
732 | { MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata }, | |
733 | { MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata }, | |
734 | #endif | |
735 | #if defined(CONFIG_I2C_MV64XXX) | |
736 | { MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata }, | |
737 | #endif | |
738 | }; | |
739 | struct platform_device *pdev; | |
740 | int i; | |
741 | ||
742 | if (dev && dev->bus_id) | |
743 | for (i = 0; i < ARRAY_SIZE(dev_map); i++) | |
744 | if (!strncmp(dev->bus_id, dev_map[i].bus_id, | |
745 | BUS_ID_SIZE)) { | |
746 | ||
747 | pdev = container_of(dev, | |
748 | struct platform_device, | |
749 | dev); | |
750 | dev_map[i].rtn(pdev); | |
751 | } | |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
756 | /***************************************************************************** | |
757 | * PCI device fixups. | |
758 | * These aren't really fixups per se. They are used to init devices as they | |
759 | * are found during PCI scan. | |
760 | * | |
761 | * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI | |
762 | * scan in order to find other devices on its secondary side. | |
763 | *****************************************************************************/ | |
764 | ||
765 | static void __init ppc7d_fixup_hb8(struct pci_dev *dev) | |
766 | { | |
767 | u16 val16; | |
768 | ||
769 | if (dev->bus->number == 0) { | |
770 | pr_debug("PCI: HB8 init\n"); | |
771 | ||
772 | pci_write_config_byte(dev, 0x1c, | |
773 | ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000) | |
774 | >> 8) | 0x01); | |
775 | pci_write_config_byte(dev, 0x1d, | |
776 | (((PPC7D_PCI0_IO_START_PCI_ADDR + | |
777 | PPC7D_PCI0_IO_SIZE - | |
778 | 1) & 0xf000) >> 8) | 0x01); | |
779 | pci_write_config_word(dev, 0x30, | |
780 | PPC7D_PCI0_IO_START_PCI_ADDR >> 16); | |
781 | pci_write_config_word(dev, 0x32, | |
782 | ((PPC7D_PCI0_IO_START_PCI_ADDR + | |
783 | PPC7D_PCI0_IO_SIZE - | |
784 | 1) >> 16) & 0xffff); | |
785 | ||
786 | pci_write_config_word(dev, 0x20, | |
787 | PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16); | |
788 | pci_write_config_word(dev, 0x22, | |
789 | ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + | |
790 | PPC7D_PCI0_MEM0_SIZE - | |
791 | 1) >> 16) & 0xffff); | |
792 | pci_write_config_word(dev, 0x24, 0); | |
793 | pci_write_config_word(dev, 0x26, 0); | |
794 | pci_write_config_dword(dev, 0x28, 0); | |
795 | pci_write_config_dword(dev, 0x2c, 0); | |
796 | ||
797 | pci_read_config_word(dev, 0x3e, &val16); | |
798 | val16 |= ((1 << 5) | (1 << 1)); /* signal master aborts and | |
799 | * SERR to primary | |
800 | */ | |
801 | val16 &= ~(1 << 2); /* ISA disable, so all ISA | |
802 | * ports forwarded to secondary | |
803 | */ | |
804 | pci_write_config_word(dev, 0x3e, val16); | |
805 | } | |
806 | } | |
807 | ||
808 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8); | |
809 | ||
810 | /* This should perhaps be a separate driver as we're actually initializing | |
811 | * the chip for this board here. It's hardly a fixup... | |
812 | */ | |
813 | static void __init ppc7d_fixup_ali1535(struct pci_dev *dev) | |
814 | { | |
815 | pr_debug("PCI: ALI1535 init\n"); | |
816 | ||
817 | if (dev->bus->number == 1) { | |
818 | /* Configure the ISA Port Settings */ | |
819 | pci_write_config_byte(dev, 0x43, 0x00); | |
820 | ||
821 | /* Disable PCI Interrupt polling mode */ | |
822 | pci_write_config_byte(dev, 0x45, 0x00); | |
823 | ||
824 | /* Multifunction pin select INTFJ -> INTF */ | |
825 | pci_write_config_byte(dev, 0x78, 0x00); | |
826 | ||
827 | /* Set PCI INT -> IRQ Routing control in for external | |
828 | * pins south bridge. | |
829 | */ | |
830 | pci_write_config_byte(dev, 0x48, 0x31); /* [7-4] INT B -> IRQ10 | |
831 | * [3-0] INT A -> IRQ9 | |
832 | */ | |
833 | pci_write_config_byte(dev, 0x49, 0x5D); /* [7-4] INT D -> IRQ5 | |
834 | * [3-0] INT C -> IRQ14 | |
835 | */ | |
836 | ||
837 | /* PPC7D setup */ | |
838 | /* NEC USB device on IRQ 11 (INTE) - INTF disabled */ | |
839 | pci_write_config_byte(dev, 0x4A, 0x09); | |
840 | ||
841 | /* GPIO on IRQ 6 */ | |
842 | pci_write_config_byte(dev, 0x76, 0x07); | |
843 | ||
844 | /* SIRQ I (COMS 5/6) use IRQ line 15. | |
845 | * Positive (not subtractive) address decode. | |
846 | */ | |
847 | pci_write_config_byte(dev, 0x44, 0x0f); | |
848 | ||
849 | /* SIRQ II disabled */ | |
850 | pci_write_config_byte(dev, 0x75, 0x0); | |
851 | ||
852 | /* On board USB and RTC disabled */ | |
853 | pci_write_config_word(dev, 0x52, (1 << 14)); | |
854 | pci_write_config_byte(dev, 0x74, 0x00); | |
855 | ||
856 | /* On board IDE disabled */ | |
857 | pci_write_config_byte(dev, 0x58, 0x00); | |
858 | ||
859 | /* Decode 32-bit addresses */ | |
860 | pci_write_config_byte(dev, 0x5b, 0); | |
861 | ||
862 | /* Disable docking IO */ | |
863 | pci_write_config_word(dev, 0x5c, 0x0000); | |
864 | ||
865 | /* Disable modem, enable sound */ | |
866 | pci_write_config_byte(dev, 0x77, (1 << 6)); | |
867 | ||
868 | /* Disable hot-docking mode */ | |
869 | pci_write_config_byte(dev, 0x7d, 0x00); | |
870 | } | |
871 | } | |
872 | ||
873 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535); | |
874 | ||
875 | static int ppc7d_pci_exclude_device(u8 bus, u8 devfn) | |
876 | { | |
877 | /* Early versions of this board were fitted with IBM ALMA | |
878 | * PCI-VME bridge chips. The PCI config space of these devices | |
879 | * was not set up correctly and causes PCI scan problems. | |
880 | */ | |
881 | if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma) | |
882 | return PCIBIOS_DEVICE_NOT_FOUND; | |
883 | ||
884 | return mv64x60_pci_exclude_device(bus, devfn); | |
885 | } | |
886 | ||
887 | /* This hook is called when each PCI bus is probed. | |
888 | */ | |
889 | static void ppc7d_pci_fixup_bus(struct pci_bus *bus) | |
890 | { | |
891 | pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n", | |
892 | bus->number, | |
893 | bus->resource[0] ? bus->resource[0]->start : 0, | |
894 | bus->resource[0] ? bus->resource[0]->end : 0, | |
895 | bus->resource[1] ? bus->resource[1]->start : 0, | |
896 | bus->resource[1] ? bus->resource[1]->end : 0, | |
897 | bus->resource[2] ? bus->resource[2]->start : 0, | |
898 | bus->resource[2] ? bus->resource[2]->end : 0, | |
899 | bus->resource[3] ? bus->resource[3]->start : 0, | |
900 | bus->resource[3] ? bus->resource[3]->end : 0); | |
901 | ||
902 | if ((bus->number == 1) && (bus->resource[2] != NULL)) { | |
903 | /* Hide PCI window 2 of Bus 1 which is used only to | |
904 | * map legacy ISA memory space. | |
905 | */ | |
906 | bus->resource[2]->start = 0; | |
907 | bus->resource[2]->end = 0; | |
908 | bus->resource[2]->flags = 0; | |
909 | } | |
910 | } | |
911 | ||
912 | /***************************************************************************** | |
913 | * Board device setup code | |
914 | *****************************************************************************/ | |
915 | ||
916 | void __init ppc7d_setup_peripherals(void) | |
917 | { | |
918 | u32 val32; | |
919 | ||
920 | /* Set up windows for boot CS */ | |
921 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, | |
922 | PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE, | |
923 | 0); | |
924 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); | |
925 | ||
926 | /* Boot firmware configures the following DevCS addresses. | |
927 | * DevCS0 - board control/status | |
928 | * DevCS1 - test registers | |
929 | * DevCS2 - AFIX port/address registers (for identifying) | |
930 | * DevCS3 - FLASH | |
931 | * | |
932 | * We don't use DevCS0, DevCS1. | |
933 | */ | |
934 | val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE); | |
935 | val32 |= ((1 << 4) | (1 << 5)); | |
936 | mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32); | |
937 | mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0); | |
938 | mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0); | |
939 | mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0); | |
940 | mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0); | |
941 | ||
942 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, | |
943 | PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0); | |
944 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); | |
945 | ||
946 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, | |
947 | PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0); | |
948 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); | |
949 | ||
950 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, | |
951 | PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, | |
952 | 0); | |
953 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); | |
954 | ||
955 | /* Set up Enet->SRAM window */ | |
956 | mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, | |
957 | PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, | |
958 | 0x2); | |
959 | bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); | |
960 | ||
961 | /* Give enet r/w access to memory region */ | |
962 | val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0); | |
963 | val32 |= (0x3 << (4 << 1)); | |
964 | mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32); | |
965 | val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1); | |
966 | val32 |= (0x3 << (4 << 1)); | |
967 | mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32); | |
968 | val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2); | |
969 | val32 |= (0x3 << (4 << 1)); | |
970 | mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32); | |
971 | ||
972 | val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL); | |
973 | val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)); | |
974 | mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32); | |
975 | ||
976 | /* Enumerate pci bus. | |
977 | * | |
978 | * We scan PCI#0 first (the bus with the HB8 and other | |
979 | * on-board peripherals). We must configure the 64360 before | |
980 | * each scan, according to the bus number assignments. Busses | |
981 | * are assigned incrementally, starting at 0. PCI#0 is | |
982 | * usually assigned bus#0, the secondary side of the HB8 gets | |
983 | * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if | |
984 | * any PMC card has a PCI bridge, these bus assignments will | |
985 | * change. | |
986 | */ | |
987 | ||
988 | /* Turn off PCI retries */ | |
989 | val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
990 | val32 |= (1 << 17); | |
991 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32); | |
992 | ||
993 | /* Scan PCI#0 */ | |
994 | mv64x60_set_bus(&bh, 0, 0); | |
995 | bh.hose_a->first_busno = 0; | |
996 | bh.hose_a->last_busno = 0xff; | |
997 | bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); | |
998 | printk(KERN_INFO "PCI#0: first=%d last=%d\n", | |
999 | bh.hose_a->first_busno, bh.hose_a->last_busno); | |
1000 | ||
1001 | /* Scan PCI#1 */ | |
1002 | bh.hose_b->first_busno = bh.hose_a->last_busno + 1; | |
1003 | mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); | |
1004 | bh.hose_b->last_busno = 0xff; | |
1005 | bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, | |
1006 | bh.hose_b->first_busno); | |
1007 | printk(KERN_INFO "PCI#1: first=%d last=%d\n", | |
1008 | bh.hose_b->first_busno, bh.hose_b->last_busno); | |
1009 | ||
1010 | /* Turn on PCI retries */ | |
1011 | val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
1012 | val32 &= ~(1 << 17); | |
1013 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32); | |
1014 | ||
1015 | /* Setup interrupts */ | |
1016 | ppc7d_intr_setup(); | |
1017 | } | |
1018 | ||
1019 | static void __init ppc7d_setup_bridge(void) | |
1020 | { | |
1021 | struct mv64x60_setup_info si; | |
1022 | int i; | |
1023 | u32 temp; | |
1024 | ||
1025 | mv64360_irq_base = 16; /* first 16 intrs are 2 x 8259's */ | |
1026 | ||
1027 | memset(&si, 0, sizeof(si)); | |
1028 | ||
1029 | si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; | |
1030 | ||
1031 | si.pci_0.enable_bus = 1; | |
1032 | si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR; | |
1033 | si.pci_0.pci_io.pci_base_hi = 0; | |
1034 | si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR; | |
1035 | si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE; | |
1036 | si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1037 | si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR; | |
1038 | si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR; | |
1039 | si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR; | |
1040 | si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE; | |
1041 | si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1042 | si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR; | |
1043 | si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR; | |
1044 | si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR; | |
1045 | si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE; | |
1046 | si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1047 | si.pci_0.pci_cmd_bits = 0; | |
1048 | si.pci_0.latency_timer = 0x80; | |
1049 | ||
1050 | si.pci_1.enable_bus = 1; | |
1051 | si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR; | |
1052 | si.pci_1.pci_io.pci_base_hi = 0; | |
1053 | si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR; | |
1054 | si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE; | |
1055 | si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1056 | si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR; | |
1057 | si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR; | |
1058 | si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR; | |
1059 | si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE; | |
1060 | si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1061 | si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR; | |
1062 | si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR; | |
1063 | si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR; | |
1064 | si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE; | |
1065 | si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE; | |
1066 | si.pci_1.pci_cmd_bits = 0; | |
1067 | si.pci_1.latency_timer = 0x80; | |
1068 | ||
1069 | /* Don't clear the SRAM window since we use it for debug */ | |
1070 | si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN); | |
1071 | ||
1072 | printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n", | |
1073 | si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size); | |
1074 | printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n", | |
1075 | si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size); | |
1076 | ||
1077 | for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { | |
1078 | #if defined(CONFIG_NOT_COHERENT_CACHE) | |
1079 | si.cpu_prot_options[i] = 0; | |
1080 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; | |
1081 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; | |
1082 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; | |
1083 | ||
1084 | si.pci_0.acc_cntl_options[i] = | |
1085 | MV64360_PCI_ACC_CNTL_SNOOP_NONE | | |
1086 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1087 | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | | |
1088 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; | |
1089 | ||
1090 | si.pci_1.acc_cntl_options[i] = | |
1091 | MV64360_PCI_ACC_CNTL_SNOOP_NONE | | |
1092 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1093 | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | | |
1094 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; | |
1095 | #else | |
1096 | si.cpu_prot_options[i] = 0; | |
1097 | /* All PPC7D hardware uses B0 or newer MV64360 silicon which | |
1098 | * does not have snoop bugs. | |
1099 | */ | |
1100 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; | |
1101 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; | |
1102 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; | |
1103 | ||
1104 | si.pci_0.acc_cntl_options[i] = | |
1105 | MV64360_PCI_ACC_CNTL_SNOOP_WB | | |
1106 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1107 | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | | |
1108 | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; | |
1109 | ||
1110 | si.pci_1.acc_cntl_options[i] = | |
1111 | MV64360_PCI_ACC_CNTL_SNOOP_WB | | |
1112 | MV64360_PCI_ACC_CNTL_SWAP_NONE | | |
1113 | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | | |
1114 | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; | |
1115 | #endif | |
1116 | } | |
1117 | ||
1118 | /* Lookup PCI host bridges */ | |
1119 | if (mv64x60_init(&bh, &si)) | |
1120 | printk(KERN_ERR "MV64360 initialization failed.\n"); | |
1121 | ||
1122 | pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base); | |
1123 | ||
1124 | /* Enable WB Cache coherency on SRAM */ | |
1125 | temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG); | |
1126 | pr_debug("SRAM_CONFIG: %x\n", temp); | |
1127 | #if defined(CONFIG_NOT_COHERENT_CACHE) | |
1128 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2); | |
1129 | #else | |
1130 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2); | |
1131 | #endif | |
1132 | /* If system operates with internal bus arbiter (CPU master | |
1133 | * control bit8) clear AACK Delay bit [25] in CPU | |
1134 | * configuration register. | |
1135 | */ | |
1136 | temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL); | |
1137 | if (temp & (1 << 8)) { | |
1138 | temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
1139 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25))); | |
1140 | } | |
1141 | ||
1142 | /* Data and address parity is enabled */ | |
1143 | temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG); | |
1144 | mv64x60_write(&bh, MV64x60_CPU_CONFIG, | |
1145 | (temp | (1 << 26) | (1 << 19))); | |
1146 | ||
1147 | pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ | |
1148 | ppc_md.pci_swizzle = common_swizzle; | |
1149 | ppc_md.pci_map_irq = ppc7d_map_irq; | |
1150 | ppc_md.pci_exclude_device = ppc7d_pci_exclude_device; | |
1151 | ||
1152 | mv64x60_set_bus(&bh, 0, 0); | |
1153 | bh.hose_a->first_busno = 0; | |
1154 | bh.hose_a->last_busno = 0xff; | |
1155 | bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR; | |
1156 | bh.hose_a->mem_space.end = | |
1157 | PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE; | |
1158 | ||
1159 | /* These will be set later, as a result of PCI0 scan */ | |
1160 | bh.hose_b->first_busno = 0; | |
1161 | bh.hose_b->last_busno = 0xff; | |
1162 | bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR; | |
1163 | bh.hose_b->mem_space.end = | |
1164 | PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE; | |
1165 | ||
1166 | pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n", | |
1167 | mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50), | |
1168 | mv64x60_read(&bh, 0xf0)); | |
1169 | } | |
1170 | ||
1171 | static void __init ppc7d_setup_arch(void) | |
1172 | { | |
1173 | int port; | |
1174 | ||
1175 | loops_per_jiffy = 100000000 / HZ; | |
1176 | ||
1177 | #ifdef CONFIG_BLK_DEV_INITRD | |
1178 | if (initrd_start) | |
1179 | ROOT_DEV = Root_RAM0; | |
1180 | else | |
1181 | #endif | |
1182 | #ifdef CONFIG_ROOT_NFS | |
1183 | ROOT_DEV = Root_NFS; | |
1184 | #else | |
1185 | ROOT_DEV = Root_HDA1; | |
1186 | #endif | |
1187 | ||
400d2212 KG |
1188 | if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) || |
1189 | (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)) | |
1da177e4 LT |
1190 | /* 745x is different. We only want to pass along enable. */ |
1191 | _set_L2CR(L2CR_L2E); | |
400d2212 | 1192 | else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR) |
1da177e4 LT |
1193 | /* All modules have 1MB of L2. We also assume that an |
1194 | * L2 divisor of 3 will work. | |
1195 | */ | |
1196 | _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 | |
1197 | | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); | |
1198 | ||
400d2212 | 1199 | if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR) |
1da177e4 LT |
1200 | /* No L3 cache */ |
1201 | _set_L3CR(0); | |
1202 | ||
1203 | #ifdef CONFIG_DUMMY_CONSOLE | |
1204 | conswitchp = &dummy_con; | |
1205 | #endif | |
1206 | ||
1207 | /* Lookup PCI host bridges */ | |
1208 | if (ppc_md.progress) | |
1209 | ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0); | |
1210 | ||
1211 | ppc7d_setup_bridge(); | |
1212 | ppc7d_setup_peripherals(); | |
1213 | ||
1214 | /* Disable ethernet. It might have been setup by the bootrom */ | |
1215 | for (port = 0; port < 3; port++) | |
1216 | mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port), | |
1217 | 0x0000ff00); | |
1218 | ||
1219 | /* Clear queue pointers to ensure they are all initialized, | |
1220 | * otherwise since queues 1-7 are unused, they have random | |
1221 | * pointers which look strange in register dumps. Don't bother | |
1222 | * with queue 0 since it will be initialized later. | |
1223 | */ | |
1224 | for (port = 0; port < 3; port++) { | |
1225 | mv64x60_write(&bh, | |
1226 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port), | |
1227 | 0x00000000); | |
1228 | mv64x60_write(&bh, | |
1229 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port), | |
1230 | 0x00000000); | |
1231 | mv64x60_write(&bh, | |
1232 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port), | |
1233 | 0x00000000); | |
1234 | mv64x60_write(&bh, | |
1235 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port), | |
1236 | 0x00000000); | |
1237 | mv64x60_write(&bh, | |
1238 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port), | |
1239 | 0x00000000); | |
1240 | mv64x60_write(&bh, | |
1241 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port), | |
1242 | 0x00000000); | |
1243 | mv64x60_write(&bh, | |
1244 | MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port), | |
1245 | 0x00000000); | |
1246 | } | |
1247 | ||
1248 | printk(KERN_INFO "Radstone Technology PPC7D\n"); | |
1249 | if (ppc_md.progress) | |
1250 | ppc_md.progress("ppc7d_setup_arch: exit", 0); | |
a497aa20 CE |
1251 | |
1252 | } | |
1253 | ||
1254 | /* Real Time Clock support. | |
1255 | * PPC7D has a DS1337 accessed by I2C. | |
1256 | */ | |
1257 | static ulong ppc7d_get_rtc_time(void) | |
1258 | { | |
1259 | struct rtc_time tm; | |
1260 | int result; | |
1261 | ||
1262 | spin_lock(&rtc_lock); | |
1263 | result = ds1337_do_command(0, DS1337_GET_DATE, &tm); | |
1264 | spin_unlock(&rtc_lock); | |
1265 | ||
1266 | if (result == 0) | |
1267 | result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); | |
1268 | ||
1269 | return result; | |
1270 | } | |
1271 | ||
1272 | static int ppc7d_set_rtc_time(unsigned long nowtime) | |
1273 | { | |
1274 | struct rtc_time tm; | |
1275 | int result; | |
1276 | ||
1277 | spin_lock(&rtc_lock); | |
1278 | to_tm(nowtime, &tm); | |
1279 | result = ds1337_do_command(0, DS1337_SET_DATE, &tm); | |
1280 | spin_unlock(&rtc_lock); | |
1281 | ||
1282 | return result; | |
1da177e4 LT |
1283 | } |
1284 | ||
1285 | /* This kernel command line parameter can be used to have the target | |
1286 | * wait for a JTAG debugger to attach. Of course, a JTAG debugger | |
1287 | * with hardware breakpoint support can have the target stop at any | |
1288 | * location during init, but this is a convenience feature that makes | |
1289 | * it easier in the common case of loading the code using the ppcboot | |
1290 | * bootloader.. | |
1291 | */ | |
1292 | static unsigned long ppc7d_wait_debugger; | |
1293 | ||
1294 | static int __init ppc7d_waitdbg(char *str) | |
1295 | { | |
1296 | ppc7d_wait_debugger = 1; | |
1297 | return 1; | |
1298 | } | |
1299 | ||
1300 | __setup("waitdbg", ppc7d_waitdbg); | |
1301 | ||
1302 | /* Second phase board init, called after other (architecture common) | |
1303 | * low-level services have been initialized. | |
1304 | */ | |
1305 | static void ppc7d_init2(void) | |
1306 | { | |
1307 | unsigned long flags; | |
1308 | u32 data; | |
1309 | u8 data8; | |
1310 | ||
1311 | pr_debug("%s: enter\n", __FUNCTION__); | |
1312 | ||
1313 | /* Wait for debugger? */ | |
1314 | if (ppc7d_wait_debugger) { | |
1315 | printk("Waiting for debugger...\n"); | |
1316 | ||
1317 | while (readl(&ppc7d_wait_debugger)) ; | |
1318 | } | |
1319 | ||
1320 | /* Hook up i8259 interrupt which is connected to GPP28 */ | |
1321 | request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr, | |
1322 | SA_INTERRUPT, "I8259 (GPP28) interrupt", (void *)0); | |
1323 | ||
1324 | /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */ | |
1325 | spin_lock_irqsave(&mv64x60_lock, flags); | |
1326 | data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); | |
1327 | data &= ~(0x0000000f << 0); | |
1328 | data |= (0x00000004 << 0); | |
1329 | data &= ~(0x0000000f << 4); | |
1330 | data |= (0x00000004 << 4); | |
1331 | mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); | |
1332 | spin_unlock_irqrestore(&mv64x60_lock, flags); | |
1333 | ||
1334 | /* All LEDs off */ | |
1335 | data8 = inb(PPC7D_CPLD_LEDS); | |
1336 | data8 &= ~0x08; | |
1337 | data8 |= 0x07; | |
1338 | outb(data8, PPC7D_CPLD_LEDS); | |
1339 | ||
a497aa20 CE |
1340 | /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */ |
1341 | ppc_md.set_rtc_time = ppc7d_set_rtc_time; | |
1342 | ppc_md.get_rtc_time = ppc7d_get_rtc_time; | |
1343 | ||
1da177e4 LT |
1344 | pr_debug("%s: exit\n", __FUNCTION__); |
1345 | } | |
1346 | ||
1347 | /* Called from machine_init(), early, before any of the __init functions | |
1348 | * have run. We must init software-configurable pins before other functions | |
1349 | * such as interrupt controllers are initialised. | |
1350 | */ | |
1351 | void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
1352 | unsigned long r6, unsigned long r7) | |
1353 | { | |
1354 | u8 val8; | |
1355 | u8 rev_num; | |
1356 | ||
1357 | /* Map 0xe0000000-0xffffffff early because we need access to SRAM | |
1358 | * and the ISA memory space (for serial port) here. This mapping | |
1359 | * is redone properly in ppc7d_map_io() later. | |
1360 | */ | |
1361 | mtspr(SPRN_DBAT3U, 0xe0003fff); | |
1362 | mtspr(SPRN_DBAT3L, 0xe000002a); | |
1363 | ||
1364 | /* | |
1365 | * Zero SRAM. Note that this generates parity errors on | |
1366 | * internal data path in SRAM if it's first time accessing it | |
1367 | * after reset. | |
1368 | * | |
1369 | * We do this ASAP to avoid parity errors when reading | |
1370 | * uninitialized SRAM. | |
1371 | */ | |
1372 | memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE); | |
1373 | ||
1374 | pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n", | |
1375 | r3, r4, r5, r6, r7); | |
1376 | ||
1377 | parse_bootinfo(find_bootinfo()); | |
1378 | ||
1379 | /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) | |
1380 | * are non-zero, then we should use the board info from the bd_t | |
1381 | * structure and the cmdline pointed to by r6 instead of the | |
1382 | * information from birecs, if any. Otherwise, use the information | |
1383 | * from birecs as discovered by the preceeding call to | |
1384 | * parse_bootinfo(). This rule should work with both PPCBoot, which | |
1385 | * uses a bd_t board info structure, and the kernel boot wrapper, | |
1386 | * which uses birecs. | |
1387 | */ | |
1388 | if (r3 && r6) { | |
1389 | bd_t *bp = (bd_t *) __res; | |
1390 | ||
1391 | /* copy board info structure */ | |
1392 | memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t)); | |
1393 | /* copy command line */ | |
1394 | *(char *)(r7 + KERNELBASE) = 0; | |
1395 | strcpy(cmd_line, (char *)(r6 + KERNELBASE)); | |
1396 | ||
1397 | printk(KERN_INFO "Board info data:-\n"); | |
1398 | printk(KERN_INFO " Internal freq: %lu MHz, bus freq: %lu MHz\n", | |
1399 | bp->bi_intfreq, bp->bi_busfreq); | |
1400 | printk(KERN_INFO " Memory: %lx, size %lx\n", bp->bi_memstart, | |
1401 | bp->bi_memsize); | |
1402 | printk(KERN_INFO " Console baudrate: %lu\n", bp->bi_baudrate); | |
1403 | printk(KERN_INFO " Ethernet address: " | |
1404 | "%02x:%02x:%02x:%02x:%02x:%02x\n", | |
1405 | bp->bi_enetaddr[0], bp->bi_enetaddr[1], | |
1406 | bp->bi_enetaddr[2], bp->bi_enetaddr[3], | |
1407 | bp->bi_enetaddr[4], bp->bi_enetaddr[5]); | |
1408 | } | |
1409 | #ifdef CONFIG_BLK_DEV_INITRD | |
1410 | /* take care of initrd if we have one */ | |
1411 | if (r4) { | |
1412 | initrd_start = r4 + KERNELBASE; | |
1413 | initrd_end = r5 + KERNELBASE; | |
1414 | printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end); | |
1415 | } | |
1416 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
1417 | ||
1418 | /* Map in board regs, etc. */ | |
1419 | isa_io_base = 0xe8000000; | |
1420 | isa_mem_base = 0xe8000000; | |
1421 | pci_dram_offset = 0x00000000; | |
1422 | ISA_DMA_THRESHOLD = 0x00ffffff; | |
1423 | DMA_MODE_READ = 0x44; | |
1424 | DMA_MODE_WRITE = 0x48; | |
1425 | ||
1426 | ppc_md.setup_arch = ppc7d_setup_arch; | |
1427 | ppc_md.init = ppc7d_init2; | |
1428 | ppc_md.show_cpuinfo = ppc7d_show_cpuinfo; | |
1429 | ppc_md.irq_canonicalize = ppc7d_irq_canonicalize; | |
1430 | ppc_md.init_IRQ = ppc7d_init_irq; | |
1431 | ppc_md.get_irq = ppc7d_get_irq; | |
1432 | ||
1433 | ppc_md.restart = ppc7d_restart; | |
1434 | ppc_md.power_off = ppc7d_power_off; | |
1435 | ppc_md.halt = ppc7d_halt; | |
1436 | ||
1437 | ppc_md.find_end_of_memory = ppc7d_find_end_of_memory; | |
1438 | ppc_md.setup_io_mappings = ppc7d_map_io; | |
1439 | ||
1440 | ppc_md.time_init = NULL; | |
1441 | ppc_md.set_rtc_time = NULL; | |
1442 | ppc_md.get_rtc_time = NULL; | |
1443 | ppc_md.calibrate_decr = ppc7d_calibrate_decr; | |
1444 | ppc_md.nvram_read_val = NULL; | |
1445 | ppc_md.nvram_write_val = NULL; | |
1446 | ||
1447 | ppc_md.heartbeat = ppc7d_heartbeat; | |
1448 | ppc_md.heartbeat_reset = HZ; | |
1449 | ppc_md.heartbeat_count = ppc_md.heartbeat_reset; | |
1450 | ||
1451 | ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus; | |
1452 | ||
1453 | #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \ | |
1454 | defined(CONFIG_I2C_MV64XXX) | |
1455 | platform_notify = ppc7d_platform_notify; | |
1456 | #endif | |
1457 | ||
1458 | #ifdef CONFIG_SERIAL_MPSC | |
1459 | /* On PPC7D, we must configure MPSC support via CPLD control | |
1460 | * registers. | |
1461 | */ | |
1462 | outb(PPC7D_CPLD_RTS_COM4_SCLK | | |
1463 | PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS); | |
1464 | outb(PPC7D_CPLD_COMS_COM3_TCLKEN | | |
1465 | PPC7D_CPLD_COMS_COM3_TXEN | | |
1466 | PPC7D_CPLD_COMS_COM4_TCLKEN | | |
1467 | PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS); | |
1468 | #endif /* CONFIG_SERIAL_MPSC */ | |
1469 | ||
1470 | #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) | |
1471 | ppc7d_early_serial_map(); | |
1472 | #ifdef CONFIG_SERIAL_TEXT_DEBUG | |
1473 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) | |
1474 | ppc_md.progress = mv64x60_mpsc_progress; | |
1475 | #elif defined(CONFIG_SERIAL_8250) | |
1476 | ppc_md.progress = gen550_progress; | |
1477 | #else | |
1478 | #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX | |
1479 | #endif /* CONFIG_SERIAL_8250 */ | |
1480 | #endif /* CONFIG_SERIAL_TEXT_DEBUG */ | |
1481 | #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */ | |
1482 | ||
1483 | /* Enable write access to user flash. This is necessary for | |
1484 | * flash probe. | |
1485 | */ | |
1486 | val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); | |
1487 | writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED & | |
1488 | PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK), | |
1489 | (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); | |
1490 | ||
1491 | /* Determine if this board has IBM ALMA VME devices */ | |
1492 | val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION); | |
1493 | rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5; | |
1494 | if (rev_num <= 1) | |
1495 | ppc7d_has_alma = 1; | |
1496 | ||
1497 | #ifdef DEBUG | |
1498 | console_printk[0] = 8; | |
1499 | #endif | |
1500 | } |