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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), | |
3 | * IBM Corp. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #define DEBUG | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/bootmem.h> | |
19 | ||
20 | #include <asm/sections.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/pci-bridge.h> | |
24 | #include <asm/machdep.h> | |
25 | #include <asm/iommu.h> | |
26 | ||
27 | #include "pci.h" | |
28 | ||
29 | #ifdef DEBUG | |
30 | #define DBG(x...) printk(x) | |
31 | #else | |
32 | #define DBG(x...) | |
33 | #endif | |
34 | ||
35 | static struct pci_controller *u3_agp, *u3_ht; | |
36 | ||
37 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) | |
38 | { | |
39 | for (; node != 0;node = node->sibling) { | |
40 | int * bus_range; | |
41 | unsigned int *class_code; | |
42 | int len; | |
43 | ||
44 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
45 | class_code = (unsigned int *) get_property(node, "class-code", NULL); | |
46 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && | |
47 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
48 | continue; | |
49 | bus_range = (int *) get_property(node, "bus-range", &len); | |
50 | if (bus_range != NULL && len > 2 * sizeof(int)) { | |
51 | if (bus_range[1] > higher) | |
52 | higher = bus_range[1]; | |
53 | } | |
54 | higher = fixup_one_level_bus_range(node->child, higher); | |
55 | } | |
56 | return higher; | |
57 | } | |
58 | ||
59 | /* This routine fixes the "bus-range" property of all bridges in the | |
60 | * system since they tend to have their "last" member wrong on macs | |
61 | * | |
62 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
63 | * are not Linux bus numbers. | |
64 | */ | |
65 | static void __init fixup_bus_range(struct device_node *bridge) | |
66 | { | |
67 | int * bus_range; | |
68 | int len; | |
69 | ||
70 | /* Lookup the "bus-range" property for the hose */ | |
71 | bus_range = (int *) get_property(bridge, "bus-range", &len); | |
72 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
73 | printk(KERN_WARNING "Can't get bus-range for %s\n", | |
74 | bridge->full_name); | |
75 | return; | |
76 | } | |
77 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); | |
78 | } | |
79 | ||
80 | ||
81 | #define U3_AGP_CFA0(devfn, off) \ | |
82 | ((1 << (unsigned long)PCI_SLOT(dev_fn)) \ | |
83 | | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \ | |
84 | | (((unsigned long)(off)) & 0xFCUL)) | |
85 | ||
86 | #define U3_AGP_CFA1(bus, devfn, off) \ | |
87 | ((((unsigned long)(bus)) << 16) \ | |
88 | |(((unsigned long)(devfn)) << 8) \ | |
89 | |(((unsigned long)(off)) & 0xFCUL) \ | |
90 | |1UL) | |
91 | ||
92 | static unsigned long u3_agp_cfg_access(struct pci_controller* hose, | |
93 | u8 bus, u8 dev_fn, u8 offset) | |
94 | { | |
95 | unsigned int caddr; | |
96 | ||
97 | if (bus == hose->first_busno) { | |
98 | if (dev_fn < (11 << 3)) | |
99 | return 0; | |
100 | caddr = U3_AGP_CFA0(dev_fn, offset); | |
101 | } else | |
102 | caddr = U3_AGP_CFA1(bus, dev_fn, offset); | |
103 | ||
104 | /* Uninorth will return garbage if we don't read back the value ! */ | |
105 | do { | |
106 | out_le32(hose->cfg_addr, caddr); | |
107 | } while (in_le32(hose->cfg_addr) != caddr); | |
108 | ||
109 | offset &= 0x07; | |
110 | return ((unsigned long)hose->cfg_data) + offset; | |
111 | } | |
112 | ||
113 | static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, | |
114 | int offset, int len, u32 *val) | |
115 | { | |
116 | struct pci_controller *hose; | |
117 | unsigned long addr; | |
118 | ||
119 | hose = pci_bus_to_host(bus); | |
120 | if (hose == NULL) | |
121 | return PCIBIOS_DEVICE_NOT_FOUND; | |
122 | ||
123 | addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); | |
124 | if (!addr) | |
125 | return PCIBIOS_DEVICE_NOT_FOUND; | |
126 | /* | |
127 | * Note: the caller has already checked that offset is | |
128 | * suitably aligned and that len is 1, 2 or 4. | |
129 | */ | |
130 | switch (len) { | |
131 | case 1: | |
132 | *val = in_8((u8 *)addr); | |
133 | break; | |
134 | case 2: | |
135 | *val = in_le16((u16 *)addr); | |
136 | break; | |
137 | default: | |
138 | *val = in_le32((u32 *)addr); | |
139 | break; | |
140 | } | |
141 | return PCIBIOS_SUCCESSFUL; | |
142 | } | |
143 | ||
144 | static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, | |
145 | int offset, int len, u32 val) | |
146 | { | |
147 | struct pci_controller *hose; | |
148 | unsigned long addr; | |
149 | ||
150 | hose = pci_bus_to_host(bus); | |
151 | if (hose == NULL) | |
152 | return PCIBIOS_DEVICE_NOT_FOUND; | |
153 | ||
154 | addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); | |
155 | if (!addr) | |
156 | return PCIBIOS_DEVICE_NOT_FOUND; | |
157 | /* | |
158 | * Note: the caller has already checked that offset is | |
159 | * suitably aligned and that len is 1, 2 or 4. | |
160 | */ | |
161 | switch (len) { | |
162 | case 1: | |
163 | out_8((u8 *)addr, val); | |
164 | (void) in_8((u8 *)addr); | |
165 | break; | |
166 | case 2: | |
167 | out_le16((u16 *)addr, val); | |
168 | (void) in_le16((u16 *)addr); | |
169 | break; | |
170 | default: | |
171 | out_le32((u32 *)addr, val); | |
172 | (void) in_le32((u32 *)addr); | |
173 | break; | |
174 | } | |
175 | return PCIBIOS_SUCCESSFUL; | |
176 | } | |
177 | ||
178 | static struct pci_ops u3_agp_pci_ops = | |
179 | { | |
180 | u3_agp_read_config, | |
181 | u3_agp_write_config | |
182 | }; | |
183 | ||
184 | ||
185 | #define U3_HT_CFA0(devfn, off) \ | |
186 | ((((unsigned long)devfn) << 8) | offset) | |
187 | #define U3_HT_CFA1(bus, devfn, off) \ | |
188 | (U3_HT_CFA0(devfn, off) \ | |
189 | + (((unsigned long)bus) << 16) \ | |
190 | + 0x01000000UL) | |
191 | ||
192 | static unsigned long u3_ht_cfg_access(struct pci_controller* hose, | |
193 | u8 bus, u8 devfn, u8 offset) | |
194 | { | |
195 | if (bus == hose->first_busno) { | |
196 | if (PCI_SLOT(devfn) == 0) | |
197 | return 0; | |
198 | return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); | |
199 | } else | |
200 | return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); | |
201 | } | |
202 | ||
203 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, | |
204 | int offset, int len, u32 *val) | |
205 | { | |
206 | struct pci_controller *hose; | |
207 | unsigned long addr; | |
208 | ||
209 | hose = pci_bus_to_host(bus); | |
210 | if (hose == NULL) | |
211 | return PCIBIOS_DEVICE_NOT_FOUND; | |
212 | ||
213 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); | |
214 | if (!addr) | |
215 | return PCIBIOS_DEVICE_NOT_FOUND; | |
216 | ||
217 | /* | |
218 | * Note: the caller has already checked that offset is | |
219 | * suitably aligned and that len is 1, 2 or 4. | |
220 | */ | |
221 | switch (len) { | |
222 | case 1: | |
223 | *val = in_8((u8 *)addr); | |
224 | break; | |
225 | case 2: | |
226 | *val = in_le16((u16 *)addr); | |
227 | break; | |
228 | default: | |
229 | *val = in_le32((u32 *)addr); | |
230 | break; | |
231 | } | |
232 | return PCIBIOS_SUCCESSFUL; | |
233 | } | |
234 | ||
235 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, | |
236 | int offset, int len, u32 val) | |
237 | { | |
238 | struct pci_controller *hose; | |
239 | unsigned long addr; | |
240 | ||
241 | hose = pci_bus_to_host(bus); | |
242 | if (hose == NULL) | |
243 | return PCIBIOS_DEVICE_NOT_FOUND; | |
244 | ||
245 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); | |
246 | if (!addr) | |
247 | return PCIBIOS_DEVICE_NOT_FOUND; | |
248 | /* | |
249 | * Note: the caller has already checked that offset is | |
250 | * suitably aligned and that len is 1, 2 or 4. | |
251 | */ | |
252 | switch (len) { | |
253 | case 1: | |
254 | out_8((u8 *)addr, val); | |
255 | (void) in_8((u8 *)addr); | |
256 | break; | |
257 | case 2: | |
258 | out_le16((u16 *)addr, val); | |
259 | (void) in_le16((u16 *)addr); | |
260 | break; | |
261 | default: | |
262 | out_le32((u32 *)addr, val); | |
263 | (void) in_le32((u32 *)addr); | |
264 | break; | |
265 | } | |
266 | return PCIBIOS_SUCCESSFUL; | |
267 | } | |
268 | ||
269 | static struct pci_ops u3_ht_pci_ops = | |
270 | { | |
271 | u3_ht_read_config, | |
272 | u3_ht_write_config | |
273 | }; | |
274 | ||
275 | static void __init setup_u3_agp(struct pci_controller* hose) | |
276 | { | |
277 | /* On G5, we move AGP up to high bus number so we don't need | |
278 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
279 | * on AGP, we'll have to move pci_assign_all_busses to the | |
280 | * pci_controller structure so we enable it for AGP and not for | |
281 | * HT childs. | |
282 | * We hard code the address because of the different size of | |
283 | * the reg address cell, we shall fix that by killing struct | |
284 | * reg_property and using some accessor functions instead | |
285 | */ | |
286 | hose->first_busno = 0xf0; | |
287 | hose->last_busno = 0xff; | |
288 | hose->ops = &u3_agp_pci_ops; | |
289 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
290 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
291 | ||
292 | u3_agp = hose; | |
293 | } | |
294 | ||
295 | static void __init setup_u3_ht(struct pci_controller* hose) | |
296 | { | |
297 | hose->ops = &u3_ht_pci_ops; | |
298 | ||
299 | /* We hard code the address because of the different size of | |
300 | * the reg address cell, we shall fix that by killing struct | |
301 | * reg_property and using some accessor functions instead | |
302 | */ | |
303 | hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); | |
304 | ||
305 | hose->first_busno = 0; | |
306 | hose->last_busno = 0xef; | |
307 | ||
308 | u3_ht = hose; | |
309 | } | |
310 | ||
311 | static int __init add_bridge(struct device_node *dev) | |
312 | { | |
313 | int len; | |
314 | struct pci_controller *hose; | |
315 | char* disp_name; | |
316 | int *bus_range; | |
317 | int primary = 1; | |
318 | struct property *of_prop; | |
319 | ||
320 | DBG("Adding PCI host bridge %s\n", dev->full_name); | |
321 | ||
322 | bus_range = (int *) get_property(dev, "bus-range", &len); | |
323 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
324 | printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", | |
325 | dev->full_name); | |
326 | } | |
327 | ||
328 | hose = alloc_bootmem(sizeof(struct pci_controller)); | |
329 | if (hose == NULL) | |
330 | return -ENOMEM; | |
331 | pci_setup_pci_controller(hose); | |
332 | ||
333 | hose->arch_data = dev; | |
334 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
335 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
336 | ||
337 | of_prop = alloc_bootmem(sizeof(struct property) + | |
338 | sizeof(hose->global_number)); | |
339 | if (of_prop) { | |
340 | memset(of_prop, 0, sizeof(struct property)); | |
341 | of_prop->name = "linux,pci-domain"; | |
342 | of_prop->length = sizeof(hose->global_number); | |
343 | of_prop->value = (unsigned char *)&of_prop[1]; | |
344 | memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number)); | |
345 | prom_add_property(dev, of_prop); | |
346 | } | |
347 | ||
348 | disp_name = NULL; | |
349 | if (device_is_compatible(dev, "u3-agp")) { | |
350 | setup_u3_agp(hose); | |
351 | disp_name = "U3-AGP"; | |
352 | primary = 0; | |
353 | } else if (device_is_compatible(dev, "u3-ht")) { | |
354 | setup_u3_ht(hose); | |
355 | disp_name = "U3-HT"; | |
356 | primary = 1; | |
357 | } | |
358 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", | |
359 | disp_name, hose->first_busno, hose->last_busno); | |
360 | ||
361 | /* Interpret the "ranges" property */ | |
362 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
363 | pci_process_bridge_OF_ranges(hose, dev); | |
364 | pci_setup_phb_io(hose, primary); | |
365 | ||
366 | /* Fixup "bus-range" OF property */ | |
367 | fixup_bus_range(dev); | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | ||
373 | void __init maple_pcibios_fixup(void) | |
374 | { | |
375 | struct pci_dev *dev = NULL; | |
376 | ||
377 | DBG(" -> maple_pcibios_fixup\n"); | |
378 | ||
379 | for_each_pci_dev(dev) | |
380 | pci_read_irq_line(dev); | |
381 | ||
382 | /* Do the mapping of the IO space */ | |
383 | phbs_remap_io(); | |
384 | ||
385 | DBG(" <- maple_pcibios_fixup\n"); | |
386 | } | |
387 | ||
388 | static void __init maple_fixup_phb_resources(void) | |
389 | { | |
390 | struct pci_controller *hose, *tmp; | |
391 | ||
392 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
393 | unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
394 | hose->io_resource.start += offset; | |
395 | hose->io_resource.end += offset; | |
396 | printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", | |
397 | hose->global_number, | |
398 | hose->io_resource.start, hose->io_resource.end); | |
399 | } | |
400 | } | |
401 | ||
402 | void __init maple_pci_init(void) | |
403 | { | |
404 | struct device_node *np, *root; | |
405 | struct device_node *ht = NULL; | |
406 | ||
407 | /* Probe root PCI hosts, that is on U3 the AGP host and the | |
408 | * HyperTransport host. That one is actually "kept" around | |
409 | * and actually added last as it's resource management relies | |
410 | * on the AGP resources to have been setup first | |
411 | */ | |
412 | root = of_find_node_by_path("/"); | |
413 | if (root == NULL) { | |
414 | printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n"); | |
415 | return; | |
416 | } | |
417 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { | |
418 | if (np->name == NULL) | |
419 | continue; | |
420 | if (strcmp(np->name, "pci") == 0) { | |
421 | if (add_bridge(np) == 0) | |
422 | of_node_get(np); | |
423 | } | |
424 | if (strcmp(np->name, "ht") == 0) { | |
425 | of_node_get(np); | |
426 | ht = np; | |
427 | } | |
428 | } | |
429 | of_node_put(root); | |
430 | ||
431 | /* Now setup the HyperTransport host if we found any | |
432 | */ | |
433 | if (ht && add_bridge(ht) != 0) | |
434 | of_node_put(ht); | |
435 | ||
436 | /* Fixup the IO resources on our host bridges as the common code | |
437 | * does it only for childs of the host bridges | |
438 | */ | |
439 | maple_fixup_phb_resources(); | |
440 | ||
441 | /* Setup the linkage between OF nodes and PHBs */ | |
442 | pci_devs_phb_init(); | |
443 | ||
444 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We | |
445 | * assume there is no P2P bridge on the AGP bus, which should be a | |
446 | * safe assumptions hopefully. | |
447 | */ | |
448 | if (u3_agp) { | |
449 | struct device_node *np = u3_agp->arch_data; | |
450 | np->busno = 0xf0; | |
451 | for (np = np->child; np; np = np->sibling) | |
452 | np->busno = 0xf0; | |
453 | } | |
454 | ||
455 | /* Tell pci.c to use the common resource allocation mecanism */ | |
456 | pci_probe_only = 0; | |
457 | ||
458 | /* Allow all IO */ | |
459 | io_page_mask = -1; | |
460 | } | |
461 | ||
462 | int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel) | |
463 | { | |
464 | struct device_node *np; | |
465 | int irq = channel ? 15 : 14; | |
466 | ||
467 | if (pdev->vendor != PCI_VENDOR_ID_AMD || | |
468 | pdev->device != PCI_DEVICE_ID_AMD_8111_IDE) | |
469 | return irq; | |
470 | ||
471 | np = pci_device_to_OF_node(pdev); | |
472 | if (np == NULL) | |
473 | return irq; | |
474 | if (np->n_intrs < 2) | |
475 | return irq; | |
476 | return np->intrs[channel & 0x1].line; | |
477 | } | |
478 | ||
479 | /* XXX: To remove once all firmwares are ok */ | |
480 | static void fixup_maple_ide(struct pci_dev* dev) | |
481 | { | |
482 | #if 0 /* Enable this to enable IDE port 0 */ | |
483 | { | |
484 | u8 v; | |
485 | ||
486 | pci_read_config_byte(dev, 0x40, &v); | |
487 | v |= 2; | |
488 | pci_write_config_byte(dev, 0x40, v); | |
489 | } | |
490 | #endif | |
491 | #if 0 /* fix bus master base */ | |
492 | pci_write_config_dword(dev, 0x20, 0xcc01); | |
493 | printk("old ide resource: %lx -> %lx \n", | |
494 | dev->resource[4].start, dev->resource[4].end); | |
495 | dev->resource[4].start = 0xcc00; | |
496 | dev->resource[4].end = 0xcc10; | |
497 | #endif | |
498 | #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */ | |
499 | { | |
500 | struct pci_dev *apicdev; | |
501 | u32 v; | |
502 | ||
503 | apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0)); | |
504 | if (apicdev == NULL) | |
505 | printk("IDE Fixup IRQ: Can't find IO-APIC !\n"); | |
506 | else { | |
507 | pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14); | |
508 | pci_read_config_dword(apicdev, 0xf4, &v); | |
509 | v &= ~0x00000022; | |
510 | pci_write_config_dword(apicdev, 0xf4, v); | |
511 | pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15); | |
512 | pci_read_config_dword(apicdev, 0xf4, &v); | |
513 | v &= ~0x00000022; | |
514 | pci_write_config_dword(apicdev, 0xf4, v); | |
515 | pci_dev_put(apicdev); | |
516 | } | |
517 | } | |
518 | #endif | |
519 | } | |
520 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, | |
521 | fixup_maple_ide); |