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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/oprofile.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/smp.h> | |
13 | #include <asm/ptrace.h> | |
14 | #include <asm/system.h> | |
15 | #include <asm/processor.h> | |
16 | #include <asm/cputable.h> | |
17 | #include <asm/systemcfg.h> | |
18 | #include <asm/rtas.h> | |
19 | ||
20 | #define dbg(args...) | |
21 | ||
22 | #include "op_impl.h" | |
23 | ||
24 | static unsigned long reset_value[OP_MAX_COUNTER]; | |
25 | ||
26 | static int num_counters; | |
27 | static int oprofile_running; | |
28 | static int mmcra_has_sihv; | |
29 | ||
30 | /* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */ | |
31 | static u32 mmcr0_val; | |
32 | static u64 mmcr1_val; | |
33 | static u32 mmcra_val; | |
34 | ||
35 | /* | |
36 | * Since we do not have an NMI, backtracing through spinlocks is | |
37 | * only a best guess. In light of this, allow it to be disabled at | |
38 | * runtime. | |
39 | */ | |
40 | static int backtrace_spinlocks; | |
41 | ||
42 | static void power4_reg_setup(struct op_counter_config *ctr, | |
43 | struct op_system_config *sys, | |
44 | int num_ctrs) | |
45 | { | |
46 | int i; | |
47 | ||
48 | num_counters = num_ctrs; | |
49 | ||
50 | /* | |
51 | * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above. | |
52 | * However we disable it on all POWER4 until we verify it works | |
53 | * (I was seeing some strange behaviour last time I tried). | |
54 | * | |
55 | * It has been verified to work on POWER5 so we enable it there. | |
56 | */ | |
57 | if (cpu_has_feature(CPU_FTR_MMCRA_SIHV)) | |
58 | mmcra_has_sihv = 1; | |
59 | ||
60 | /* | |
61 | * The performance counter event settings are given in the mmcr0, | |
62 | * mmcr1 and mmcra values passed from the user in the | |
63 | * op_system_config structure (sys variable). | |
64 | */ | |
65 | mmcr0_val = sys->mmcr0; | |
66 | mmcr1_val = sys->mmcr1; | |
67 | mmcra_val = sys->mmcra; | |
68 | ||
69 | backtrace_spinlocks = sys->backtrace_spinlocks; | |
70 | ||
71 | for (i = 0; i < num_counters; ++i) | |
72 | reset_value[i] = 0x80000000UL - ctr[i].count; | |
73 | ||
74 | /* setup user and kernel profiling */ | |
75 | if (sys->enable_kernel) | |
76 | mmcr0_val &= ~MMCR0_KERNEL_DISABLE; | |
77 | else | |
78 | mmcr0_val |= MMCR0_KERNEL_DISABLE; | |
79 | ||
80 | if (sys->enable_user) | |
81 | mmcr0_val &= ~MMCR0_PROBLEM_DISABLE; | |
82 | else | |
83 | mmcr0_val |= MMCR0_PROBLEM_DISABLE; | |
84 | } | |
85 | ||
86 | extern void ppc64_enable_pmcs(void); | |
87 | ||
88 | static void power4_cpu_setup(void *unused) | |
89 | { | |
90 | unsigned int mmcr0 = mmcr0_val; | |
91 | unsigned long mmcra = mmcra_val; | |
92 | ||
93 | ppc64_enable_pmcs(); | |
94 | ||
95 | /* set the freeze bit */ | |
96 | mmcr0 |= MMCR0_FC; | |
97 | mtspr(SPRN_MMCR0, mmcr0); | |
98 | ||
99 | mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE; | |
100 | mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE; | |
101 | mtspr(SPRN_MMCR0, mmcr0); | |
102 | ||
103 | mtspr(SPRN_MMCR1, mmcr1_val); | |
104 | ||
105 | mmcra |= MMCRA_SAMPLE_ENABLE; | |
106 | mtspr(SPRN_MMCRA, mmcra); | |
107 | ||
108 | dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(), | |
109 | mfspr(SPRN_MMCR0)); | |
110 | dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(), | |
111 | mfspr(SPRN_MMCR1)); | |
112 | dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(), | |
113 | mfspr(SPRN_MMCRA)); | |
114 | } | |
115 | ||
116 | static void power4_start(struct op_counter_config *ctr) | |
117 | { | |
118 | int i; | |
119 | unsigned int mmcr0; | |
120 | ||
121 | /* set the PMM bit (see comment below) */ | |
122 | mtmsrd(mfmsr() | MSR_PMM); | |
123 | ||
124 | for (i = 0; i < num_counters; ++i) { | |
125 | if (ctr[i].enabled) { | |
126 | ctr_write(i, reset_value[i]); | |
127 | } else { | |
128 | ctr_write(i, 0); | |
129 | } | |
130 | } | |
131 | ||
132 | mmcr0 = mfspr(SPRN_MMCR0); | |
133 | ||
134 | /* | |
135 | * We must clear the PMAO bit on some (GQ) chips. Just do it | |
136 | * all the time | |
137 | */ | |
138 | mmcr0 &= ~MMCR0_PMAO; | |
139 | ||
140 | /* | |
141 | * now clear the freeze bit, counting will not start until we | |
142 | * rfid from this excetion, because only at that point will | |
143 | * the PMM bit be cleared | |
144 | */ | |
145 | mmcr0 &= ~MMCR0_FC; | |
146 | mtspr(SPRN_MMCR0, mmcr0); | |
147 | ||
148 | oprofile_running = 1; | |
149 | ||
150 | dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0); | |
151 | } | |
152 | ||
153 | static void power4_stop(void) | |
154 | { | |
155 | unsigned int mmcr0; | |
156 | ||
157 | /* freeze counters */ | |
158 | mmcr0 = mfspr(SPRN_MMCR0); | |
159 | mmcr0 |= MMCR0_FC; | |
160 | mtspr(SPRN_MMCR0, mmcr0); | |
161 | ||
162 | oprofile_running = 0; | |
163 | ||
164 | dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0); | |
165 | ||
166 | mb(); | |
167 | } | |
168 | ||
169 | /* Fake functions used by canonicalize_pc */ | |
170 | static void __attribute_used__ hypervisor_bucket(void) | |
171 | { | |
172 | } | |
173 | ||
174 | static void __attribute_used__ rtas_bucket(void) | |
175 | { | |
176 | } | |
177 | ||
178 | static void __attribute_used__ kernel_unknown_bucket(void) | |
179 | { | |
180 | } | |
181 | ||
182 | static unsigned long check_spinlock_pc(struct pt_regs *regs, | |
183 | unsigned long profile_pc) | |
184 | { | |
185 | unsigned long pc = instruction_pointer(regs); | |
186 | ||
187 | /* | |
188 | * If both the SIAR (sampled instruction) and the perfmon exception | |
189 | * occurred in a spinlock region then we account the sample to the | |
190 | * calling function. This isnt 100% correct, we really need soft | |
191 | * IRQ disable so we always get the perfmon exception at the | |
192 | * point at which the SIAR is set. | |
193 | */ | |
194 | if (backtrace_spinlocks && in_lock_functions(pc) && | |
195 | in_lock_functions(profile_pc)) | |
196 | return regs->link; | |
197 | else | |
198 | return profile_pc; | |
199 | } | |
200 | ||
201 | /* | |
202 | * On GQ and newer the MMCRA stores the HV and PR bits at the time | |
203 | * the SIAR was sampled. We use that to work out if the SIAR was sampled in | |
204 | * the hypervisor, our exception vectors or RTAS. | |
205 | */ | |
206 | static unsigned long get_pc(struct pt_regs *regs) | |
207 | { | |
208 | unsigned long pc = mfspr(SPRN_SIAR); | |
209 | unsigned long mmcra; | |
210 | ||
211 | /* Cant do much about it */ | |
212 | if (!mmcra_has_sihv) | |
213 | return check_spinlock_pc(regs, pc); | |
214 | ||
215 | mmcra = mfspr(SPRN_MMCRA); | |
216 | ||
217 | /* Were we in the hypervisor? */ | |
218 | if ((systemcfg->platform == PLATFORM_PSERIES_LPAR) && | |
219 | (mmcra & MMCRA_SIHV)) | |
220 | /* function descriptor madness */ | |
221 | return *((unsigned long *)hypervisor_bucket); | |
222 | ||
223 | /* We were in userspace, nothing to do */ | |
224 | if (mmcra & MMCRA_SIPR) | |
225 | return pc; | |
226 | ||
227 | #ifdef CONFIG_PPC_RTAS | |
228 | /* Were we in RTAS? */ | |
229 | if (pc >= rtas.base && pc < (rtas.base + rtas.size)) | |
230 | /* function descriptor madness */ | |
231 | return *((unsigned long *)rtas_bucket); | |
232 | #endif | |
233 | ||
234 | /* Were we in our exception vectors or SLB real mode miss handler? */ | |
235 | if (pc < 0x1000000UL) | |
236 | return (unsigned long)__va(pc); | |
237 | ||
238 | /* Not sure where we were */ | |
239 | if (pc < KERNELBASE) | |
240 | /* function descriptor madness */ | |
241 | return *((unsigned long *)kernel_unknown_bucket); | |
242 | ||
243 | return check_spinlock_pc(regs, pc); | |
244 | } | |
245 | ||
246 | static int get_kernel(unsigned long pc) | |
247 | { | |
248 | int is_kernel; | |
249 | ||
250 | if (!mmcra_has_sihv) { | |
251 | is_kernel = (pc >= KERNELBASE); | |
252 | } else { | |
253 | unsigned long mmcra = mfspr(SPRN_MMCRA); | |
254 | is_kernel = ((mmcra & MMCRA_SIPR) == 0); | |
255 | } | |
256 | ||
257 | return is_kernel; | |
258 | } | |
259 | ||
260 | static void power4_handle_interrupt(struct pt_regs *regs, | |
261 | struct op_counter_config *ctr) | |
262 | { | |
263 | unsigned long pc; | |
264 | int is_kernel; | |
265 | int val; | |
266 | int i; | |
267 | unsigned int mmcr0; | |
268 | ||
269 | pc = get_pc(regs); | |
270 | is_kernel = get_kernel(pc); | |
271 | ||
272 | /* set the PMM bit (see comment below) */ | |
273 | mtmsrd(mfmsr() | MSR_PMM); | |
274 | ||
275 | for (i = 0; i < num_counters; ++i) { | |
276 | val = ctr_read(i); | |
277 | if (val < 0) { | |
278 | if (oprofile_running && ctr[i].enabled) { | |
279 | oprofile_add_pc(pc, is_kernel, i); | |
280 | ctr_write(i, reset_value[i]); | |
281 | } else { | |
282 | ctr_write(i, 0); | |
283 | } | |
284 | } | |
285 | } | |
286 | ||
287 | mmcr0 = mfspr(SPRN_MMCR0); | |
288 | ||
289 | /* reset the perfmon trigger */ | |
290 | mmcr0 |= MMCR0_PMXE; | |
291 | ||
292 | /* | |
293 | * We must clear the PMAO bit on some (GQ) chips. Just do it | |
294 | * all the time | |
295 | */ | |
296 | mmcr0 &= ~MMCR0_PMAO; | |
297 | ||
298 | /* | |
299 | * now clear the freeze bit, counting will not start until we | |
300 | * rfid from this exception, because only at that point will | |
301 | * the PMM bit be cleared | |
302 | */ | |
303 | mmcr0 &= ~MMCR0_FC; | |
304 | mtspr(SPRN_MMCR0, mmcr0); | |
305 | } | |
306 | ||
307 | struct op_ppc64_model op_model_power4 = { | |
308 | .reg_setup = power4_reg_setup, | |
309 | .cpu_setup = power4_cpu_setup, | |
310 | .start = power4_start, | |
311 | .stop = power4_stop, | |
312 | .handle_interrupt = power4_handle_interrupt, | |
313 | }; |