[mirror_ubuntu-jammy-kernel.git] / arch / riscv / include / asm / io.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
 *   which was based on arch/arm/include/io.h
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 * Copyright (C) 2014 Regents of the University of California
 */

#ifndef _ASM_RISCV_IO_H
#define _ASM_RISCV_IO_H

#include <linux/types.h>
#include <linux/pgtable.h>
#include <asm/mmiowb.h>

/*
 * MMIO access functions are separated out to break dependency cycles
 * when using {read,write}* fns in low-level headers
 */
#include <asm/mmio.h>

/*
 *  I/O port access constants.
 */
#ifdef CONFIG_MMU
#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
#define PCI_IOBASE		((void __iomem *)PCI_IO_START)
#endif /* CONFIG_MMU */

/*
 * Emulation routines for the port-mapped IO space used by some PCI drivers.
 * These are defined as being "fully synchronous", but also "not guaranteed to
 * be fully ordered with respect to other memory and I/O operations".  We're
 * going to be on the safe side here and just make them:
 *  - Fully ordered WRT each other, by bracketing them with two fences.  The
 *    outer set contains both I/O so inX is ordered with outX, while the inner just
 *    needs the type of the access (I for inX and O for outX).
 *  - Ordered in the same manner as readX/writeX WRT memory by subsuming their
 *    fences.
 *  - Ordered WRT timer reads, so udelay and friends don't get elided by the
 *    implementation.
 * Note that there is no way to actually enforce that outX is a non-posted
 * operation on RISC-V, but hopefully the timer ordering constraint is
 * sufficient to ensure this works sanely on controllers that support I/O
 * writes.
 */
#define __io_pbr()	__asm__ __volatile__ ("fence io,i"  : : : "memory");
#define __io_par(v)	__asm__ __volatile__ ("fence i,ior" : : : "memory");
#define __io_pbw()	__asm__ __volatile__ ("fence iow,o" : : : "memory");
#define __io_paw()	__asm__ __volatile__ ("fence o,io"  : : : "memory");

#define inb(c)		({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
#define inw(c)		({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
#define inl(c)		({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })

#define outb(v,c)	({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
#define outw(v,c)	({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
#define outl(v,c)	({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })

#ifdef CONFIG_64BIT
#define inq(c)		({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
#define outq(v,c)	({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
#endif

/*
 * Accesses from a single hart to a single I/O address must be ordered.  This
 * allows us to use the raw read macros, but we still need to fence before and
 * after the block to ensure ordering WRT other macros.  These are defined to
 * perform host-endian accesses so we use __raw instead of __cpu.
 */
#define __io_reads_ins(port, ctype, len, bfence, afence)			\
	static inline void __ ## port ## len(const volatile void __iomem *addr,	\
					     void *buffer,			\
					     unsigned int count)		\
	{									\
		bfence;								\
		if (count) {							\
			ctype *buf = buffer;					\
										\
			do {							\
				ctype x = __raw_read ## len(addr);		\
				*buf++ = x;					\
			} while (--count);					\
		}								\
		afence;								\
	}

#define __io_writes_outs(port, ctype, len, bfence, afence)			\
	static inline void __ ## port ## len(volatile void __iomem *addr,	\
					     const void *buffer,		\
					     unsigned int count)		\
	{									\
		bfence;								\
		if (count) {							\
			const ctype *buf = buffer;				\
										\
			do {							\
				__raw_write ## len(*buf++, addr);		\
			} while (--count);					\
		}								\
		afence;								\
	}

__io_reads_ins(reads,  u8, b, __io_br(), __io_ar(addr))
__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
#define readsb(addr, buffer, count) __readsb(addr, buffer, count)
#define readsw(addr, buffer, count) __readsw(addr, buffer, count)
#define readsl(addr, buffer, count) __readsl(addr, buffer, count)

__io_reads_ins(ins,  u8, b, __io_pbr(), __io_par(addr))
__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)

__io_writes_outs(writes,  u8, b, __io_bw(), __io_aw())
__io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
__io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
#define writesb(addr, buffer, count) __writesb(addr, buffer, count)
#define writesw(addr, buffer, count) __writesw(addr, buffer, count)
#define writesl(addr, buffer, count) __writesl(addr, buffer, count)

__io_writes_outs(outs,  u8, b, __io_pbw(), __io_paw())
__io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
__io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)

#ifdef CONFIG_64BIT
__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
#define readsq(addr, buffer, count) __readsq(addr, buffer, count)

__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)

__io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
#define writesq(addr, buffer, count) __writesq(addr, buffer, count)

__io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
#endif

#include <asm-generic/io.h>

#endif /* _ASM_RISCV_IO_H */
Commit	Line	Data
50acfb2b	1	/* SPDX-License-Identifier: GPL-2.0-only */
fab957c1 PD	2	/*
	3	* {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
	4	* which was based on arch/arm/include/io.h
	5	*
	6	* Copyright (C) 1996-2000 Russell King
	7	* Copyright (C) 2012 ARM Ltd.
	8	* Copyright (C) 2014 Regents of the University of California
fab957c1 PD	9	*/
	10
	11	#ifndef _ASM_RISCV_IO_H
	12	#define _ASM_RISCV_IO_H
	13
fe2726af	14	#include <linux/types.h>
ca5999fd	15	#include <linux/pgtable.h>
65fddcfc	16	#include <asm/mmiowb.h>
fe2726af	17
fab957c1	18	/*
0c3ac289 PW	19	* MMIO access functions are separated out to break dependency cycles
0c3ac289 PW	20	* when using {read,write}* fns in low-level headers
fab957c1	21	*/
0c3ac289	22	#include <asm/mmio.h>
fab957c1	23
00a5bf3a YS	24	/*
	25	* I/O port access constants.
	26	*/
6bd33e1e	27	#ifdef CONFIG_MMU
00a5bf3a YS	28	#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
00a5bf3a YS	29	#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
6bd33e1e	30	#endif /* CONFIG_MMU */
00a5bf3a	31
fab957c1 PD	32	/*
	33	* Emulation routines for the port-mapped IO space used by some PCI drivers.
	34	* These are defined as being "fully synchronous", but also "not guaranteed to
	35	* be fully ordered with respect to other memory and I/O operations". We're
	36	* going to be on the safe side here and just make them:
	37	* - Fully ordered WRT each other, by bracketing them with two fences. The
	38	* outer set contains both I/O so inX is ordered with outX, while the inner just
	39	* needs the type of the access (I for inX and O for outX).
	40	* - Ordered in the same manner as readX/writeX WRT memory by subsuming their
	41	* fences.
	42	* - Ordered WRT timer reads, so udelay and friends don't get elided by the
	43	* implementation.
	44	* Note that there is no way to actually enforce that outX is a non-posted
	45	* operation on RISC-V, but hopefully the timer ordering constraint is
	46	* sufficient to ensure this works sanely on controllers that support I/O
	47	* writes.
	48	*/
	49	#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory");
ce246c44	50	#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory");
fab957c1 PD	51	#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory");
	52	#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory");
	53
ce246c44 WD	54	#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
	55	#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
	56	#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
fab957c1 PD	57
	58	#define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
	59	#define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
	60	#define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
	61
	62	#ifdef CONFIG_64BIT
ce246c44	63	#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
fab957c1 PD	64	#define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
	65	#endif
	66
	67	/*
	68	* Accesses from a single hart to a single I/O address must be ordered. This
	69	* allows us to use the raw read macros, but we still need to fence before and
	70	* after the block to ensure ordering WRT other macros. These are defined to
	71	* perform host-endian accesses so we use __raw instead of __cpu.
	72	*/
	73	#define __io_reads_ins(port, ctype, len, bfence, afence) \
	74	static inline void __ ## port ## len(const volatile void __iomem *addr, \
	75	void *buffer, \
	76	unsigned int count) \
	77	{ \
	78	bfence; \
	79	if (count) { \
	80	ctype *buf = buffer; \
	81	\
	82	do { \
	83	ctype x = __raw_read ## len(addr); \
	84	*buf++ = x; \
	85	} while (--count); \
	86	} \
	87	afence; \
	88	}
	89
	90	#define __io_writes_outs(port, ctype, len, bfence, afence) \
	91	static inline void __ ## port ## len(volatile void __iomem *addr, \
	92	const void *buffer, \
	93	unsigned int count) \
	94	{ \
	95	bfence; \
	96	if (count) { \
	97	const ctype *buf = buffer; \
	98	\
	99	do { \
da894ff1	100	__raw_write ## len(*buf++, addr); \
fab957c1 PD	101	} while (--count); \
	102	} \
	103	afence; \
	104	}
	105
ce246c44 WD	106	__io_reads_ins(reads, u8, b, __io_br(), __io_ar(addr))
	107	__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
	108	__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
fab957c1 PD	109	#define readsb(addr, buffer, count) __readsb(addr, buffer, count)
	110	#define readsw(addr, buffer, count) __readsw(addr, buffer, count)
	111	#define readsl(addr, buffer, count) __readsl(addr, buffer, count)
	112
ce246c44 WD	113	__io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
	114	__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
	115	__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
fe2726af OJ	116	#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
	117	#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
	118	#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
fab957c1 PD	119
	120	__io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
	121	__io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
	122	__io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
	123	#define writesb(addr, buffer, count) __writesb(addr, buffer, count)
	124	#define writesw(addr, buffer, count) __writesw(addr, buffer, count)
	125	#define writesl(addr, buffer, count) __writesl(addr, buffer, count)
	126
	127	__io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
	128	__io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
	129	__io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
fe2726af OJ	130	#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
	131	#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
	132	#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
fab957c1 PD	133
fab957c1 PD	134	#ifdef CONFIG_64BIT
ce246c44	135	__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
fab957c1 PD	136	#define readsq(addr, buffer, count) __readsq(addr, buffer, count)
fab957c1 PD	137
ce246c44	138	__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
fab957c1 PD	139	#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
	140
	141	__io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
	142	#define writesq(addr, buffer, count) __writesq(addr, buffer, count)
	143
	144	__io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
	145	#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
	146	#endif
	147
	148	#include <asm-generic/io.h>
	149
	150	#endif /* _ASM_RISCV_IO_H */