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50acfb2b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
6d60b6ee PD |
2 | /* |
3 | * Copyright (C) 2012 Regents of the University of California | |
6d60b6ee PD |
4 | */ |
5 | ||
6 | #ifndef _ASM_RISCV_TIMEX_H | |
7 | #define _ASM_RISCV_TIMEX_H | |
8 | ||
2f12dbf1 | 9 | #include <asm/csr.h> |
6d60b6ee PD |
10 | |
11 | typedef unsigned long cycles_t; | |
12 | ||
d5be89a8 PD |
13 | #ifdef CONFIG_RISCV_M_MODE |
14 | ||
15 | #include <asm/clint.h> | |
16 | ||
17 | #ifdef CONFIG_64BIT | |
18 | static inline cycles_t get_cycles(void) | |
19 | { | |
20 | return readq_relaxed(clint_time_val); | |
21 | } | |
22 | #else /* !CONFIG_64BIT */ | |
23 | static inline u32 get_cycles(void) | |
24 | { | |
25 | return readl_relaxed(((u32 *)clint_time_val)); | |
26 | } | |
27 | #define get_cycles get_cycles | |
28 | ||
29 | static inline u32 get_cycles_hi(void) | |
30 | { | |
31 | return readl_relaxed(((u32 *)clint_time_val) + 1); | |
32 | } | |
33 | #define get_cycles_hi get_cycles_hi | |
34 | #endif /* CONFIG_64BIT */ | |
35 | ||
aa988760 AP |
36 | /* |
37 | * Much like MIPS, we may not have a viable counter to use at an early point | |
38 | * in the boot process. Unfortunately we don't have a fallback, so instead | |
39 | * we just return 0. | |
40 | */ | |
41 | static inline unsigned long random_get_entropy(void) | |
42 | { | |
43 | if (unlikely(clint_time_val == NULL)) | |
44 | return 0; | |
45 | return get_cycles(); | |
46 | } | |
47 | #define random_get_entropy() random_get_entropy() | |
48 | ||
d5be89a8 PD |
49 | #else /* CONFIG_RISCV_M_MODE */ |
50 | ||
2f12dbf1 | 51 | static inline cycles_t get_cycles(void) |
6d60b6ee | 52 | { |
2bc3fc87 | 53 | return csr_read(CSR_TIME); |
6d60b6ee | 54 | } |
2f12dbf1 | 55 | #define get_cycles get_cycles |
6d60b6ee | 56 | |
2bc3fc87 AP |
57 | static inline u32 get_cycles_hi(void) |
58 | { | |
59 | return csr_read(CSR_TIMEH); | |
60 | } | |
61 | #define get_cycles_hi get_cycles_hi | |
62 | ||
ccbbfd1c PD |
63 | #endif /* !CONFIG_RISCV_M_MODE */ |
64 | ||
6d60b6ee | 65 | #ifdef CONFIG_64BIT |
2f12dbf1 CH |
66 | static inline u64 get_cycles64(void) |
67 | { | |
68 | return get_cycles(); | |
69 | } | |
70 | #else /* CONFIG_64BIT */ | |
2f12dbf1 | 71 | static inline u64 get_cycles64(void) |
6d60b6ee | 72 | { |
2f12dbf1 CH |
73 | u32 hi, lo; |
74 | ||
75 | do { | |
76 | hi = get_cycles_hi(); | |
77 | lo = get_cycles(); | |
78 | } while (hi != get_cycles_hi()); | |
79 | ||
6d60b6ee PD |
80 | return ((u64)hi << 32) | lo; |
81 | } | |
2f12dbf1 | 82 | #endif /* CONFIG_64BIT */ |
6d60b6ee PD |
83 | |
84 | #define ARCH_HAS_READ_CURRENT_TIMER | |
6d60b6ee PD |
85 | static inline int read_current_timer(unsigned long *timer_val) |
86 | { | |
87 | *timer_val = get_cycles(); | |
88 | return 0; | |
89 | } | |
90 | ||
db2a8f92 NS |
91 | extern void time_init(void); |
92 | ||
6d60b6ee | 93 | #endif /* _ASM_RISCV_TIMEX_H */ |