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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 | 14 | /* |
a1c843b8 MS |
15 | * The Linux memory management assumes a three-level page table setup. |
16 | * For s390 64 bit we use up to four of the five levels the hardware | |
17 | * provides (region first tables are not used). | |
1da177e4 LT |
18 | * |
19 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
20 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
21 | * into the pgd entry) | |
22 | * | |
23 | * This file contains the functions and defines necessary to modify and use | |
24 | * the S390 page table tree. | |
25 | */ | |
26 | #ifndef __ASSEMBLY__ | |
9789db08 | 27 | #include <linux/sched.h> |
2dcea57a | 28 | #include <linux/mm_types.h> |
abf09bed | 29 | #include <linux/page-flags.h> |
527e30b4 | 30 | #include <linux/radix-tree.h> |
37cd944c | 31 | #include <linux/atomic.h> |
1da177e4 | 32 | #include <asm/bug.h> |
b2fa47e6 | 33 | #include <asm/page.h> |
1da177e4 | 34 | |
0ccb32c9 | 35 | extern pgd_t swapper_pg_dir[]; |
1da177e4 | 36 | extern void paging_init(void); |
2b67fc46 | 37 | extern void vmem_map_init(void); |
e8a97e42 HC |
38 | pmd_t *vmem_pmd_alloc(void); |
39 | pte_t *vmem_pte_alloc(void); | |
1da177e4 | 40 | |
37cd944c HC |
41 | enum { |
42 | PG_DIRECT_MAP_4K = 0, | |
43 | PG_DIRECT_MAP_1M, | |
44 | PG_DIRECT_MAP_2G, | |
45 | PG_DIRECT_MAP_MAX | |
46 | }; | |
47 | ||
48 | extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; | |
49 | ||
50 | static inline void update_page_count(int level, long count) | |
51 | { | |
52 | if (IS_ENABLED(CONFIG_PROC_FS)) | |
53 | atomic_long_add(count, &direct_pages_count[level]); | |
54 | } | |
55 | ||
56 | struct seq_file; | |
57 | void arch_report_meminfo(struct seq_file *m); | |
58 | ||
1da177e4 LT |
59 | /* |
60 | * The S390 doesn't have any external MMU info: the kernel page | |
61 | * tables contain all the necessary information. | |
62 | */ | |
4b3073e1 | 63 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 64 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
65 | |
66 | /* | |
238ec4ef | 67 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
68 | * for zero-mapped memory areas etc.. |
69 | */ | |
238ec4ef MS |
70 | |
71 | extern unsigned long empty_zero_page; | |
72 | extern unsigned long zero_page_mask; | |
73 | ||
74 | #define ZERO_PAGE(vaddr) \ | |
75 | (virt_to_page((void *)(empty_zero_page + \ | |
76 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 77 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 78 | |
4f2e2903 | 79 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
80 | #endif /* !__ASSEMBLY__ */ |
81 | ||
82 | /* | |
83 | * PMD_SHIFT determines the size of the area a second-level page | |
84 | * table can map | |
85 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
86 | */ | |
5a79859a HC |
87 | #define PMD_SHIFT 20 |
88 | #define PUD_SHIFT 31 | |
1aea9b3f MS |
89 | #define P4D_SHIFT 42 |
90 | #define PGDIR_SHIFT 53 | |
1da177e4 LT |
91 | |
92 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
93 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
94 | #define PUD_SIZE (1UL << PUD_SHIFT) |
95 | #define PUD_MASK (~(PUD_SIZE-1)) | |
1aea9b3f MS |
96 | #define P4D_SIZE (1UL << P4D_SHIFT) |
97 | #define P4D_MASK (~(P4D_SIZE-1)) | |
5a216a20 MS |
98 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
99 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
100 | |
101 | /* | |
102 | * entries per page directory level: the S390 is two-level, so | |
103 | * we don't really have any PMD directory physically. | |
104 | * for S390 segment-table entries are combined to one PGD | |
105 | * that leads to 1024 pte per pgd | |
106 | */ | |
146e4b3c | 107 | #define PTRS_PER_PTE 256 |
146e4b3c | 108 | #define PTRS_PER_PMD 2048 |
5a216a20 | 109 | #define PTRS_PER_PUD 2048 |
1aea9b3f | 110 | #define PTRS_PER_P4D 2048 |
146e4b3c | 111 | #define PTRS_PER_PGD 2048 |
1da177e4 | 112 | |
d016bf7e | 113 | #define FIRST_USER_ADDRESS 0UL |
d455a369 | 114 | |
1da177e4 LT |
115 | #define pte_ERROR(e) \ |
116 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
117 | #define pmd_ERROR(e) \ | |
118 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
119 | #define pud_ERROR(e) \ |
120 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1aea9b3f MS |
121 | #define p4d_ERROR(e) \ |
122 | printk("%s:%d: bad p4d %p.\n", __FILE__, __LINE__, (void *) p4d_val(e)) | |
1da177e4 LT |
123 | #define pgd_ERROR(e) \ |
124 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
125 | ||
126 | #ifndef __ASSEMBLY__ | |
127 | /* | |
a1c843b8 MS |
128 | * The vmalloc and module area will always be on the topmost area of the |
129 | * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. | |
c972cc60 HC |
130 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where |
131 | * modules will reside. That makes sure that inter module branches always | |
132 | * happen without trampolines and in addition the placement within a 2GB frame | |
133 | * is branch prediction unit friendly. | |
8b62bc96 | 134 | */ |
239a6425 | 135 | extern unsigned long VMALLOC_START; |
14045ebf MS |
136 | extern unsigned long VMALLOC_END; |
137 | extern struct page *vmemmap; | |
239a6425 | 138 | |
14045ebf | 139 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 140 | |
c972cc60 HC |
141 | extern unsigned long MODULES_VADDR; |
142 | extern unsigned long MODULES_END; | |
143 | #define MODULES_VADDR MODULES_VADDR | |
144 | #define MODULES_END MODULES_END | |
145 | #define MODULES_LEN (1UL << 31) | |
c972cc60 | 146 | |
c933146a HC |
147 | static inline int is_module_addr(void *addr) |
148 | { | |
c933146a HC |
149 | BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); |
150 | if (addr < (void *)MODULES_VADDR) | |
151 | return 0; | |
152 | if (addr > (void *)MODULES_END) | |
153 | return 0; | |
c933146a HC |
154 | return 1; |
155 | } | |
156 | ||
1da177e4 | 157 | /* |
1da177e4 | 158 | * A 64 bit pagetable entry of S390 has following format: |
6a985c61 | 159 | * | PFRA |0IPC| OS | |
1da177e4 LT |
160 | * 0000000000111111111122222222223333333333444444444455555555556666 |
161 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
162 | * | |
163 | * I Page-Invalid Bit: Page is not available for address-translation | |
164 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 165 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
166 | * |
167 | * A 64 bit segmenttable entry of S390 has following format: | |
168 | * | P-table origin | TT | |
169 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
170 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
171 | * | |
172 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
173 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
174 | * P Page-Protection Bit: Store access not possible for page | |
175 | * TT Type 00 | |
176 | * | |
177 | * A 64 bit region table entry of S390 has following format: | |
178 | * | S-table origin | TF TTTL | |
179 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
180 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
181 | * | |
182 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
183 | * TT Type 01 | |
184 | * TF | |
190a1d72 | 185 | * TL Table length |
1da177e4 LT |
186 | * |
187 | * The 64 bit regiontable origin of S390 has following format: | |
188 | * | region table origon | DTTL | |
189 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
190 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
191 | * | |
192 | * X Space-Switch event: | |
193 | * G Segment-Invalid Bit: | |
194 | * P Private-Space Bit: | |
195 | * S Storage-Alteration: | |
196 | * R Real space | |
197 | * TL Table-Length: | |
198 | * | |
199 | * A storage key has the following format: | |
200 | * | ACC |F|R|C|0| | |
201 | * 0 3 4 5 6 7 | |
202 | * ACC: access key | |
203 | * F : fetch protection bit | |
204 | * R : referenced bit | |
205 | * C : changed bit | |
206 | */ | |
207 | ||
208 | /* Hardware bits in the page table entry */ | |
57d7f939 | 209 | #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ |
e5098611 | 210 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 211 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 212 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
213 | |
214 | /* Software bits in the page table entry */ | |
e5098611 | 215 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
e5098611 MS |
216 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ |
217 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
218 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
219 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
220 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 221 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 222 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 223 | |
5614dd92 MS |
224 | #ifdef CONFIG_MEM_SOFT_DIRTY |
225 | #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ | |
226 | #else | |
227 | #define _PAGE_SOFT_DIRTY 0x000 | |
228 | #endif | |
229 | ||
138c9021 | 230 | /* Set of bits not changed in pte_modify */ |
6a5c1482 | 231 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ |
5614dd92 | 232 | _PAGE_YOUNG | _PAGE_SOFT_DIRTY) |
53492b1d | 233 | |
83377484 | 234 | /* |
6e76d4b2 KS |
235 | * handle_pte_fault uses pte_present and pte_none to find out the pte type |
236 | * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to | |
237 | * distinguish present from not-present ptes. It is changed only with the page | |
238 | * table lock held. | |
83377484 | 239 | * |
e5098611 | 240 | * The following table gives the different possible bit combinations for |
a1c843b8 MS |
241 | * the pte hardware and software bits in the last 12 bits of a pte |
242 | * (. unassigned bit, x don't care, t swap type): | |
83377484 | 243 | * |
0944fe3f MS |
244 | * 842100000000 |
245 | * 000084210000 | |
246 | * 000000008421 | |
a1c843b8 MS |
247 | * .IR.uswrdy.p |
248 | * empty .10.00000000 | |
249 | * swap .11..ttttt.0 | |
250 | * prot-none, clean, old .11.xx0000.1 | |
251 | * prot-none, clean, young .11.xx0001.1 | |
bc29b7ac GS |
252 | * prot-none, dirty, old .11.xx0010.1 |
253 | * prot-none, dirty, young .11.xx0011.1 | |
a1c843b8 MS |
254 | * read-only, clean, old .11.xx0100.1 |
255 | * read-only, clean, young .01.xx0101.1 | |
256 | * read-only, dirty, old .11.xx0110.1 | |
257 | * read-only, dirty, young .01.xx0111.1 | |
258 | * read-write, clean, old .11.xx1100.1 | |
259 | * read-write, clean, young .01.xx1101.1 | |
260 | * read-write, dirty, old .10.xx1110.1 | |
261 | * read-write, dirty, young .00.xx1111.1 | |
262 | * HW-bits: R read-only, I invalid | |
263 | * SW-bits: p present, y young, d dirty, r read, w write, s special, | |
264 | * u unused, l large | |
e5098611 | 265 | * |
a1c843b8 MS |
266 | * pte_none is true for the bit pattern .10.00000000, pte == 0x400 |
267 | * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 | |
268 | * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 | |
83377484 MS |
269 | */ |
270 | ||
3610cce8 MS |
271 | /* Bits in the segment/region table address-space-control-element */ |
272 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
273 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
274 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
275 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
276 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
277 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
278 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
279 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
280 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
281 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
282 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
283 | ||
284 | /* Bits in the region table entry */ | |
285 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 | 286 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
57d7f939 | 287 | #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ |
4be130a0 | 288 | #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ |
e5098611 | 289 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ |
3610cce8 MS |
290 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
291 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
292 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
293 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
294 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
295 | ||
296 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 297 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 298 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 299 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 300 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 301 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 302 | |
9e20b4da | 303 | #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ |
2dffdcba HC |
304 | #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ |
305 | #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ | |
306 | #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ | |
307 | #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ | |
308 | #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ | |
309 | ||
310 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
311 | #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ | |
312 | #else | |
313 | #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ | |
314 | #endif | |
315 | ||
1aea9b3f MS |
316 | #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL |
317 | #define _REGION_ENTRY_BITS_LARGE 0xffffffff8000fe2fUL | |
d08de8e2 | 318 | |
1da177e4 | 319 | /* Bits in the segment table entry */ |
0944fe3f | 320 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 321 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 322 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 | 323 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
e5098611 | 324 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
57d7f939 | 325 | #define _SEGMENT_ENTRY_NOEXEC 0x100 /* region no-execute bit */ |
e5098611 | 326 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ |
1da177e4 | 327 | |
3610cce8 | 328 | #define _SEGMENT_ENTRY (0) |
e5098611 | 329 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 330 | |
152125b7 MS |
331 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
332 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
152125b7 | 333 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ |
bc29b7ac GS |
334 | #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ |
335 | #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ | |
0944fe3f | 336 | |
5614dd92 MS |
337 | #ifdef CONFIG_MEM_SOFT_DIRTY |
338 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ | |
339 | #else | |
340 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ | |
341 | #endif | |
342 | ||
0944fe3f | 343 | /* |
2dffdcba HC |
344 | * Segment table and region3 table entry encoding |
345 | * (R = read-only, I = invalid, y = young bit): | |
bc29b7ac | 346 | * dy..R...I...wr |
152125b7 MS |
347 | * prot-none, clean, old 00..1...1...00 |
348 | * prot-none, clean, young 01..1...1...00 | |
349 | * prot-none, dirty, old 10..1...1...00 | |
350 | * prot-none, dirty, young 11..1...1...00 | |
bc29b7ac GS |
351 | * read-only, clean, old 00..1...1...01 |
352 | * read-only, clean, young 01..1...0...01 | |
353 | * read-only, dirty, old 10..1...1...01 | |
354 | * read-only, dirty, young 11..1...0...01 | |
152125b7 MS |
355 | * read-write, clean, old 00..1...1...11 |
356 | * read-write, clean, young 01..1...0...11 | |
357 | * read-write, dirty, old 10..0...1...11 | |
358 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
359 | * The segment table origin is used to distinguish empty (origin==0) from |
360 | * read-write, old segment table entries (origin!=0) | |
a1c843b8 MS |
361 | * HW-bits: R read-only, I invalid |
362 | * SW-bits: y young, d dirty, r read, w write | |
0944fe3f | 363 | */ |
e5098611 | 364 | |
6c61cfe9 | 365 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
366 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
367 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
368 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
369 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
370 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
371 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
372 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
373 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
374 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
4be130a0 | 375 | #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ |
6c61cfe9 | 376 | |
b31288fa | 377 | /* Guest Page State used for virtualization */ |
2d42f947 CI |
378 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL |
379 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL | |
380 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
381 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
382 | #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL | |
383 | #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK | |
b31288fa | 384 | |
1da177e4 | 385 | /* |
3610cce8 MS |
386 | * A user page table pointer has the space-switch-event bit, the |
387 | * private-space-control bit and the storage-alteration-event-control | |
388 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 389 | */ |
3610cce8 MS |
390 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
391 | _ASCE_ALT_EVENT) | |
1da177e4 | 392 | |
1da177e4 | 393 | /* |
9282ed92 | 394 | * Page protection definitions. |
1da177e4 | 395 | */ |
bc29b7ac | 396 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) |
57d7f939 MS |
397 | #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
398 | _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) | |
399 | #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ | |
0944fe3f | 400 | _PAGE_INVALID | _PAGE_PROTECT) |
57d7f939 MS |
401 | #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
402 | _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) | |
403 | #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
0944fe3f MS |
404 | _PAGE_INVALID | _PAGE_PROTECT) |
405 | ||
406 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
57d7f939 | 407 | _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) |
0944fe3f | 408 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
57d7f939 | 409 | _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) |
0944fe3f | 410 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ |
57d7f939 MS |
411 | _PAGE_PROTECT | _PAGE_NOEXEC) |
412 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
413 | _PAGE_YOUNG | _PAGE_DIRTY) | |
1da177e4 LT |
414 | |
415 | /* | |
043d0708 MS |
416 | * On s390 the page table entry has an invalid bit and a read-only bit. |
417 | * Read permission implies execute permission and write permission | |
418 | * implies read permission. | |
1da177e4 LT |
419 | */ |
420 | /*xwr*/ | |
9282ed92 | 421 | #define __P000 PAGE_NONE |
57d7f939 MS |
422 | #define __P001 PAGE_RO |
423 | #define __P010 PAGE_RO | |
424 | #define __P011 PAGE_RO | |
425 | #define __P100 PAGE_RX | |
426 | #define __P101 PAGE_RX | |
427 | #define __P110 PAGE_RX | |
428 | #define __P111 PAGE_RX | |
9282ed92 GS |
429 | |
430 | #define __S000 PAGE_NONE | |
57d7f939 MS |
431 | #define __S001 PAGE_RO |
432 | #define __S010 PAGE_RW | |
433 | #define __S011 PAGE_RW | |
434 | #define __S100 PAGE_RX | |
435 | #define __S101 PAGE_RX | |
436 | #define __S110 PAGE_RWX | |
437 | #define __S111 PAGE_RWX | |
1da177e4 | 438 | |
106c992a GS |
439 | /* |
440 | * Segment entry (large page) protection definitions. | |
441 | */ | |
e5098611 MS |
442 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
443 | _SEGMENT_ENTRY_PROTECT) | |
57d7f939 MS |
444 | #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
445 | _SEGMENT_ENTRY_READ | \ | |
446 | _SEGMENT_ENTRY_NOEXEC) | |
447 | #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ | |
152125b7 | 448 | _SEGMENT_ENTRY_READ) |
57d7f939 MS |
449 | #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ |
450 | _SEGMENT_ENTRY_WRITE | \ | |
451 | _SEGMENT_ENTRY_NOEXEC) | |
452 | #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ | |
152125b7 | 453 | _SEGMENT_ENTRY_WRITE) |
2dffdcba HC |
454 | #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ |
455 | _SEGMENT_ENTRY_LARGE | \ | |
456 | _SEGMENT_ENTRY_READ | \ | |
457 | _SEGMENT_ENTRY_WRITE | \ | |
458 | _SEGMENT_ENTRY_YOUNG | \ | |
57d7f939 MS |
459 | _SEGMENT_ENTRY_DIRTY | \ |
460 | _SEGMENT_ENTRY_NOEXEC) | |
2dffdcba HC |
461 | #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ |
462 | _SEGMENT_ENTRY_LARGE | \ | |
463 | _SEGMENT_ENTRY_READ | \ | |
464 | _SEGMENT_ENTRY_YOUNG | \ | |
57d7f939 MS |
465 | _SEGMENT_ENTRY_PROTECT | \ |
466 | _SEGMENT_ENTRY_NOEXEC) | |
2dffdcba HC |
467 | |
468 | /* | |
469 | * Region3 entry (large page) protection definitions. | |
470 | */ | |
471 | ||
472 | #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ | |
473 | _REGION3_ENTRY_LARGE | \ | |
474 | _REGION3_ENTRY_READ | \ | |
475 | _REGION3_ENTRY_WRITE | \ | |
476 | _REGION3_ENTRY_YOUNG | \ | |
57d7f939 MS |
477 | _REGION3_ENTRY_DIRTY | \ |
478 | _REGION_ENTRY_NOEXEC) | |
2dffdcba HC |
479 | #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ |
480 | _REGION3_ENTRY_LARGE | \ | |
481 | _REGION3_ENTRY_READ | \ | |
482 | _REGION3_ENTRY_YOUNG | \ | |
57d7f939 MS |
483 | _REGION_ENTRY_PROTECT | \ |
484 | _REGION_ENTRY_NOEXEC) | |
106c992a | 485 | |
b2fa47e6 MS |
486 | static inline int mm_has_pgste(struct mm_struct *mm) |
487 | { | |
488 | #ifdef CONFIG_PGSTE | |
489 | if (unlikely(mm->context.has_pgste)) | |
490 | return 1; | |
491 | #endif | |
492 | return 0; | |
493 | } | |
65eef335 | 494 | |
0b46e0a3 MS |
495 | static inline int mm_alloc_pgste(struct mm_struct *mm) |
496 | { | |
497 | #ifdef CONFIG_PGSTE | |
498 | if (unlikely(mm->context.alloc_pgste)) | |
499 | return 1; | |
500 | #endif | |
501 | return 0; | |
502 | } | |
503 | ||
2faee8ff DD |
504 | /* |
505 | * In the case that a guest uses storage keys | |
506 | * faults should no longer be backed by zero pages | |
507 | */ | |
508 | #define mm_forbids_zeropage mm_use_skey | |
65eef335 DD |
509 | static inline int mm_use_skey(struct mm_struct *mm) |
510 | { | |
511 | #ifdef CONFIG_PGSTE | |
512 | if (mm->context.use_skey) | |
513 | return 1; | |
514 | #endif | |
515 | return 0; | |
516 | } | |
517 | ||
4ccccc52 HC |
518 | static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) |
519 | { | |
520 | register unsigned long reg2 asm("2") = old; | |
521 | register unsigned long reg3 asm("3") = new; | |
522 | unsigned long address = (unsigned long)ptr | 1; | |
523 | ||
524 | asm volatile( | |
525 | " csp %0,%3" | |
526 | : "+d" (reg2), "+m" (*ptr) | |
527 | : "d" (reg3), "d" (address) | |
528 | : "cc"); | |
529 | } | |
530 | ||
e8a97e42 HC |
531 | static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) |
532 | { | |
533 | register unsigned long reg2 asm("2") = old; | |
534 | register unsigned long reg3 asm("3") = new; | |
535 | unsigned long address = (unsigned long)ptr | 1; | |
536 | ||
537 | asm volatile( | |
538 | " .insn rre,0xb98a0000,%0,%3" | |
539 | : "+d" (reg2), "+m" (*ptr) | |
540 | : "d" (reg3), "d" (address) | |
541 | : "cc"); | |
542 | } | |
543 | ||
544 | #define CRDTE_DTT_PAGE 0x00UL | |
545 | #define CRDTE_DTT_SEGMENT 0x10UL | |
546 | #define CRDTE_DTT_REGION3 0x14UL | |
547 | #define CRDTE_DTT_REGION2 0x18UL | |
548 | #define CRDTE_DTT_REGION1 0x1cUL | |
549 | ||
550 | static inline void crdte(unsigned long old, unsigned long new, | |
551 | unsigned long table, unsigned long dtt, | |
552 | unsigned long address, unsigned long asce) | |
553 | { | |
554 | register unsigned long reg2 asm("2") = old; | |
555 | register unsigned long reg3 asm("3") = new; | |
556 | register unsigned long reg4 asm("4") = table | dtt; | |
557 | register unsigned long reg5 asm("5") = address; | |
558 | ||
559 | asm volatile(".insn rrf,0xb98f0000,%0,%2,%4,0" | |
560 | : "+d" (reg2) | |
561 | : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce) | |
562 | : "memory", "cc"); | |
563 | } | |
564 | ||
1da177e4 | 565 | /* |
cc18b460 | 566 | * pgd/p4d/pud/pmd/pte query functions |
1da177e4 | 567 | */ |
cc18b460 HC |
568 | static inline int pgd_folded(pgd_t pgd) |
569 | { | |
570 | return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; | |
571 | } | |
572 | ||
5a216a20 MS |
573 | static inline int pgd_present(pgd_t pgd) |
574 | { | |
cc18b460 | 575 | if (pgd_folded(pgd)) |
6252d702 | 576 | return 1; |
5a216a20 MS |
577 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
578 | } | |
579 | ||
580 | static inline int pgd_none(pgd_t pgd) | |
581 | { | |
cc18b460 | 582 | if (pgd_folded(pgd)) |
6252d702 | 583 | return 0; |
e5098611 | 584 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
585 | } |
586 | ||
587 | static inline int pgd_bad(pgd_t pgd) | |
588 | { | |
6252d702 MS |
589 | /* |
590 | * With dynamic page table levels the pgd can be a region table | |
591 | * entry or a segment table entry. Check for the bit that are | |
592 | * invalid for either table entry. | |
593 | */ | |
5a216a20 | 594 | unsigned long mask = |
e5098611 | 595 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
596 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
597 | return (pgd_val(pgd) & mask) != 0; | |
598 | } | |
190a1d72 | 599 | |
cc18b460 HC |
600 | static inline int p4d_folded(p4d_t p4d) |
601 | { | |
602 | return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; | |
603 | } | |
604 | ||
1aea9b3f MS |
605 | static inline int p4d_present(p4d_t p4d) |
606 | { | |
cc18b460 | 607 | if (p4d_folded(p4d)) |
1aea9b3f MS |
608 | return 1; |
609 | return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; | |
610 | } | |
611 | ||
612 | static inline int p4d_none(p4d_t p4d) | |
613 | { | |
cc18b460 | 614 | if (p4d_folded(p4d)) |
1aea9b3f MS |
615 | return 0; |
616 | return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; | |
617 | } | |
618 | ||
619 | static inline unsigned long p4d_pfn(p4d_t p4d) | |
620 | { | |
621 | unsigned long origin_mask; | |
622 | ||
623 | origin_mask = _REGION_ENTRY_ORIGIN; | |
624 | return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; | |
625 | } | |
626 | ||
cc18b460 HC |
627 | static inline int pud_folded(pud_t pud) |
628 | { | |
629 | return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; | |
630 | } | |
631 | ||
190a1d72 | 632 | static inline int pud_present(pud_t pud) |
1da177e4 | 633 | { |
cc18b460 | 634 | if (pud_folded(pud)) |
6252d702 | 635 | return 1; |
0d017923 | 636 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
637 | } |
638 | ||
190a1d72 | 639 | static inline int pud_none(pud_t pud) |
1da177e4 | 640 | { |
cc18b460 | 641 | if (pud_folded(pud)) |
6252d702 | 642 | return 0; |
d08de8e2 | 643 | return pud_val(pud) == _REGION3_ENTRY_EMPTY; |
1da177e4 LT |
644 | } |
645 | ||
18da2369 HC |
646 | static inline int pud_large(pud_t pud) |
647 | { | |
648 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
649 | return 0; | |
650 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
651 | } | |
652 | ||
9e20b4da HC |
653 | static inline unsigned long pud_pfn(pud_t pud) |
654 | { | |
655 | unsigned long origin_mask; | |
656 | ||
f96c6f72 | 657 | origin_mask = _REGION_ENTRY_ORIGIN; |
9e20b4da HC |
658 | if (pud_large(pud)) |
659 | origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; | |
660 | return (pud_val(pud) & origin_mask) >> PAGE_SHIFT; | |
661 | } | |
662 | ||
d08de8e2 GS |
663 | static inline int pmd_large(pmd_t pmd) |
664 | { | |
665 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; | |
666 | } | |
667 | ||
668 | static inline int pmd_bad(pmd_t pmd) | |
669 | { | |
670 | if (pmd_large(pmd)) | |
671 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
672 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; | |
673 | } | |
674 | ||
190a1d72 | 675 | static inline int pud_bad(pud_t pud) |
1da177e4 | 676 | { |
d08de8e2 GS |
677 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
678 | return pmd_bad(__pmd(pud_val(pud))); | |
679 | if (pud_large(pud)) | |
680 | return (pud_val(pud) & ~_REGION_ENTRY_BITS_LARGE) != 0; | |
681 | return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; | |
1da177e4 LT |
682 | } |
683 | ||
1aea9b3f MS |
684 | static inline int p4d_bad(p4d_t p4d) |
685 | { | |
686 | if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) | |
687 | return pud_bad(__pud(p4d_val(p4d))); | |
688 | return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; | |
689 | } | |
690 | ||
4448aaf0 | 691 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 692 | { |
54397bb0 | 693 | return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
694 | } |
695 | ||
4448aaf0 | 696 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 697 | { |
54397bb0 | 698 | return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
699 | } |
700 | ||
7cded342 | 701 | static inline unsigned long pmd_pfn(pmd_t pmd) |
0944fe3f | 702 | { |
152125b7 MS |
703 | unsigned long origin_mask; |
704 | ||
705 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
706 | if (pmd_large(pmd)) | |
707 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
708 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
709 | } |
710 | ||
1ae1c1d0 GS |
711 | #define __HAVE_ARCH_PMD_WRITE |
712 | static inline int pmd_write(pmd_t pmd) | |
713 | { | |
152125b7 MS |
714 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
715 | } | |
716 | ||
717 | static inline int pmd_dirty(pmd_t pmd) | |
718 | { | |
719 | int dirty = 1; | |
720 | if (pmd_large(pmd)) | |
721 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
722 | return dirty; | |
1ae1c1d0 GS |
723 | } |
724 | ||
725 | static inline int pmd_young(pmd_t pmd) | |
726 | { | |
152125b7 MS |
727 | int young = 1; |
728 | if (pmd_large(pmd)) | |
0944fe3f | 729 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 730 | return young; |
1ae1c1d0 GS |
731 | } |
732 | ||
e5098611 | 733 | static inline int pte_present(pte_t pte) |
1da177e4 | 734 | { |
e5098611 MS |
735 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
736 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
737 | } |
738 | ||
e5098611 | 739 | static inline int pte_none(pte_t pte) |
1da177e4 | 740 | { |
e5098611 MS |
741 | /* Bit pattern: pte == 0x400 */ |
742 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
743 | } |
744 | ||
b31288fa KW |
745 | static inline int pte_swap(pte_t pte) |
746 | { | |
a1c843b8 MS |
747 | /* Bit pattern: (pte & 0x201) == 0x200 */ |
748 | return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) | |
749 | == _PAGE_PROTECT; | |
b31288fa KW |
750 | } |
751 | ||
7e675137 NP |
752 | static inline int pte_special(pte_t pte) |
753 | { | |
a08cb629 | 754 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
755 | } |
756 | ||
ba8a9229 | 757 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
758 | static inline int pte_same(pte_t a, pte_t b) |
759 | { | |
760 | return pte_val(a) == pte_val(b); | |
761 | } | |
1da177e4 | 762 | |
b54565b8 MS |
763 | #ifdef CONFIG_NUMA_BALANCING |
764 | static inline int pte_protnone(pte_t pte) | |
765 | { | |
766 | return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); | |
767 | } | |
768 | ||
769 | static inline int pmd_protnone(pmd_t pmd) | |
770 | { | |
771 | /* pmd_large(pmd) implies pmd_present(pmd) */ | |
772 | return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); | |
773 | } | |
774 | #endif | |
775 | ||
5614dd92 MS |
776 | static inline int pte_soft_dirty(pte_t pte) |
777 | { | |
778 | return pte_val(pte) & _PAGE_SOFT_DIRTY; | |
779 | } | |
780 | #define pte_swp_soft_dirty pte_soft_dirty | |
781 | ||
782 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
783 | { | |
784 | pte_val(pte) |= _PAGE_SOFT_DIRTY; | |
785 | return pte; | |
786 | } | |
787 | #define pte_swp_mksoft_dirty pte_mksoft_dirty | |
788 | ||
789 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
790 | { | |
791 | pte_val(pte) &= ~_PAGE_SOFT_DIRTY; | |
792 | return pte; | |
793 | } | |
794 | #define pte_swp_clear_soft_dirty pte_clear_soft_dirty | |
795 | ||
796 | static inline int pmd_soft_dirty(pmd_t pmd) | |
797 | { | |
798 | return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; | |
799 | } | |
800 | ||
801 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
802 | { | |
803 | pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; | |
804 | return pmd; | |
805 | } | |
806 | ||
807 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
808 | { | |
809 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; | |
810 | return pmd; | |
811 | } | |
812 | ||
1da177e4 LT |
813 | /* |
814 | * query functions pte_write/pte_dirty/pte_young only work if | |
815 | * pte_present() is true. Undefined behaviour if not.. | |
816 | */ | |
4448aaf0 | 817 | static inline int pte_write(pte_t pte) |
1da177e4 | 818 | { |
e5098611 | 819 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
820 | } |
821 | ||
4448aaf0 | 822 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 823 | { |
e5098611 | 824 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
825 | } |
826 | ||
4448aaf0 | 827 | static inline int pte_young(pte_t pte) |
1da177e4 | 828 | { |
0944fe3f | 829 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
830 | } |
831 | ||
b31288fa KW |
832 | #define __HAVE_ARCH_PTE_UNUSED |
833 | static inline int pte_unused(pte_t pte) | |
834 | { | |
835 | return pte_val(pte) & _PAGE_UNUSED; | |
836 | } | |
837 | ||
1da177e4 LT |
838 | /* |
839 | * pgd/pmd/pte modification functions | |
840 | */ | |
841 | ||
b2fa47e6 | 842 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 843 | { |
1aea9b3f MS |
844 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) |
845 | pgd_val(*pgd) = _REGION1_ENTRY_EMPTY; | |
846 | } | |
847 | ||
848 | static inline void p4d_clear(p4d_t *p4d) | |
849 | { | |
850 | if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
851 | p4d_val(*p4d) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
852 | } |
853 | ||
b2fa47e6 | 854 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 855 | { |
6252d702 MS |
856 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
857 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
858 | } |
859 | ||
b2fa47e6 | 860 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 861 | { |
54397bb0 | 862 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
863 | } |
864 | ||
4448aaf0 | 865 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 866 | { |
e5098611 | 867 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
868 | } |
869 | ||
870 | /* | |
871 | * The following pte modification functions only work if | |
872 | * pte_present() is true. Undefined behaviour if not.. | |
873 | */ | |
4448aaf0 | 874 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 875 | { |
138c9021 | 876 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 877 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f | 878 | /* |
57d7f939 MS |
879 | * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX |
880 | * has the invalid bit set, clear it again for readable, young pages | |
0944fe3f MS |
881 | */ |
882 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
883 | pte_val(pte) &= ~_PAGE_INVALID; | |
884 | /* | |
57d7f939 MS |
885 | * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page |
886 | * protection bit set, clear it again for writable, dirty pages | |
0944fe3f | 887 | */ |
e5098611 MS |
888 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
889 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
890 | return pte; |
891 | } | |
892 | ||
4448aaf0 | 893 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 894 | { |
e5098611 MS |
895 | pte_val(pte) &= ~_PAGE_WRITE; |
896 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
897 | return pte; |
898 | } | |
899 | ||
4448aaf0 | 900 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 901 | { |
e5098611 MS |
902 | pte_val(pte) |= _PAGE_WRITE; |
903 | if (pte_val(pte) & _PAGE_DIRTY) | |
904 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
905 | return pte; |
906 | } | |
907 | ||
4448aaf0 | 908 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 909 | { |
e5098611 MS |
910 | pte_val(pte) &= ~_PAGE_DIRTY; |
911 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
912 | return pte; |
913 | } | |
914 | ||
4448aaf0 | 915 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 916 | { |
5614dd92 | 917 | pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; |
e5098611 MS |
918 | if (pte_val(pte) & _PAGE_WRITE) |
919 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
920 | return pte; |
921 | } | |
922 | ||
4448aaf0 | 923 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 924 | { |
e5098611 | 925 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 926 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
927 | return pte; |
928 | } | |
929 | ||
4448aaf0 | 930 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 931 | { |
0944fe3f MS |
932 | pte_val(pte) |= _PAGE_YOUNG; |
933 | if (pte_val(pte) & _PAGE_READ) | |
934 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
935 | return pte; |
936 | } | |
937 | ||
7e675137 NP |
938 | static inline pte_t pte_mkspecial(pte_t pte) |
939 | { | |
a08cb629 | 940 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
941 | return pte; |
942 | } | |
943 | ||
84afdcee HC |
944 | #ifdef CONFIG_HUGETLB_PAGE |
945 | static inline pte_t pte_mkhuge(pte_t pte) | |
946 | { | |
e5098611 | 947 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
948 | return pte; |
949 | } | |
950 | #endif | |
951 | ||
34eeaf37 MS |
952 | #define IPTE_GLOBAL 0 |
953 | #define IPTE_LOCAL 1 | |
53e857f3 | 954 | |
118bd31b | 955 | #define IPTE_NODAT 0x400 |
28c807e5 | 956 | #define IPTE_GUEST_ASCE 0x800 |
118bd31b MS |
957 | |
958 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep, | |
28c807e5 MS |
959 | unsigned long opt, unsigned long asce, |
960 | int local) | |
1b948d6c MS |
961 | { |
962 | unsigned long pto = (unsigned long) ptep; | |
963 | ||
118bd31b MS |
964 | if (__builtin_constant_p(opt) && opt == 0) { |
965 | /* Invalidation + TLB flush for the pte */ | |
966 | asm volatile( | |
967 | " .insn rrf,0xb2210000,%[r1],%[r2],0,%[m4]" | |
968 | : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), | |
969 | [m4] "i" (local)); | |
970 | return; | |
971 | } | |
972 | ||
973 | /* Invalidate ptes with options + TLB flush of the ptes */ | |
28c807e5 | 974 | opt = opt | (asce & _ASCE_ORIGIN); |
1b948d6c | 975 | asm volatile( |
118bd31b MS |
976 | " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" |
977 | : [r2] "+a" (address), [r3] "+a" (opt) | |
978 | : [r1] "a" (pto), [m4] "i" (local) : "memory"); | |
1b948d6c MS |
979 | } |
980 | ||
34eeaf37 MS |
981 | static inline void __ptep_ipte_range(unsigned long address, int nr, |
982 | pte_t *ptep, int local) | |
cfb0b241 HC |
983 | { |
984 | unsigned long pto = (unsigned long) ptep; | |
985 | ||
34eeaf37 | 986 | /* Invalidate a range of ptes + TLB flush of the ptes */ |
cfb0b241 HC |
987 | do { |
988 | asm volatile( | |
34eeaf37 MS |
989 | " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" |
990 | : [r2] "+a" (address), [r3] "+a" (nr) | |
991 | : [r1] "a" (pto), [m4] "i" (local) : "memory"); | |
cfb0b241 HC |
992 | } while (nr != 255); |
993 | } | |
994 | ||
0a61b222 | 995 | /* |
ebde765c MS |
996 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush |
997 | * both clear the TLB for the unmapped pte. The reason is that | |
998 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
999 | * to modify an active pte. The sequence is | |
1000 | * 1) ptep_get_and_clear | |
1001 | * 2) set_pte_at | |
1002 | * 3) flush_tlb_range | |
1003 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1004 | * if the pte is active. The only way how this can be implemented is to | |
1005 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1006 | * is a nop. | |
0a61b222 | 1007 | */ |
ebde765c MS |
1008 | pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); |
1009 | pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); | |
0a61b222 | 1010 | |
0944fe3f MS |
1011 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1012 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1013 | unsigned long addr, pte_t *ptep) | |
1014 | { | |
ebde765c | 1015 | pte_t pte = *ptep; |
0944fe3f | 1016 | |
ebde765c MS |
1017 | pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); |
1018 | return pte_young(pte); | |
0944fe3f MS |
1019 | } |
1020 | ||
1021 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
1022 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1023 | unsigned long address, pte_t *ptep) | |
1024 | { | |
1025 | return ptep_test_and_clear_young(vma, address, ptep); | |
1026 | } | |
1027 | ||
ba8a9229 | 1028 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
b2fa47e6 | 1029 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
ebde765c | 1030 | unsigned long addr, pte_t *ptep) |
b2fa47e6 | 1031 | { |
ebde765c | 1032 | return ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); |
b2fa47e6 MS |
1033 | } |
1034 | ||
1035 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
ebde765c MS |
1036 | pte_t ptep_modify_prot_start(struct mm_struct *, unsigned long, pte_t *); |
1037 | void ptep_modify_prot_commit(struct mm_struct *, unsigned long, pte_t *, pte_t); | |
ba8a9229 MS |
1038 | |
1039 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 | 1040 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
ebde765c | 1041 | unsigned long addr, pte_t *ptep) |
f0e47c22 | 1042 | { |
ebde765c | 1043 | return ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); |
1da177e4 LT |
1044 | } |
1045 | ||
ba8a9229 MS |
1046 | /* |
1047 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1048 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1049 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1050 | * cannot be accessed while the batched unmap is running. In this case | |
1051 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1052 | */ | |
1053 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1054 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
ebde765c | 1055 | unsigned long addr, |
ba8a9229 | 1056 | pte_t *ptep, int full) |
1da177e4 | 1057 | { |
ebde765c MS |
1058 | if (full) { |
1059 | pte_t pte = *ptep; | |
1060 | *ptep = __pte(_PAGE_INVALID); | |
1061 | return pte; | |
b2fa47e6 | 1062 | } |
ebde765c | 1063 | return ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); |
1da177e4 LT |
1064 | } |
1065 | ||
ba8a9229 | 1066 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
ebde765c MS |
1067 | static inline void ptep_set_wrprotect(struct mm_struct *mm, |
1068 | unsigned long addr, pte_t *ptep) | |
b2fa47e6 | 1069 | { |
b2fa47e6 MS |
1070 | pte_t pte = *ptep; |
1071 | ||
ebde765c MS |
1072 | if (pte_write(pte)) |
1073 | ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); | |
b2fa47e6 | 1074 | } |
ba8a9229 MS |
1075 | |
1076 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 | 1077 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
ebde765c | 1078 | unsigned long addr, pte_t *ptep, |
b2fa47e6 MS |
1079 | pte_t entry, int dirty) |
1080 | { | |
ebde765c | 1081 | if (pte_same(*ptep, entry)) |
b2fa47e6 | 1082 | return 0; |
ebde765c MS |
1083 | ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); |
1084 | return 1; | |
1085 | } | |
b2fa47e6 | 1086 | |
1e133ab2 MS |
1087 | /* |
1088 | * Additional functions to handle KVM guest page tables | |
1089 | */ | |
1090 | void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1091 | pte_t *ptep, pte_t entry); | |
1092 | void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | |
4be130a0 MS |
1093 | void ptep_notify(struct mm_struct *mm, unsigned long addr, |
1094 | pte_t *ptep, unsigned long bits); | |
b2d73b2a | 1095 | int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, |
4be130a0 | 1096 | pte_t *ptep, int prot, unsigned long bit); |
1e133ab2 MS |
1097 | void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, |
1098 | pte_t *ptep , int reset); | |
1099 | void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | |
4be130a0 | 1100 | int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, |
a9d23e71 | 1101 | pte_t *sptep, pte_t *tptep, pte_t pte); |
4be130a0 | 1102 | void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); |
1e133ab2 MS |
1103 | |
1104 | bool test_and_clear_guest_dirty(struct mm_struct *mm, unsigned long address); | |
1105 | int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, | |
1106 | unsigned char key, bool nq); | |
1824c723 DH |
1107 | int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, |
1108 | unsigned char key, unsigned char *oldkey, | |
1109 | bool nq, bool mr, bool mc); | |
a7e19ab5 | 1110 | int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); |
154c8c19 DH |
1111 | int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, |
1112 | unsigned char *key); | |
b2fa47e6 | 1113 | |
2d42f947 CI |
1114 | int set_pgste_bits(struct mm_struct *mm, unsigned long addr, |
1115 | unsigned long bits, unsigned long value); | |
1116 | int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); | |
1117 | int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, | |
1118 | unsigned long *oldpte, unsigned long *oldpgste); | |
1119 | ||
ebde765c MS |
1120 | /* |
1121 | * Certain architectures need to do special things when PTEs | |
1122 | * within a page table are directly modified. Thus, the following | |
1123 | * hook is made available. | |
1124 | */ | |
1125 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1126 | pte_t *ptep, pte_t entry) | |
1127 | { | |
57d7f939 MS |
1128 | if (!MACHINE_HAS_NX) |
1129 | pte_val(entry) &= ~_PAGE_NOEXEC; | |
a8f60d1f CB |
1130 | if (pte_present(entry)) |
1131 | pte_val(entry) &= ~_PAGE_UNUSED; | |
ebde765c | 1132 | if (mm_has_pgste(mm)) |
1e133ab2 | 1133 | ptep_set_pte_at(mm, addr, ptep, entry); |
ebde765c | 1134 | else |
abf09bed | 1135 | *ptep = entry; |
b2fa47e6 | 1136 | } |
1da177e4 | 1137 | |
1da177e4 LT |
1138 | /* |
1139 | * Conversion functions: convert a page and protection to a page entry, | |
1140 | * and a page entry and page directory to the page they refer to. | |
1141 | */ | |
1142 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1143 | { | |
1144 | pte_t __pte; | |
1145 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1146 | return pte_mkyoung(__pte); |
1da177e4 LT |
1147 | } |
1148 | ||
2dcea57a HC |
1149 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1150 | { | |
0b2b6e1d | 1151 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1152 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1153 | |
e5098611 MS |
1154 | if (pte_write(__pte) && PageDirty(page)) |
1155 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1156 | return __pte; |
2dcea57a HC |
1157 | } |
1158 | ||
190a1d72 | 1159 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1aea9b3f | 1160 | #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) |
190a1d72 MS |
1161 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
1162 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1163 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1164 | |
190a1d72 MS |
1165 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1166 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1167 | |
190a1d72 MS |
1168 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1169 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
1aea9b3f | 1170 | #define p4d_deref(pud) (p4d_val(pud) & _REGION_ENTRY_ORIGIN) |
5a216a20 | 1171 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1172 | |
1aea9b3f | 1173 | static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) |
5a216a20 | 1174 | { |
1aea9b3f MS |
1175 | p4d_t *p4d = (p4d_t *) pgd; |
1176 | ||
1177 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) | |
1178 | p4d = (p4d_t *) pgd_deref(*pgd); | |
1179 | return p4d + p4d_index(address); | |
1180 | } | |
1181 | ||
1182 | static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) | |
1183 | { | |
1184 | pud_t *pud = (pud_t *) p4d; | |
1185 | ||
1186 | if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1187 | pud = (pud_t *) p4d_deref(*p4d); | |
1188 | return pud + pud_index(address); | |
5a216a20 | 1189 | } |
1da177e4 | 1190 | |
190a1d72 | 1191 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1192 | { |
6252d702 | 1193 | pmd_t *pmd = (pmd_t *) pud; |
1aea9b3f | 1194 | |
6252d702 MS |
1195 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
1196 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1197 | return pmd + pmd_index(address); |
1da177e4 LT |
1198 | } |
1199 | ||
190a1d72 MS |
1200 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1201 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1202 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1203 | |
152125b7 | 1204 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
d08de8e2 | 1205 | #define pud_page(pud) pfn_to_page(pud_pfn(pud)) |
1aea9b3f | 1206 | #define p4d_page(pud) pfn_to_page(p4d_pfn(p4d)) |
1da177e4 | 1207 | |
190a1d72 MS |
1208 | /* Find an entry in the lowest level page table.. */ |
1209 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1210 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1211 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1212 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1213 | |
152125b7 | 1214 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1215 | { |
152125b7 MS |
1216 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1217 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1218 | return pmd; | |
1219 | } | |
1220 | ||
1221 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1222 | { | |
1223 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1224 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1225 | return pmd; | |
1226 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1227 | return pmd; | |
1228 | } | |
1229 | ||
1230 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1231 | { | |
1232 | if (pmd_large(pmd)) { | |
1233 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1234 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1235 | } |
1236 | return pmd; | |
1237 | } | |
1238 | ||
1239 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1240 | { | |
1241 | if (pmd_large(pmd)) { | |
5614dd92 MS |
1242 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | |
1243 | _SEGMENT_ENTRY_SOFT_DIRTY; | |
152125b7 MS |
1244 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) |
1245 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1246 | } | |
1247 | return pmd; | |
1248 | } | |
1249 | ||
9e20b4da HC |
1250 | static inline pud_t pud_wrprotect(pud_t pud) |
1251 | { | |
1252 | pud_val(pud) &= ~_REGION3_ENTRY_WRITE; | |
1253 | pud_val(pud) |= _REGION_ENTRY_PROTECT; | |
1254 | return pud; | |
1255 | } | |
1256 | ||
1257 | static inline pud_t pud_mkwrite(pud_t pud) | |
1258 | { | |
1259 | pud_val(pud) |= _REGION3_ENTRY_WRITE; | |
1260 | if (pud_large(pud) && !(pud_val(pud) & _REGION3_ENTRY_DIRTY)) | |
1261 | return pud; | |
1262 | pud_val(pud) &= ~_REGION_ENTRY_PROTECT; | |
1263 | return pud; | |
1264 | } | |
1265 | ||
1266 | static inline pud_t pud_mkclean(pud_t pud) | |
1267 | { | |
1268 | if (pud_large(pud)) { | |
1269 | pud_val(pud) &= ~_REGION3_ENTRY_DIRTY; | |
1270 | pud_val(pud) |= _REGION_ENTRY_PROTECT; | |
1271 | } | |
1272 | return pud; | |
1273 | } | |
1274 | ||
1275 | static inline pud_t pud_mkdirty(pud_t pud) | |
1276 | { | |
1277 | if (pud_large(pud)) { | |
1278 | pud_val(pud) |= _REGION3_ENTRY_DIRTY | | |
1279 | _REGION3_ENTRY_SOFT_DIRTY; | |
1280 | if (pud_val(pud) & _REGION3_ENTRY_WRITE) | |
1281 | pud_val(pud) &= ~_REGION_ENTRY_PROTECT; | |
1282 | } | |
1283 | return pud; | |
1284 | } | |
1285 | ||
1286 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) | |
1287 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) | |
1288 | { | |
1289 | /* | |
57d7f939 MS |
1290 | * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX |
1291 | * (see __Pxxx / __Sxxx). Convert to segment table entry format. | |
9e20b4da HC |
1292 | */ |
1293 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1294 | return pgprot_val(SEGMENT_NONE); | |
57d7f939 MS |
1295 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) |
1296 | return pgprot_val(SEGMENT_RO); | |
1297 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) | |
1298 | return pgprot_val(SEGMENT_RX); | |
1299 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) | |
1300 | return pgprot_val(SEGMENT_RW); | |
1301 | return pgprot_val(SEGMENT_RWX); | |
9e20b4da HC |
1302 | } |
1303 | ||
152125b7 MS |
1304 | static inline pmd_t pmd_mkyoung(pmd_t pmd) |
1305 | { | |
1306 | if (pmd_large(pmd)) { | |
0944fe3f | 1307 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1308 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1309 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1310 | } |
0944fe3f MS |
1311 | return pmd; |
1312 | } | |
1313 | ||
1314 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1315 | { | |
152125b7 | 1316 | if (pmd_large(pmd)) { |
0944fe3f MS |
1317 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1318 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1319 | } | |
0944fe3f MS |
1320 | return pmd; |
1321 | } | |
1322 | ||
1ae1c1d0 GS |
1323 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1324 | { | |
152125b7 MS |
1325 | if (pmd_large(pmd)) { |
1326 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1327 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
fecffad2 | 1328 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SOFT_DIRTY; |
152125b7 MS |
1329 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1330 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1331 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1332 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1333 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1334 | return pmd; | |
1335 | } | |
1336 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1337 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1338 | return pmd; | |
1339 | } | |
1340 | ||
106c992a | 1341 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1342 | { |
106c992a GS |
1343 | pmd_t __pmd; |
1344 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1345 | return __pmd; |
1ae1c1d0 GS |
1346 | } |
1347 | ||
106c992a GS |
1348 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1349 | ||
1b948d6c MS |
1350 | static inline void __pmdp_csp(pmd_t *pmdp) |
1351 | { | |
4ccccc52 HC |
1352 | csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), |
1353 | pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); | |
1b948d6c MS |
1354 | } |
1355 | ||
47e4d851 MS |
1356 | #define IDTE_GLOBAL 0 |
1357 | #define IDTE_LOCAL 1 | |
d08de8e2 | 1358 | |
118bd31b MS |
1359 | #define IDTE_PTOA 0x0800 |
1360 | #define IDTE_NODAT 0x1000 | |
28c807e5 | 1361 | #define IDTE_GUEST_ASCE 0x2000 |
118bd31b MS |
1362 | |
1363 | static inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, | |
28c807e5 MS |
1364 | unsigned long opt, unsigned long asce, |
1365 | int local) | |
1b948d6c MS |
1366 | { |
1367 | unsigned long sto; | |
1368 | ||
118bd31b | 1369 | sto = (unsigned long) pmdp - pmd_index(addr) * sizeof(pmd_t); |
28c807e5 MS |
1370 | if (__builtin_constant_p(opt) && opt == 0) { |
1371 | /* flush without guest asce */ | |
1372 | asm volatile( | |
1373 | " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" | |
1374 | : "+m" (*pmdp) | |
1375 | : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), | |
1376 | [m4] "i" (local) | |
1377 | : "cc" ); | |
1378 | } else { | |
1379 | /* flush with guest asce */ | |
1380 | asm volatile( | |
1381 | " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" | |
1382 | : "+m" (*pmdp) | |
1383 | : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), | |
1384 | [r3] "a" (asce), [m4] "i" (local) | |
1385 | : "cc" ); | |
1386 | } | |
1b948d6c MS |
1387 | } |
1388 | ||
118bd31b | 1389 | static inline void __pudp_idte(unsigned long addr, pud_t *pudp, |
28c807e5 MS |
1390 | unsigned long opt, unsigned long asce, |
1391 | int local) | |
d08de8e2 GS |
1392 | { |
1393 | unsigned long r3o; | |
1394 | ||
118bd31b | 1395 | r3o = (unsigned long) pudp - pud_index(addr) * sizeof(pud_t); |
d08de8e2 | 1396 | r3o |= _ASCE_TYPE_REGION3; |
28c807e5 MS |
1397 | if (__builtin_constant_p(opt) && opt == 0) { |
1398 | /* flush without guest asce */ | |
1399 | asm volatile( | |
1400 | " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" | |
1401 | : "+m" (*pudp) | |
1402 | : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), | |
1403 | [m4] "i" (local) | |
1404 | : "cc"); | |
1405 | } else { | |
1406 | /* flush with guest asce */ | |
1407 | asm volatile( | |
1408 | " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" | |
1409 | : "+m" (*pudp) | |
1410 | : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), | |
1411 | [r3] "a" (asce), [m4] "i" (local) | |
1412 | : "cc" ); | |
1413 | } | |
d08de8e2 GS |
1414 | } |
1415 | ||
227be799 MS |
1416 | pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); |
1417 | pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); | |
d08de8e2 | 1418 | pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); |
1b948d6c | 1419 | |
227be799 MS |
1420 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1421 | ||
1422 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
1423 | void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
1424 | pgtable_t pgtable); | |
1425 | ||
1426 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
1427 | pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); | |
1b948d6c | 1428 | |
227be799 MS |
1429 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1430 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1431 | unsigned long addr, pmd_t *pmdp, | |
1432 | pmd_t entry, int dirty) | |
3eabaee9 | 1433 | { |
227be799 | 1434 | VM_BUG_ON(addr & ~HPAGE_MASK); |
3eabaee9 | 1435 | |
227be799 MS |
1436 | entry = pmd_mkyoung(entry); |
1437 | if (dirty) | |
1438 | entry = pmd_mkdirty(entry); | |
1439 | if (pmd_val(*pmdp) == pmd_val(entry)) | |
1440 | return 0; | |
1441 | pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); | |
1442 | return 1; | |
3eabaee9 MS |
1443 | } |
1444 | ||
227be799 MS |
1445 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1446 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1447 | unsigned long addr, pmd_t *pmdp) | |
1448 | { | |
1449 | pmd_t pmd = *pmdp; | |
106c992a | 1450 | |
227be799 MS |
1451 | pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); |
1452 | return pmd_young(pmd); | |
1453 | } | |
106c992a | 1454 | |
227be799 MS |
1455 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH |
1456 | static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
1457 | unsigned long addr, pmd_t *pmdp) | |
1458 | { | |
1459 | VM_BUG_ON(addr & ~HPAGE_MASK); | |
1460 | return pmdp_test_and_clear_young(vma, addr, pmdp); | |
1461 | } | |
106c992a | 1462 | |
106c992a GS |
1463 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
1464 | pmd_t *pmdp, pmd_t entry) | |
1465 | { | |
57d7f939 MS |
1466 | if (!MACHINE_HAS_NX) |
1467 | pmd_val(entry) &= ~_SEGMENT_ENTRY_NOEXEC; | |
106c992a GS |
1468 | *pmdp = entry; |
1469 | } | |
1470 | ||
1471 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1472 | { | |
1473 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1474 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1475 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1476 | return pmd; |
1477 | } | |
1478 | ||
8809aa2d AK |
1479 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
1480 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
227be799 | 1481 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1482 | { |
54397bb0 | 1483 | return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); |
1ae1c1d0 GS |
1484 | } |
1485 | ||
8809aa2d AK |
1486 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1487 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, | |
227be799 | 1488 | unsigned long addr, |
8809aa2d | 1489 | pmd_t *pmdp, int full) |
fcbe08d6 | 1490 | { |
227be799 MS |
1491 | if (full) { |
1492 | pmd_t pmd = *pmdp; | |
54397bb0 | 1493 | *pmdp = __pmd(_SEGMENT_ENTRY_EMPTY); |
227be799 MS |
1494 | return pmd; |
1495 | } | |
54397bb0 | 1496 | return pmdp_xchg_lazy(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); |
fcbe08d6 MS |
1497 | } |
1498 | ||
8809aa2d AK |
1499 | #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
1500 | static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
227be799 | 1501 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1502 | { |
227be799 | 1503 | return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); |
1ae1c1d0 GS |
1504 | } |
1505 | ||
1506 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1507 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
227be799 | 1508 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1509 | { |
54397bb0 | 1510 | pmdp_xchg_direct(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); |
1ae1c1d0 GS |
1511 | } |
1512 | ||
be328650 GS |
1513 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1514 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
227be799 | 1515 | unsigned long addr, pmd_t *pmdp) |
be328650 GS |
1516 | { |
1517 | pmd_t pmd = *pmdp; | |
1518 | ||
227be799 MS |
1519 | if (pmd_write(pmd)) |
1520 | pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); | |
be328650 GS |
1521 | } |
1522 | ||
f28b6ff8 AK |
1523 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1524 | unsigned long address, | |
1525 | pmd_t *pmdp) | |
1526 | { | |
8809aa2d | 1527 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
f28b6ff8 AK |
1528 | } |
1529 | #define pmdp_collapse_flush pmdp_collapse_flush | |
1530 | ||
1ae1c1d0 GS |
1531 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1532 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1533 | ||
1534 | static inline int pmd_trans_huge(pmd_t pmd) | |
1535 | { | |
1536 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1537 | } | |
1538 | ||
fd8cfd30 | 1539 | #define has_transparent_hugepage has_transparent_hugepage |
1ae1c1d0 GS |
1540 | static inline int has_transparent_hugepage(void) |
1541 | { | |
466178fc | 1542 | return MACHINE_HAS_EDAT1 ? 1 : 0; |
1ae1c1d0 | 1543 | } |
75077afb GS |
1544 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1545 | ||
1da177e4 | 1546 | /* |
1da177e4 LT |
1547 | * 64 bit swap entry format: |
1548 | * A page-table entry has some bits we have to treat in a special way. | |
4e0a6412 | 1549 | * Bits 52 and bit 55 have to be zero, otherwise a specification |
1da177e4 | 1550 | * exception will occur instead of a page translation exception. The |
4e0a6412 | 1551 | * specification exception has the bad habit not to store necessary |
1da177e4 | 1552 | * information in the lowcore. |
a1c843b8 MS |
1553 | * Bits 54 and 63 are used to indicate the page type. |
1554 | * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 | |
1555 | * This leaves the bits 0-51 and bits 56-62 to store type and offset. | |
1556 | * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 | |
1557 | * for the offset. | |
1558 | * | offset |01100|type |00| | |
1559 | * |0000000000111111111122222222223333333333444444444455|55555|55566|66| | |
1560 | * |0123456789012345678901234567890123456789012345678901|23456|78901|23| | |
1da177e4 | 1561 | */ |
5a79859a | 1562 | |
a1c843b8 MS |
1563 | #define __SWP_OFFSET_MASK ((1UL << 52) - 1) |
1564 | #define __SWP_OFFSET_SHIFT 12 | |
1565 | #define __SWP_TYPE_MASK ((1UL << 5) - 1) | |
1566 | #define __SWP_TYPE_SHIFT 2 | |
5a79859a | 1567 | |
4448aaf0 | 1568 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1569 | { |
1570 | pte_t pte; | |
a1c843b8 MS |
1571 | |
1572 | pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; | |
1573 | pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; | |
1574 | pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; | |
1da177e4 LT |
1575 | return pte; |
1576 | } | |
1577 | ||
a1c843b8 MS |
1578 | static inline unsigned long __swp_type(swp_entry_t entry) |
1579 | { | |
1580 | return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; | |
1581 | } | |
1582 | ||
1583 | static inline unsigned long __swp_offset(swp_entry_t entry) | |
1584 | { | |
1585 | return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; | |
1586 | } | |
1587 | ||
1588 | static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) | |
1589 | { | |
1590 | return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; | |
1591 | } | |
1da177e4 LT |
1592 | |
1593 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1594 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1595 | ||
1da177e4 LT |
1596 | #endif /* !__ASSEMBLY__ */ |
1597 | ||
1598 | #define kern_addr_valid(addr) (1) | |
1599 | ||
17f34580 HC |
1600 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1601 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1602 | extern int s390_enable_sie(void); |
3ac8e380 | 1603 | extern int s390_enable_skey(void); |
a13cff31 | 1604 | extern void s390_reset_cmma(struct mm_struct *mm); |
f4eb07c1 | 1605 | |
1f6b83e5 MS |
1606 | /* s390 has a private copy of get unmapped area to deal with cache synonyms */ |
1607 | #define HAVE_ARCH_UNMAPPED_AREA | |
1608 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1609 | ||
1da177e4 LT |
1610 | /* |
1611 | * No page table caches to initialise | |
1612 | */ | |
765a0cac HC |
1613 | static inline void pgtable_cache_init(void) { } |
1614 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1615 | |
1da177e4 LT |
1616 | #include <asm-generic/pgtable.h> |
1617 | ||
1618 | #endif /* _S390_PAGE_H */ |