]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
1da177e4 | 3 | * S390 version |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
5 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
6 | * Ulrich Weigand (weigand@de.ibm.com) | |
7 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
8 | * | |
9 | * Derived from "include/asm-i386/pgtable.h" | |
10 | */ | |
11 | ||
12 | #ifndef _ASM_S390_PGTABLE_H | |
13 | #define _ASM_S390_PGTABLE_H | |
14 | ||
9789db08 | 15 | #include <linux/sched.h> |
2dcea57a | 16 | #include <linux/mm_types.h> |
abf09bed | 17 | #include <linux/page-flags.h> |
527e30b4 | 18 | #include <linux/radix-tree.h> |
37cd944c | 19 | #include <linux/atomic.h> |
1da177e4 | 20 | #include <asm/bug.h> |
b2fa47e6 | 21 | #include <asm/page.h> |
1da177e4 | 22 | |
0ccb32c9 | 23 | extern pgd_t swapper_pg_dir[]; |
1da177e4 LT |
24 | extern void paging_init(void); |
25 | ||
37cd944c HC |
26 | enum { |
27 | PG_DIRECT_MAP_4K = 0, | |
28 | PG_DIRECT_MAP_1M, | |
29 | PG_DIRECT_MAP_2G, | |
30 | PG_DIRECT_MAP_MAX | |
31 | }; | |
32 | ||
33 | extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; | |
34 | ||
35 | static inline void update_page_count(int level, long count) | |
36 | { | |
37 | if (IS_ENABLED(CONFIG_PROC_FS)) | |
38 | atomic_long_add(count, &direct_pages_count[level]); | |
39 | } | |
40 | ||
41 | struct seq_file; | |
42 | void arch_report_meminfo(struct seq_file *m); | |
43 | ||
1da177e4 LT |
44 | /* |
45 | * The S390 doesn't have any external MMU info: the kernel page | |
46 | * tables contain all the necessary information. | |
47 | */ | |
4b3073e1 | 48 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 49 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
50 | |
51 | /* | |
238ec4ef | 52 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
53 | * for zero-mapped memory areas etc.. |
54 | */ | |
238ec4ef MS |
55 | |
56 | extern unsigned long empty_zero_page; | |
57 | extern unsigned long zero_page_mask; | |
58 | ||
59 | #define ZERO_PAGE(vaddr) \ | |
60 | (virt_to_page((void *)(empty_zero_page + \ | |
61 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 62 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 63 | |
4f2e2903 | 64 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 | 65 | |
d016bf7e | 66 | #define FIRST_USER_ADDRESS 0UL |
d455a369 | 67 | |
1da177e4 LT |
68 | #define pte_ERROR(e) \ |
69 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
70 | #define pmd_ERROR(e) \ | |
71 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
72 | #define pud_ERROR(e) \ |
73 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1aea9b3f MS |
74 | #define p4d_ERROR(e) \ |
75 | printk("%s:%d: bad p4d %p.\n", __FILE__, __LINE__, (void *) p4d_val(e)) | |
1da177e4 LT |
76 | #define pgd_ERROR(e) \ |
77 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
78 | ||
1da177e4 | 79 | /* |
a1c843b8 MS |
80 | * The vmalloc and module area will always be on the topmost area of the |
81 | * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. | |
c972cc60 HC |
82 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where |
83 | * modules will reside. That makes sure that inter module branches always | |
84 | * happen without trampolines and in addition the placement within a 2GB frame | |
85 | * is branch prediction unit friendly. | |
8b62bc96 | 86 | */ |
239a6425 | 87 | extern unsigned long VMALLOC_START; |
14045ebf MS |
88 | extern unsigned long VMALLOC_END; |
89 | extern struct page *vmemmap; | |
239a6425 | 90 | |
14045ebf | 91 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 92 | |
c972cc60 HC |
93 | extern unsigned long MODULES_VADDR; |
94 | extern unsigned long MODULES_END; | |
95 | #define MODULES_VADDR MODULES_VADDR | |
96 | #define MODULES_END MODULES_END | |
97 | #define MODULES_LEN (1UL << 31) | |
c972cc60 | 98 | |
c933146a HC |
99 | static inline int is_module_addr(void *addr) |
100 | { | |
c933146a HC |
101 | BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); |
102 | if (addr < (void *)MODULES_VADDR) | |
103 | return 0; | |
104 | if (addr > (void *)MODULES_END) | |
105 | return 0; | |
c933146a HC |
106 | return 1; |
107 | } | |
108 | ||
1da177e4 | 109 | /* |
1da177e4 | 110 | * A 64 bit pagetable entry of S390 has following format: |
6a985c61 | 111 | * | PFRA |0IPC| OS | |
1da177e4 LT |
112 | * 0000000000111111111122222222223333333333444444444455555555556666 |
113 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
114 | * | |
115 | * I Page-Invalid Bit: Page is not available for address-translation | |
116 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 117 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
118 | * |
119 | * A 64 bit segmenttable entry of S390 has following format: | |
120 | * | P-table origin | TT | |
121 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
122 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
123 | * | |
124 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
125 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
126 | * P Page-Protection Bit: Store access not possible for page | |
127 | * TT Type 00 | |
128 | * | |
129 | * A 64 bit region table entry of S390 has following format: | |
130 | * | S-table origin | TF TTTL | |
131 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
132 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
133 | * | |
134 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
135 | * TT Type 01 | |
136 | * TF | |
190a1d72 | 137 | * TL Table length |
1da177e4 LT |
138 | * |
139 | * The 64 bit regiontable origin of S390 has following format: | |
140 | * | region table origon | DTTL | |
141 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
142 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
143 | * | |
144 | * X Space-Switch event: | |
145 | * G Segment-Invalid Bit: | |
146 | * P Private-Space Bit: | |
147 | * S Storage-Alteration: | |
148 | * R Real space | |
149 | * TL Table-Length: | |
150 | * | |
151 | * A storage key has the following format: | |
152 | * | ACC |F|R|C|0| | |
153 | * 0 3 4 5 6 7 | |
154 | * ACC: access key | |
155 | * F : fetch protection bit | |
156 | * R : referenced bit | |
157 | * C : changed bit | |
158 | */ | |
159 | ||
160 | /* Hardware bits in the page table entry */ | |
57d7f939 | 161 | #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ |
e5098611 | 162 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 163 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 164 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
165 | |
166 | /* Software bits in the page table entry */ | |
e5098611 | 167 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
e5098611 MS |
168 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ |
169 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
170 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
171 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
172 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 173 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 174 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 175 | |
5614dd92 MS |
176 | #ifdef CONFIG_MEM_SOFT_DIRTY |
177 | #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ | |
178 | #else | |
179 | #define _PAGE_SOFT_DIRTY 0x000 | |
180 | #endif | |
181 | ||
138c9021 | 182 | /* Set of bits not changed in pte_modify */ |
6a5c1482 | 183 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ |
5614dd92 | 184 | _PAGE_YOUNG | _PAGE_SOFT_DIRTY) |
53492b1d | 185 | |
83377484 | 186 | /* |
6e76d4b2 KS |
187 | * handle_pte_fault uses pte_present and pte_none to find out the pte type |
188 | * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to | |
189 | * distinguish present from not-present ptes. It is changed only with the page | |
190 | * table lock held. | |
83377484 | 191 | * |
e5098611 | 192 | * The following table gives the different possible bit combinations for |
a1c843b8 MS |
193 | * the pte hardware and software bits in the last 12 bits of a pte |
194 | * (. unassigned bit, x don't care, t swap type): | |
83377484 | 195 | * |
0944fe3f MS |
196 | * 842100000000 |
197 | * 000084210000 | |
198 | * 000000008421 | |
a1c843b8 MS |
199 | * .IR.uswrdy.p |
200 | * empty .10.00000000 | |
201 | * swap .11..ttttt.0 | |
202 | * prot-none, clean, old .11.xx0000.1 | |
203 | * prot-none, clean, young .11.xx0001.1 | |
bc29b7ac GS |
204 | * prot-none, dirty, old .11.xx0010.1 |
205 | * prot-none, dirty, young .11.xx0011.1 | |
a1c843b8 MS |
206 | * read-only, clean, old .11.xx0100.1 |
207 | * read-only, clean, young .01.xx0101.1 | |
208 | * read-only, dirty, old .11.xx0110.1 | |
209 | * read-only, dirty, young .01.xx0111.1 | |
210 | * read-write, clean, old .11.xx1100.1 | |
211 | * read-write, clean, young .01.xx1101.1 | |
212 | * read-write, dirty, old .10.xx1110.1 | |
213 | * read-write, dirty, young .00.xx1111.1 | |
214 | * HW-bits: R read-only, I invalid | |
215 | * SW-bits: p present, y young, d dirty, r read, w write, s special, | |
216 | * u unused, l large | |
e5098611 | 217 | * |
a1c843b8 MS |
218 | * pte_none is true for the bit pattern .10.00000000, pte == 0x400 |
219 | * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 | |
220 | * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 | |
83377484 MS |
221 | */ |
222 | ||
3610cce8 | 223 | /* Bits in the segment/region table address-space-control-element */ |
8457d775 | 224 | #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ |
3610cce8 MS |
225 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ |
226 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
227 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
228 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
229 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
230 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
231 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
232 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
233 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
234 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
235 | ||
236 | /* Bits in the region table entry */ | |
237 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 | 238 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
57d7f939 | 239 | #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ |
4be130a0 | 240 | #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ |
e5098611 | 241 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ |
3610cce8 MS |
242 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
243 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
244 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
245 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
246 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
247 | ||
248 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 249 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 250 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 251 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 252 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 253 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 254 | |
9e20b4da | 255 | #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ |
2dffdcba HC |
256 | #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ |
257 | #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ | |
258 | #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ | |
259 | #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ | |
260 | #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ | |
261 | ||
262 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
263 | #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ | |
264 | #else | |
265 | #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ | |
266 | #endif | |
267 | ||
1aea9b3f MS |
268 | #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL |
269 | #define _REGION_ENTRY_BITS_LARGE 0xffffffff8000fe2fUL | |
d08de8e2 | 270 | |
1da177e4 | 271 | /* Bits in the segment table entry */ |
0944fe3f | 272 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 273 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 274 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
8457d775 HC |
275 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ |
276 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ | |
277 | #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ | |
e5098611 | 278 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ |
1da177e4 | 279 | |
3610cce8 | 280 | #define _SEGMENT_ENTRY (0) |
e5098611 | 281 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 282 | |
152125b7 MS |
283 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
284 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
152125b7 | 285 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ |
bc29b7ac GS |
286 | #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ |
287 | #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ | |
0944fe3f | 288 | |
5614dd92 MS |
289 | #ifdef CONFIG_MEM_SOFT_DIRTY |
290 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ | |
291 | #else | |
292 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ | |
293 | #endif | |
294 | ||
c67da7c7 HC |
295 | #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ |
296 | #define _PAGE_ENTRIES 256 /* number of page table entries */ | |
297 | ||
298 | #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) | |
299 | #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) | |
300 | ||
301 | #define _REGION1_SHIFT 53 | |
302 | #define _REGION2_SHIFT 42 | |
303 | #define _REGION3_SHIFT 31 | |
304 | #define _SEGMENT_SHIFT 20 | |
305 | ||
306 | #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) | |
307 | #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) | |
308 | #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) | |
309 | #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) | |
310 | #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) | |
311 | ||
312 | #define _REGION1_SIZE (1UL << _REGION1_SHIFT) | |
313 | #define _REGION2_SIZE (1UL << _REGION2_SHIFT) | |
314 | #define _REGION3_SIZE (1UL << _REGION3_SHIFT) | |
315 | #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) | |
316 | ||
317 | #define _REGION1_MASK (~(_REGION1_SIZE - 1)) | |
318 | #define _REGION2_MASK (~(_REGION2_SIZE - 1)) | |
319 | #define _REGION3_MASK (~(_REGION3_SIZE - 1)) | |
320 | #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) | |
321 | ||
322 | #define PMD_SHIFT _SEGMENT_SHIFT | |
323 | #define PUD_SHIFT _REGION3_SHIFT | |
324 | #define P4D_SHIFT _REGION2_SHIFT | |
325 | #define PGDIR_SHIFT _REGION1_SHIFT | |
326 | ||
327 | #define PMD_SIZE _SEGMENT_SIZE | |
328 | #define PUD_SIZE _REGION3_SIZE | |
329 | #define P4D_SIZE _REGION2_SIZE | |
330 | #define PGDIR_SIZE _REGION1_SIZE | |
331 | ||
332 | #define PMD_MASK _SEGMENT_MASK | |
333 | #define PUD_MASK _REGION3_MASK | |
334 | #define P4D_MASK _REGION2_MASK | |
335 | #define PGDIR_MASK _REGION1_MASK | |
336 | ||
337 | #define PTRS_PER_PTE _PAGE_ENTRIES | |
338 | #define PTRS_PER_PMD _CRST_ENTRIES | |
339 | #define PTRS_PER_PUD _CRST_ENTRIES | |
340 | #define PTRS_PER_P4D _CRST_ENTRIES | |
341 | #define PTRS_PER_PGD _CRST_ENTRIES | |
342 | ||
0944fe3f | 343 | /* |
2dffdcba HC |
344 | * Segment table and region3 table entry encoding |
345 | * (R = read-only, I = invalid, y = young bit): | |
bc29b7ac | 346 | * dy..R...I...wr |
152125b7 MS |
347 | * prot-none, clean, old 00..1...1...00 |
348 | * prot-none, clean, young 01..1...1...00 | |
349 | * prot-none, dirty, old 10..1...1...00 | |
350 | * prot-none, dirty, young 11..1...1...00 | |
bc29b7ac GS |
351 | * read-only, clean, old 00..1...1...01 |
352 | * read-only, clean, young 01..1...0...01 | |
353 | * read-only, dirty, old 10..1...1...01 | |
354 | * read-only, dirty, young 11..1...0...01 | |
152125b7 MS |
355 | * read-write, clean, old 00..1...1...11 |
356 | * read-write, clean, young 01..1...0...11 | |
357 | * read-write, dirty, old 10..0...1...11 | |
358 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
359 | * The segment table origin is used to distinguish empty (origin==0) from |
360 | * read-write, old segment table entries (origin!=0) | |
a1c843b8 MS |
361 | * HW-bits: R read-only, I invalid |
362 | * SW-bits: y young, d dirty, r read, w write | |
0944fe3f | 363 | */ |
e5098611 | 364 | |
6c61cfe9 | 365 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
366 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
367 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
368 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
369 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
370 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
371 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
372 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
373 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
374 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
4be130a0 | 375 | #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ |
6c61cfe9 | 376 | |
b31288fa | 377 | /* Guest Page State used for virtualization */ |
2d42f947 | 378 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL |
cd774b90 | 379 | #define _PGSTE_GPS_NODAT 0x0000000040000000UL |
2d42f947 CI |
380 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL |
381 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
382 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
383 | #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL | |
384 | #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK | |
b31288fa | 385 | |
1da177e4 | 386 | /* |
3610cce8 MS |
387 | * A user page table pointer has the space-switch-event bit, the |
388 | * private-space-control bit and the storage-alteration-event-control | |
389 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 390 | */ |
3610cce8 MS |
391 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
392 | _ASCE_ALT_EVENT) | |
1da177e4 | 393 | |
1da177e4 | 394 | /* |
9282ed92 | 395 | * Page protection definitions. |
1da177e4 | 396 | */ |
bc29b7ac | 397 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) |
57d7f939 MS |
398 | #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
399 | _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) | |
400 | #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ | |
0944fe3f | 401 | _PAGE_INVALID | _PAGE_PROTECT) |
57d7f939 MS |
402 | #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
403 | _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) | |
404 | #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
0944fe3f MS |
405 | _PAGE_INVALID | _PAGE_PROTECT) |
406 | ||
407 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
57d7f939 | 408 | _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) |
0944fe3f | 409 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
57d7f939 | 410 | _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) |
0944fe3f | 411 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ |
57d7f939 MS |
412 | _PAGE_PROTECT | _PAGE_NOEXEC) |
413 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
414 | _PAGE_YOUNG | _PAGE_DIRTY) | |
1da177e4 LT |
415 | |
416 | /* | |
043d0708 MS |
417 | * On s390 the page table entry has an invalid bit and a read-only bit. |
418 | * Read permission implies execute permission and write permission | |
419 | * implies read permission. | |
1da177e4 LT |
420 | */ |
421 | /*xwr*/ | |
9282ed92 | 422 | #define __P000 PAGE_NONE |
57d7f939 MS |
423 | #define __P001 PAGE_RO |
424 | #define __P010 PAGE_RO | |
425 | #define __P011 PAGE_RO | |
426 | #define __P100 PAGE_RX | |
427 | #define __P101 PAGE_RX | |
428 | #define __P110 PAGE_RX | |
429 | #define __P111 PAGE_RX | |
9282ed92 GS |
430 | |
431 | #define __S000 PAGE_NONE | |
57d7f939 MS |
432 | #define __S001 PAGE_RO |
433 | #define __S010 PAGE_RW | |
434 | #define __S011 PAGE_RW | |
435 | #define __S100 PAGE_RX | |
436 | #define __S101 PAGE_RX | |
437 | #define __S110 PAGE_RWX | |
438 | #define __S111 PAGE_RWX | |
1da177e4 | 439 | |
106c992a GS |
440 | /* |
441 | * Segment entry (large page) protection definitions. | |
442 | */ | |
e5098611 MS |
443 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
444 | _SEGMENT_ENTRY_PROTECT) | |
57d7f939 MS |
445 | #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
446 | _SEGMENT_ENTRY_READ | \ | |
447 | _SEGMENT_ENTRY_NOEXEC) | |
448 | #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ | |
152125b7 | 449 | _SEGMENT_ENTRY_READ) |
57d7f939 MS |
450 | #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ |
451 | _SEGMENT_ENTRY_WRITE | \ | |
452 | _SEGMENT_ENTRY_NOEXEC) | |
453 | #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ | |
152125b7 | 454 | _SEGMENT_ENTRY_WRITE) |
2dffdcba HC |
455 | #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ |
456 | _SEGMENT_ENTRY_LARGE | \ | |
457 | _SEGMENT_ENTRY_READ | \ | |
458 | _SEGMENT_ENTRY_WRITE | \ | |
459 | _SEGMENT_ENTRY_YOUNG | \ | |
57d7f939 MS |
460 | _SEGMENT_ENTRY_DIRTY | \ |
461 | _SEGMENT_ENTRY_NOEXEC) | |
2dffdcba HC |
462 | #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ |
463 | _SEGMENT_ENTRY_LARGE | \ | |
464 | _SEGMENT_ENTRY_READ | \ | |
465 | _SEGMENT_ENTRY_YOUNG | \ | |
57d7f939 MS |
466 | _SEGMENT_ENTRY_PROTECT | \ |
467 | _SEGMENT_ENTRY_NOEXEC) | |
2dffdcba HC |
468 | |
469 | /* | |
470 | * Region3 entry (large page) protection definitions. | |
471 | */ | |
472 | ||
473 | #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ | |
474 | _REGION3_ENTRY_LARGE | \ | |
475 | _REGION3_ENTRY_READ | \ | |
476 | _REGION3_ENTRY_WRITE | \ | |
477 | _REGION3_ENTRY_YOUNG | \ | |
57d7f939 MS |
478 | _REGION3_ENTRY_DIRTY | \ |
479 | _REGION_ENTRY_NOEXEC) | |
2dffdcba HC |
480 | #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ |
481 | _REGION3_ENTRY_LARGE | \ | |
482 | _REGION3_ENTRY_READ | \ | |
483 | _REGION3_ENTRY_YOUNG | \ | |
57d7f939 MS |
484 | _REGION_ENTRY_PROTECT | \ |
485 | _REGION_ENTRY_NOEXEC) | |
106c992a | 486 | |
b2fa47e6 MS |
487 | static inline int mm_has_pgste(struct mm_struct *mm) |
488 | { | |
489 | #ifdef CONFIG_PGSTE | |
490 | if (unlikely(mm->context.has_pgste)) | |
491 | return 1; | |
492 | #endif | |
493 | return 0; | |
494 | } | |
65eef335 | 495 | |
0b46e0a3 MS |
496 | static inline int mm_alloc_pgste(struct mm_struct *mm) |
497 | { | |
498 | #ifdef CONFIG_PGSTE | |
499 | if (unlikely(mm->context.alloc_pgste)) | |
500 | return 1; | |
501 | #endif | |
502 | return 0; | |
503 | } | |
504 | ||
2faee8ff DD |
505 | /* |
506 | * In the case that a guest uses storage keys | |
507 | * faults should no longer be backed by zero pages | |
508 | */ | |
fa41ba0d | 509 | #define mm_forbids_zeropage mm_has_pgste |
65eef335 DD |
510 | static inline int mm_use_skey(struct mm_struct *mm) |
511 | { | |
512 | #ifdef CONFIG_PGSTE | |
513 | if (mm->context.use_skey) | |
514 | return 1; | |
515 | #endif | |
516 | return 0; | |
517 | } | |
518 | ||
4ccccc52 HC |
519 | static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) |
520 | { | |
521 | register unsigned long reg2 asm("2") = old; | |
522 | register unsigned long reg3 asm("3") = new; | |
523 | unsigned long address = (unsigned long)ptr | 1; | |
524 | ||
525 | asm volatile( | |
526 | " csp %0,%3" | |
527 | : "+d" (reg2), "+m" (*ptr) | |
528 | : "d" (reg3), "d" (address) | |
529 | : "cc"); | |
530 | } | |
531 | ||
e8a97e42 HC |
532 | static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) |
533 | { | |
534 | register unsigned long reg2 asm("2") = old; | |
535 | register unsigned long reg3 asm("3") = new; | |
536 | unsigned long address = (unsigned long)ptr | 1; | |
537 | ||
538 | asm volatile( | |
539 | " .insn rre,0xb98a0000,%0,%3" | |
540 | : "+d" (reg2), "+m" (*ptr) | |
541 | : "d" (reg3), "d" (address) | |
542 | : "cc"); | |
543 | } | |
544 | ||
545 | #define CRDTE_DTT_PAGE 0x00UL | |
546 | #define CRDTE_DTT_SEGMENT 0x10UL | |
547 | #define CRDTE_DTT_REGION3 0x14UL | |
548 | #define CRDTE_DTT_REGION2 0x18UL | |
549 | #define CRDTE_DTT_REGION1 0x1cUL | |
550 | ||
551 | static inline void crdte(unsigned long old, unsigned long new, | |
552 | unsigned long table, unsigned long dtt, | |
553 | unsigned long address, unsigned long asce) | |
554 | { | |
555 | register unsigned long reg2 asm("2") = old; | |
556 | register unsigned long reg3 asm("3") = new; | |
557 | register unsigned long reg4 asm("4") = table | dtt; | |
558 | register unsigned long reg5 asm("5") = address; | |
559 | ||
560 | asm volatile(".insn rrf,0xb98f0000,%0,%2,%4,0" | |
561 | : "+d" (reg2) | |
562 | : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce) | |
563 | : "memory", "cc"); | |
564 | } | |
565 | ||
1da177e4 | 566 | /* |
cc18b460 | 567 | * pgd/p4d/pud/pmd/pte query functions |
1da177e4 | 568 | */ |
cc18b460 HC |
569 | static inline int pgd_folded(pgd_t pgd) |
570 | { | |
571 | return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; | |
572 | } | |
573 | ||
5a216a20 MS |
574 | static inline int pgd_present(pgd_t pgd) |
575 | { | |
cc18b460 | 576 | if (pgd_folded(pgd)) |
6252d702 | 577 | return 1; |
5a216a20 MS |
578 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
579 | } | |
580 | ||
581 | static inline int pgd_none(pgd_t pgd) | |
582 | { | |
cc18b460 | 583 | if (pgd_folded(pgd)) |
6252d702 | 584 | return 0; |
e5098611 | 585 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
586 | } |
587 | ||
588 | static inline int pgd_bad(pgd_t pgd) | |
589 | { | |
6252d702 MS |
590 | /* |
591 | * With dynamic page table levels the pgd can be a region table | |
592 | * entry or a segment table entry. Check for the bit that are | |
593 | * invalid for either table entry. | |
594 | */ | |
5a216a20 | 595 | unsigned long mask = |
e5098611 | 596 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
597 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
598 | return (pgd_val(pgd) & mask) != 0; | |
599 | } | |
190a1d72 | 600 | |
cc18b460 HC |
601 | static inline int p4d_folded(p4d_t p4d) |
602 | { | |
603 | return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; | |
604 | } | |
605 | ||
1aea9b3f MS |
606 | static inline int p4d_present(p4d_t p4d) |
607 | { | |
cc18b460 | 608 | if (p4d_folded(p4d)) |
1aea9b3f MS |
609 | return 1; |
610 | return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; | |
611 | } | |
612 | ||
613 | static inline int p4d_none(p4d_t p4d) | |
614 | { | |
cc18b460 | 615 | if (p4d_folded(p4d)) |
1aea9b3f MS |
616 | return 0; |
617 | return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; | |
618 | } | |
619 | ||
620 | static inline unsigned long p4d_pfn(p4d_t p4d) | |
621 | { | |
622 | unsigned long origin_mask; | |
623 | ||
624 | origin_mask = _REGION_ENTRY_ORIGIN; | |
625 | return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; | |
626 | } | |
627 | ||
cc18b460 HC |
628 | static inline int pud_folded(pud_t pud) |
629 | { | |
630 | return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; | |
631 | } | |
632 | ||
190a1d72 | 633 | static inline int pud_present(pud_t pud) |
1da177e4 | 634 | { |
cc18b460 | 635 | if (pud_folded(pud)) |
6252d702 | 636 | return 1; |
0d017923 | 637 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
638 | } |
639 | ||
190a1d72 | 640 | static inline int pud_none(pud_t pud) |
1da177e4 | 641 | { |
cc18b460 | 642 | if (pud_folded(pud)) |
6252d702 | 643 | return 0; |
d08de8e2 | 644 | return pud_val(pud) == _REGION3_ENTRY_EMPTY; |
1da177e4 LT |
645 | } |
646 | ||
18da2369 HC |
647 | static inline int pud_large(pud_t pud) |
648 | { | |
649 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
650 | return 0; | |
651 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
652 | } | |
653 | ||
9e20b4da HC |
654 | static inline unsigned long pud_pfn(pud_t pud) |
655 | { | |
656 | unsigned long origin_mask; | |
657 | ||
f96c6f72 | 658 | origin_mask = _REGION_ENTRY_ORIGIN; |
9e20b4da HC |
659 | if (pud_large(pud)) |
660 | origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; | |
661 | return (pud_val(pud) & origin_mask) >> PAGE_SHIFT; | |
662 | } | |
663 | ||
d08de8e2 GS |
664 | static inline int pmd_large(pmd_t pmd) |
665 | { | |
666 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; | |
667 | } | |
668 | ||
669 | static inline int pmd_bad(pmd_t pmd) | |
670 | { | |
671 | if (pmd_large(pmd)) | |
672 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
673 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; | |
674 | } | |
675 | ||
190a1d72 | 676 | static inline int pud_bad(pud_t pud) |
1da177e4 | 677 | { |
d08de8e2 GS |
678 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
679 | return pmd_bad(__pmd(pud_val(pud))); | |
680 | if (pud_large(pud)) | |
681 | return (pud_val(pud) & ~_REGION_ENTRY_BITS_LARGE) != 0; | |
682 | return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; | |
1da177e4 LT |
683 | } |
684 | ||
1aea9b3f MS |
685 | static inline int p4d_bad(p4d_t p4d) |
686 | { | |
687 | if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) | |
688 | return pud_bad(__pud(p4d_val(p4d))); | |
689 | return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; | |
690 | } | |
691 | ||
4448aaf0 | 692 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 693 | { |
54397bb0 | 694 | return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
695 | } |
696 | ||
4448aaf0 | 697 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 698 | { |
54397bb0 | 699 | return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
700 | } |
701 | ||
7cded342 | 702 | static inline unsigned long pmd_pfn(pmd_t pmd) |
0944fe3f | 703 | { |
152125b7 MS |
704 | unsigned long origin_mask; |
705 | ||
706 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
707 | if (pmd_large(pmd)) | |
708 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
709 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
710 | } |
711 | ||
1ae1c1d0 GS |
712 | #define __HAVE_ARCH_PMD_WRITE |
713 | static inline int pmd_write(pmd_t pmd) | |
714 | { | |
152125b7 MS |
715 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
716 | } | |
717 | ||
718 | static inline int pmd_dirty(pmd_t pmd) | |
719 | { | |
720 | int dirty = 1; | |
721 | if (pmd_large(pmd)) | |
722 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
723 | return dirty; | |
1ae1c1d0 GS |
724 | } |
725 | ||
726 | static inline int pmd_young(pmd_t pmd) | |
727 | { | |
152125b7 MS |
728 | int young = 1; |
729 | if (pmd_large(pmd)) | |
0944fe3f | 730 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 731 | return young; |
1ae1c1d0 GS |
732 | } |
733 | ||
e5098611 | 734 | static inline int pte_present(pte_t pte) |
1da177e4 | 735 | { |
e5098611 MS |
736 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
737 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
738 | } |
739 | ||
e5098611 | 740 | static inline int pte_none(pte_t pte) |
1da177e4 | 741 | { |
e5098611 MS |
742 | /* Bit pattern: pte == 0x400 */ |
743 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
744 | } |
745 | ||
b31288fa KW |
746 | static inline int pte_swap(pte_t pte) |
747 | { | |
a1c843b8 MS |
748 | /* Bit pattern: (pte & 0x201) == 0x200 */ |
749 | return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) | |
750 | == _PAGE_PROTECT; | |
b31288fa KW |
751 | } |
752 | ||
7e675137 NP |
753 | static inline int pte_special(pte_t pte) |
754 | { | |
a08cb629 | 755 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
756 | } |
757 | ||
ba8a9229 | 758 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
759 | static inline int pte_same(pte_t a, pte_t b) |
760 | { | |
761 | return pte_val(a) == pte_val(b); | |
762 | } | |
1da177e4 | 763 | |
b54565b8 MS |
764 | #ifdef CONFIG_NUMA_BALANCING |
765 | static inline int pte_protnone(pte_t pte) | |
766 | { | |
767 | return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); | |
768 | } | |
769 | ||
770 | static inline int pmd_protnone(pmd_t pmd) | |
771 | { | |
772 | /* pmd_large(pmd) implies pmd_present(pmd) */ | |
773 | return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); | |
774 | } | |
775 | #endif | |
776 | ||
5614dd92 MS |
777 | static inline int pte_soft_dirty(pte_t pte) |
778 | { | |
779 | return pte_val(pte) & _PAGE_SOFT_DIRTY; | |
780 | } | |
781 | #define pte_swp_soft_dirty pte_soft_dirty | |
782 | ||
783 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
784 | { | |
785 | pte_val(pte) |= _PAGE_SOFT_DIRTY; | |
786 | return pte; | |
787 | } | |
788 | #define pte_swp_mksoft_dirty pte_mksoft_dirty | |
789 | ||
790 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
791 | { | |
792 | pte_val(pte) &= ~_PAGE_SOFT_DIRTY; | |
793 | return pte; | |
794 | } | |
795 | #define pte_swp_clear_soft_dirty pte_clear_soft_dirty | |
796 | ||
797 | static inline int pmd_soft_dirty(pmd_t pmd) | |
798 | { | |
799 | return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; | |
800 | } | |
801 | ||
802 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
803 | { | |
804 | pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; | |
805 | return pmd; | |
806 | } | |
807 | ||
808 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
809 | { | |
810 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; | |
811 | return pmd; | |
812 | } | |
813 | ||
1da177e4 LT |
814 | /* |
815 | * query functions pte_write/pte_dirty/pte_young only work if | |
816 | * pte_present() is true. Undefined behaviour if not.. | |
817 | */ | |
4448aaf0 | 818 | static inline int pte_write(pte_t pte) |
1da177e4 | 819 | { |
e5098611 | 820 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
821 | } |
822 | ||
4448aaf0 | 823 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 824 | { |
e5098611 | 825 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
826 | } |
827 | ||
4448aaf0 | 828 | static inline int pte_young(pte_t pte) |
1da177e4 | 829 | { |
0944fe3f | 830 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
831 | } |
832 | ||
b31288fa KW |
833 | #define __HAVE_ARCH_PTE_UNUSED |
834 | static inline int pte_unused(pte_t pte) | |
835 | { | |
836 | return pte_val(pte) & _PAGE_UNUSED; | |
837 | } | |
838 | ||
1da177e4 LT |
839 | /* |
840 | * pgd/pmd/pte modification functions | |
841 | */ | |
842 | ||
b2fa47e6 | 843 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 844 | { |
1aea9b3f MS |
845 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) |
846 | pgd_val(*pgd) = _REGION1_ENTRY_EMPTY; | |
847 | } | |
848 | ||
849 | static inline void p4d_clear(p4d_t *p4d) | |
850 | { | |
851 | if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
852 | p4d_val(*p4d) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
853 | } |
854 | ||
b2fa47e6 | 855 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 856 | { |
6252d702 MS |
857 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
858 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
859 | } |
860 | ||
b2fa47e6 | 861 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 862 | { |
54397bb0 | 863 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
864 | } |
865 | ||
4448aaf0 | 866 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 867 | { |
e5098611 | 868 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
869 | } |
870 | ||
871 | /* | |
872 | * The following pte modification functions only work if | |
873 | * pte_present() is true. Undefined behaviour if not.. | |
874 | */ | |
4448aaf0 | 875 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 876 | { |
138c9021 | 877 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 878 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f | 879 | /* |
57d7f939 MS |
880 | * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX |
881 | * has the invalid bit set, clear it again for readable, young pages | |
0944fe3f MS |
882 | */ |
883 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
884 | pte_val(pte) &= ~_PAGE_INVALID; | |
885 | /* | |
57d7f939 MS |
886 | * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page |
887 | * protection bit set, clear it again for writable, dirty pages | |
0944fe3f | 888 | */ |
e5098611 MS |
889 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
890 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
891 | return pte; |
892 | } | |
893 | ||
4448aaf0 | 894 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 895 | { |
e5098611 MS |
896 | pte_val(pte) &= ~_PAGE_WRITE; |
897 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
898 | return pte; |
899 | } | |
900 | ||
4448aaf0 | 901 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 902 | { |
e5098611 MS |
903 | pte_val(pte) |= _PAGE_WRITE; |
904 | if (pte_val(pte) & _PAGE_DIRTY) | |
905 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
906 | return pte; |
907 | } | |
908 | ||
4448aaf0 | 909 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 910 | { |
e5098611 MS |
911 | pte_val(pte) &= ~_PAGE_DIRTY; |
912 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
913 | return pte; |
914 | } | |
915 | ||
4448aaf0 | 916 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 917 | { |
5614dd92 | 918 | pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; |
e5098611 MS |
919 | if (pte_val(pte) & _PAGE_WRITE) |
920 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
921 | return pte; |
922 | } | |
923 | ||
4448aaf0 | 924 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 925 | { |
e5098611 | 926 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 927 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
928 | return pte; |
929 | } | |
930 | ||
4448aaf0 | 931 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 932 | { |
0944fe3f MS |
933 | pte_val(pte) |= _PAGE_YOUNG; |
934 | if (pte_val(pte) & _PAGE_READ) | |
935 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
936 | return pte; |
937 | } | |
938 | ||
7e675137 NP |
939 | static inline pte_t pte_mkspecial(pte_t pte) |
940 | { | |
a08cb629 | 941 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
942 | return pte; |
943 | } | |
944 | ||
84afdcee HC |
945 | #ifdef CONFIG_HUGETLB_PAGE |
946 | static inline pte_t pte_mkhuge(pte_t pte) | |
947 | { | |
e5098611 | 948 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
949 | return pte; |
950 | } | |
951 | #endif | |
952 | ||
34eeaf37 MS |
953 | #define IPTE_GLOBAL 0 |
954 | #define IPTE_LOCAL 1 | |
53e857f3 | 955 | |
118bd31b | 956 | #define IPTE_NODAT 0x400 |
28c807e5 | 957 | #define IPTE_GUEST_ASCE 0x800 |
118bd31b MS |
958 | |
959 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep, | |
28c807e5 MS |
960 | unsigned long opt, unsigned long asce, |
961 | int local) | |
1b948d6c MS |
962 | { |
963 | unsigned long pto = (unsigned long) ptep; | |
964 | ||
118bd31b MS |
965 | if (__builtin_constant_p(opt) && opt == 0) { |
966 | /* Invalidation + TLB flush for the pte */ | |
967 | asm volatile( | |
968 | " .insn rrf,0xb2210000,%[r1],%[r2],0,%[m4]" | |
969 | : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), | |
970 | [m4] "i" (local)); | |
971 | return; | |
972 | } | |
973 | ||
974 | /* Invalidate ptes with options + TLB flush of the ptes */ | |
28c807e5 | 975 | opt = opt | (asce & _ASCE_ORIGIN); |
1b948d6c | 976 | asm volatile( |
118bd31b MS |
977 | " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" |
978 | : [r2] "+a" (address), [r3] "+a" (opt) | |
979 | : [r1] "a" (pto), [m4] "i" (local) : "memory"); | |
1b948d6c MS |
980 | } |
981 | ||
34eeaf37 MS |
982 | static inline void __ptep_ipte_range(unsigned long address, int nr, |
983 | pte_t *ptep, int local) | |
cfb0b241 HC |
984 | { |
985 | unsigned long pto = (unsigned long) ptep; | |
986 | ||
34eeaf37 | 987 | /* Invalidate a range of ptes + TLB flush of the ptes */ |
cfb0b241 HC |
988 | do { |
989 | asm volatile( | |
34eeaf37 MS |
990 | " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" |
991 | : [r2] "+a" (address), [r3] "+a" (nr) | |
992 | : [r1] "a" (pto), [m4] "i" (local) : "memory"); | |
cfb0b241 HC |
993 | } while (nr != 255); |
994 | } | |
995 | ||
0a61b222 | 996 | /* |
ebde765c MS |
997 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush |
998 | * both clear the TLB for the unmapped pte. The reason is that | |
999 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
1000 | * to modify an active pte. The sequence is | |
1001 | * 1) ptep_get_and_clear | |
1002 | * 2) set_pte_at | |
1003 | * 3) flush_tlb_range | |
1004 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1005 | * if the pte is active. The only way how this can be implemented is to | |
1006 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1007 | * is a nop. | |
0a61b222 | 1008 | */ |
ebde765c MS |
1009 | pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); |
1010 | pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); | |
0a61b222 | 1011 | |
0944fe3f MS |
1012 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1013 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1014 | unsigned long addr, pte_t *ptep) | |
1015 | { | |
ebde765c | 1016 | pte_t pte = *ptep; |
0944fe3f | 1017 | |
ebde765c MS |
1018 | pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); |
1019 | return pte_young(pte); | |
0944fe3f MS |
1020 | } |
1021 | ||
1022 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
1023 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1024 | unsigned long address, pte_t *ptep) | |
1025 | { | |
1026 | return ptep_test_and_clear_young(vma, address, ptep); | |
1027 | } | |
1028 | ||
ba8a9229 | 1029 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
b2fa47e6 | 1030 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
ebde765c | 1031 | unsigned long addr, pte_t *ptep) |
b2fa47e6 | 1032 | { |
ebde765c | 1033 | return ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); |
b2fa47e6 MS |
1034 | } |
1035 | ||
1036 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
ebde765c MS |
1037 | pte_t ptep_modify_prot_start(struct mm_struct *, unsigned long, pte_t *); |
1038 | void ptep_modify_prot_commit(struct mm_struct *, unsigned long, pte_t *, pte_t); | |
ba8a9229 MS |
1039 | |
1040 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 | 1041 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
ebde765c | 1042 | unsigned long addr, pte_t *ptep) |
f0e47c22 | 1043 | { |
ebde765c | 1044 | return ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); |
1da177e4 LT |
1045 | } |
1046 | ||
ba8a9229 MS |
1047 | /* |
1048 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1049 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1050 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1051 | * cannot be accessed while the batched unmap is running. In this case | |
1052 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1053 | */ | |
1054 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1055 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
ebde765c | 1056 | unsigned long addr, |
ba8a9229 | 1057 | pte_t *ptep, int full) |
1da177e4 | 1058 | { |
ebde765c MS |
1059 | if (full) { |
1060 | pte_t pte = *ptep; | |
1061 | *ptep = __pte(_PAGE_INVALID); | |
1062 | return pte; | |
b2fa47e6 | 1063 | } |
ebde765c | 1064 | return ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); |
1da177e4 LT |
1065 | } |
1066 | ||
ba8a9229 | 1067 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
ebde765c MS |
1068 | static inline void ptep_set_wrprotect(struct mm_struct *mm, |
1069 | unsigned long addr, pte_t *ptep) | |
b2fa47e6 | 1070 | { |
b2fa47e6 MS |
1071 | pte_t pte = *ptep; |
1072 | ||
ebde765c MS |
1073 | if (pte_write(pte)) |
1074 | ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); | |
b2fa47e6 | 1075 | } |
ba8a9229 MS |
1076 | |
1077 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 | 1078 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
ebde765c | 1079 | unsigned long addr, pte_t *ptep, |
b2fa47e6 MS |
1080 | pte_t entry, int dirty) |
1081 | { | |
ebde765c | 1082 | if (pte_same(*ptep, entry)) |
b2fa47e6 | 1083 | return 0; |
ebde765c MS |
1084 | ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); |
1085 | return 1; | |
1086 | } | |
b2fa47e6 | 1087 | |
1e133ab2 MS |
1088 | /* |
1089 | * Additional functions to handle KVM guest page tables | |
1090 | */ | |
1091 | void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1092 | pte_t *ptep, pte_t entry); | |
1093 | void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | |
4be130a0 MS |
1094 | void ptep_notify(struct mm_struct *mm, unsigned long addr, |
1095 | pte_t *ptep, unsigned long bits); | |
b2d73b2a | 1096 | int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, |
4be130a0 | 1097 | pte_t *ptep, int prot, unsigned long bit); |
1e133ab2 MS |
1098 | void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, |
1099 | pte_t *ptep , int reset); | |
1100 | void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | |
4be130a0 | 1101 | int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, |
a9d23e71 | 1102 | pte_t *sptep, pte_t *tptep, pte_t pte); |
4be130a0 | 1103 | void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); |
1e133ab2 MS |
1104 | |
1105 | bool test_and_clear_guest_dirty(struct mm_struct *mm, unsigned long address); | |
1106 | int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, | |
1107 | unsigned char key, bool nq); | |
1824c723 DH |
1108 | int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, |
1109 | unsigned char key, unsigned char *oldkey, | |
1110 | bool nq, bool mr, bool mc); | |
a7e19ab5 | 1111 | int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); |
154c8c19 DH |
1112 | int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, |
1113 | unsigned char *key); | |
b2fa47e6 | 1114 | |
2d42f947 CI |
1115 | int set_pgste_bits(struct mm_struct *mm, unsigned long addr, |
1116 | unsigned long bits, unsigned long value); | |
1117 | int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); | |
1118 | int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, | |
1119 | unsigned long *oldpte, unsigned long *oldpgste); | |
1120 | ||
ebde765c MS |
1121 | /* |
1122 | * Certain architectures need to do special things when PTEs | |
1123 | * within a page table are directly modified. Thus, the following | |
1124 | * hook is made available. | |
1125 | */ | |
1126 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1127 | pte_t *ptep, pte_t entry) | |
1128 | { | |
57d7f939 MS |
1129 | if (!MACHINE_HAS_NX) |
1130 | pte_val(entry) &= ~_PAGE_NOEXEC; | |
a8f60d1f CB |
1131 | if (pte_present(entry)) |
1132 | pte_val(entry) &= ~_PAGE_UNUSED; | |
ebde765c | 1133 | if (mm_has_pgste(mm)) |
1e133ab2 | 1134 | ptep_set_pte_at(mm, addr, ptep, entry); |
ebde765c | 1135 | else |
abf09bed | 1136 | *ptep = entry; |
b2fa47e6 | 1137 | } |
1da177e4 | 1138 | |
1da177e4 LT |
1139 | /* |
1140 | * Conversion functions: convert a page and protection to a page entry, | |
1141 | * and a page entry and page directory to the page they refer to. | |
1142 | */ | |
1143 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1144 | { | |
1145 | pte_t __pte; | |
1146 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1147 | return pte_mkyoung(__pte); |
1da177e4 LT |
1148 | } |
1149 | ||
2dcea57a HC |
1150 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1151 | { | |
0b2b6e1d | 1152 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1153 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1154 | |
e5098611 MS |
1155 | if (pte_write(__pte) && PageDirty(page)) |
1156 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1157 | return __pte; |
2dcea57a HC |
1158 | } |
1159 | ||
190a1d72 | 1160 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1aea9b3f | 1161 | #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) |
190a1d72 MS |
1162 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
1163 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1164 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1165 | |
190a1d72 MS |
1166 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1167 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1168 | |
190a1d72 MS |
1169 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1170 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
1aea9b3f | 1171 | #define p4d_deref(pud) (p4d_val(pud) & _REGION_ENTRY_ORIGIN) |
5a216a20 | 1172 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1173 | |
1aea9b3f | 1174 | static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) |
5a216a20 | 1175 | { |
1aea9b3f MS |
1176 | p4d_t *p4d = (p4d_t *) pgd; |
1177 | ||
1178 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) | |
1179 | p4d = (p4d_t *) pgd_deref(*pgd); | |
1180 | return p4d + p4d_index(address); | |
1181 | } | |
1182 | ||
1183 | static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) | |
1184 | { | |
1185 | pud_t *pud = (pud_t *) p4d; | |
1186 | ||
1187 | if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1188 | pud = (pud_t *) p4d_deref(*p4d); | |
1189 | return pud + pud_index(address); | |
5a216a20 | 1190 | } |
1da177e4 | 1191 | |
190a1d72 | 1192 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1193 | { |
6252d702 | 1194 | pmd_t *pmd = (pmd_t *) pud; |
1aea9b3f | 1195 | |
6252d702 MS |
1196 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
1197 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1198 | return pmd + pmd_index(address); |
1da177e4 LT |
1199 | } |
1200 | ||
190a1d72 MS |
1201 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1202 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1203 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1204 | |
152125b7 | 1205 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
d08de8e2 | 1206 | #define pud_page(pud) pfn_to_page(pud_pfn(pud)) |
1aea9b3f | 1207 | #define p4d_page(pud) pfn_to_page(p4d_pfn(p4d)) |
1da177e4 | 1208 | |
190a1d72 MS |
1209 | /* Find an entry in the lowest level page table.. */ |
1210 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1211 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1212 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1213 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1214 | |
152125b7 | 1215 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1216 | { |
152125b7 MS |
1217 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1218 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1219 | return pmd; | |
1220 | } | |
1221 | ||
1222 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1223 | { | |
1224 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1225 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1226 | return pmd; | |
1227 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1228 | return pmd; | |
1229 | } | |
1230 | ||
1231 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1232 | { | |
1233 | if (pmd_large(pmd)) { | |
1234 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1235 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1236 | } |
1237 | return pmd; | |
1238 | } | |
1239 | ||
1240 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1241 | { | |
1242 | if (pmd_large(pmd)) { | |
5614dd92 MS |
1243 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | |
1244 | _SEGMENT_ENTRY_SOFT_DIRTY; | |
152125b7 MS |
1245 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) |
1246 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1247 | } | |
1248 | return pmd; | |
1249 | } | |
1250 | ||
9e20b4da HC |
1251 | static inline pud_t pud_wrprotect(pud_t pud) |
1252 | { | |
1253 | pud_val(pud) &= ~_REGION3_ENTRY_WRITE; | |
1254 | pud_val(pud) |= _REGION_ENTRY_PROTECT; | |
1255 | return pud; | |
1256 | } | |
1257 | ||
1258 | static inline pud_t pud_mkwrite(pud_t pud) | |
1259 | { | |
1260 | pud_val(pud) |= _REGION3_ENTRY_WRITE; | |
1261 | if (pud_large(pud) && !(pud_val(pud) & _REGION3_ENTRY_DIRTY)) | |
1262 | return pud; | |
1263 | pud_val(pud) &= ~_REGION_ENTRY_PROTECT; | |
1264 | return pud; | |
1265 | } | |
1266 | ||
1267 | static inline pud_t pud_mkclean(pud_t pud) | |
1268 | { | |
1269 | if (pud_large(pud)) { | |
1270 | pud_val(pud) &= ~_REGION3_ENTRY_DIRTY; | |
1271 | pud_val(pud) |= _REGION_ENTRY_PROTECT; | |
1272 | } | |
1273 | return pud; | |
1274 | } | |
1275 | ||
1276 | static inline pud_t pud_mkdirty(pud_t pud) | |
1277 | { | |
1278 | if (pud_large(pud)) { | |
1279 | pud_val(pud) |= _REGION3_ENTRY_DIRTY | | |
1280 | _REGION3_ENTRY_SOFT_DIRTY; | |
1281 | if (pud_val(pud) & _REGION3_ENTRY_WRITE) | |
1282 | pud_val(pud) &= ~_REGION_ENTRY_PROTECT; | |
1283 | } | |
1284 | return pud; | |
1285 | } | |
1286 | ||
1287 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) | |
1288 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) | |
1289 | { | |
1290 | /* | |
57d7f939 MS |
1291 | * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX |
1292 | * (see __Pxxx / __Sxxx). Convert to segment table entry format. | |
9e20b4da HC |
1293 | */ |
1294 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1295 | return pgprot_val(SEGMENT_NONE); | |
57d7f939 MS |
1296 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) |
1297 | return pgprot_val(SEGMENT_RO); | |
1298 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) | |
1299 | return pgprot_val(SEGMENT_RX); | |
1300 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) | |
1301 | return pgprot_val(SEGMENT_RW); | |
1302 | return pgprot_val(SEGMENT_RWX); | |
9e20b4da HC |
1303 | } |
1304 | ||
152125b7 MS |
1305 | static inline pmd_t pmd_mkyoung(pmd_t pmd) |
1306 | { | |
1307 | if (pmd_large(pmd)) { | |
0944fe3f | 1308 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1309 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1310 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1311 | } |
0944fe3f MS |
1312 | return pmd; |
1313 | } | |
1314 | ||
1315 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1316 | { | |
152125b7 | 1317 | if (pmd_large(pmd)) { |
0944fe3f MS |
1318 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1319 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1320 | } | |
0944fe3f MS |
1321 | return pmd; |
1322 | } | |
1323 | ||
1ae1c1d0 GS |
1324 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1325 | { | |
152125b7 MS |
1326 | if (pmd_large(pmd)) { |
1327 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1328 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
fecffad2 | 1329 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SOFT_DIRTY; |
152125b7 MS |
1330 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1331 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1332 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1333 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1334 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1335 | return pmd; | |
1336 | } | |
1337 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1338 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1339 | return pmd; | |
1340 | } | |
1341 | ||
106c992a | 1342 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1343 | { |
106c992a GS |
1344 | pmd_t __pmd; |
1345 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1346 | return __pmd; |
1ae1c1d0 GS |
1347 | } |
1348 | ||
106c992a GS |
1349 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1350 | ||
1b948d6c MS |
1351 | static inline void __pmdp_csp(pmd_t *pmdp) |
1352 | { | |
4ccccc52 HC |
1353 | csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), |
1354 | pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); | |
1b948d6c MS |
1355 | } |
1356 | ||
47e4d851 MS |
1357 | #define IDTE_GLOBAL 0 |
1358 | #define IDTE_LOCAL 1 | |
d08de8e2 | 1359 | |
118bd31b MS |
1360 | #define IDTE_PTOA 0x0800 |
1361 | #define IDTE_NODAT 0x1000 | |
28c807e5 | 1362 | #define IDTE_GUEST_ASCE 0x2000 |
118bd31b MS |
1363 | |
1364 | static inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, | |
28c807e5 MS |
1365 | unsigned long opt, unsigned long asce, |
1366 | int local) | |
1b948d6c MS |
1367 | { |
1368 | unsigned long sto; | |
1369 | ||
118bd31b | 1370 | sto = (unsigned long) pmdp - pmd_index(addr) * sizeof(pmd_t); |
28c807e5 MS |
1371 | if (__builtin_constant_p(opt) && opt == 0) { |
1372 | /* flush without guest asce */ | |
1373 | asm volatile( | |
1374 | " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" | |
1375 | : "+m" (*pmdp) | |
1376 | : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), | |
1377 | [m4] "i" (local) | |
1378 | : "cc" ); | |
1379 | } else { | |
1380 | /* flush with guest asce */ | |
1381 | asm volatile( | |
1382 | " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" | |
1383 | : "+m" (*pmdp) | |
1384 | : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), | |
1385 | [r3] "a" (asce), [m4] "i" (local) | |
1386 | : "cc" ); | |
1387 | } | |
1b948d6c MS |
1388 | } |
1389 | ||
118bd31b | 1390 | static inline void __pudp_idte(unsigned long addr, pud_t *pudp, |
28c807e5 MS |
1391 | unsigned long opt, unsigned long asce, |
1392 | int local) | |
d08de8e2 GS |
1393 | { |
1394 | unsigned long r3o; | |
1395 | ||
118bd31b | 1396 | r3o = (unsigned long) pudp - pud_index(addr) * sizeof(pud_t); |
d08de8e2 | 1397 | r3o |= _ASCE_TYPE_REGION3; |
28c807e5 MS |
1398 | if (__builtin_constant_p(opt) && opt == 0) { |
1399 | /* flush without guest asce */ | |
1400 | asm volatile( | |
1401 | " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" | |
1402 | : "+m" (*pudp) | |
1403 | : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), | |
1404 | [m4] "i" (local) | |
1405 | : "cc"); | |
1406 | } else { | |
1407 | /* flush with guest asce */ | |
1408 | asm volatile( | |
1409 | " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" | |
1410 | : "+m" (*pudp) | |
1411 | : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), | |
1412 | [r3] "a" (asce), [m4] "i" (local) | |
1413 | : "cc" ); | |
1414 | } | |
d08de8e2 GS |
1415 | } |
1416 | ||
227be799 MS |
1417 | pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); |
1418 | pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); | |
d08de8e2 | 1419 | pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); |
1b948d6c | 1420 | |
227be799 MS |
1421 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1422 | ||
1423 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
1424 | void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
1425 | pgtable_t pgtable); | |
1426 | ||
1427 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
1428 | pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); | |
1b948d6c | 1429 | |
227be799 MS |
1430 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1431 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1432 | unsigned long addr, pmd_t *pmdp, | |
1433 | pmd_t entry, int dirty) | |
3eabaee9 | 1434 | { |
227be799 | 1435 | VM_BUG_ON(addr & ~HPAGE_MASK); |
3eabaee9 | 1436 | |
227be799 MS |
1437 | entry = pmd_mkyoung(entry); |
1438 | if (dirty) | |
1439 | entry = pmd_mkdirty(entry); | |
1440 | if (pmd_val(*pmdp) == pmd_val(entry)) | |
1441 | return 0; | |
1442 | pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); | |
1443 | return 1; | |
3eabaee9 MS |
1444 | } |
1445 | ||
227be799 MS |
1446 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1447 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1448 | unsigned long addr, pmd_t *pmdp) | |
1449 | { | |
1450 | pmd_t pmd = *pmdp; | |
106c992a | 1451 | |
227be799 MS |
1452 | pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); |
1453 | return pmd_young(pmd); | |
1454 | } | |
106c992a | 1455 | |
227be799 MS |
1456 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH |
1457 | static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
1458 | unsigned long addr, pmd_t *pmdp) | |
1459 | { | |
1460 | VM_BUG_ON(addr & ~HPAGE_MASK); | |
1461 | return pmdp_test_and_clear_young(vma, addr, pmdp); | |
1462 | } | |
106c992a | 1463 | |
106c992a GS |
1464 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
1465 | pmd_t *pmdp, pmd_t entry) | |
1466 | { | |
57d7f939 MS |
1467 | if (!MACHINE_HAS_NX) |
1468 | pmd_val(entry) &= ~_SEGMENT_ENTRY_NOEXEC; | |
106c992a GS |
1469 | *pmdp = entry; |
1470 | } | |
1471 | ||
1472 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1473 | { | |
1474 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1475 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1476 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1477 | return pmd; |
1478 | } | |
1479 | ||
8809aa2d AK |
1480 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
1481 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
227be799 | 1482 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1483 | { |
54397bb0 | 1484 | return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); |
1ae1c1d0 GS |
1485 | } |
1486 | ||
8809aa2d AK |
1487 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1488 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, | |
227be799 | 1489 | unsigned long addr, |
8809aa2d | 1490 | pmd_t *pmdp, int full) |
fcbe08d6 | 1491 | { |
227be799 MS |
1492 | if (full) { |
1493 | pmd_t pmd = *pmdp; | |
54397bb0 | 1494 | *pmdp = __pmd(_SEGMENT_ENTRY_EMPTY); |
227be799 MS |
1495 | return pmd; |
1496 | } | |
54397bb0 | 1497 | return pmdp_xchg_lazy(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); |
fcbe08d6 MS |
1498 | } |
1499 | ||
8809aa2d AK |
1500 | #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
1501 | static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
227be799 | 1502 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1503 | { |
227be799 | 1504 | return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); |
1ae1c1d0 GS |
1505 | } |
1506 | ||
1507 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1508 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
227be799 | 1509 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1510 | { |
91c575b3 GS |
1511 | pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); |
1512 | ||
1513 | pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); | |
1ae1c1d0 GS |
1514 | } |
1515 | ||
be328650 GS |
1516 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1517 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
227be799 | 1518 | unsigned long addr, pmd_t *pmdp) |
be328650 GS |
1519 | { |
1520 | pmd_t pmd = *pmdp; | |
1521 | ||
227be799 MS |
1522 | if (pmd_write(pmd)) |
1523 | pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); | |
be328650 GS |
1524 | } |
1525 | ||
f28b6ff8 AK |
1526 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1527 | unsigned long address, | |
1528 | pmd_t *pmdp) | |
1529 | { | |
8809aa2d | 1530 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
f28b6ff8 AK |
1531 | } |
1532 | #define pmdp_collapse_flush pmdp_collapse_flush | |
1533 | ||
1ae1c1d0 GS |
1534 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1535 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1536 | ||
1537 | static inline int pmd_trans_huge(pmd_t pmd) | |
1538 | { | |
1539 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1540 | } | |
1541 | ||
fd8cfd30 | 1542 | #define has_transparent_hugepage has_transparent_hugepage |
1ae1c1d0 GS |
1543 | static inline int has_transparent_hugepage(void) |
1544 | { | |
466178fc | 1545 | return MACHINE_HAS_EDAT1 ? 1 : 0; |
1ae1c1d0 | 1546 | } |
75077afb GS |
1547 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1548 | ||
1da177e4 | 1549 | /* |
1da177e4 LT |
1550 | * 64 bit swap entry format: |
1551 | * A page-table entry has some bits we have to treat in a special way. | |
4e0a6412 | 1552 | * Bits 52 and bit 55 have to be zero, otherwise a specification |
1da177e4 | 1553 | * exception will occur instead of a page translation exception. The |
4e0a6412 | 1554 | * specification exception has the bad habit not to store necessary |
1da177e4 | 1555 | * information in the lowcore. |
a1c843b8 MS |
1556 | * Bits 54 and 63 are used to indicate the page type. |
1557 | * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 | |
1558 | * This leaves the bits 0-51 and bits 56-62 to store type and offset. | |
1559 | * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 | |
1560 | * for the offset. | |
1561 | * | offset |01100|type |00| | |
1562 | * |0000000000111111111122222222223333333333444444444455|55555|55566|66| | |
1563 | * |0123456789012345678901234567890123456789012345678901|23456|78901|23| | |
1da177e4 | 1564 | */ |
5a79859a | 1565 | |
a1c843b8 MS |
1566 | #define __SWP_OFFSET_MASK ((1UL << 52) - 1) |
1567 | #define __SWP_OFFSET_SHIFT 12 | |
1568 | #define __SWP_TYPE_MASK ((1UL << 5) - 1) | |
1569 | #define __SWP_TYPE_SHIFT 2 | |
5a79859a | 1570 | |
4448aaf0 | 1571 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1572 | { |
1573 | pte_t pte; | |
a1c843b8 MS |
1574 | |
1575 | pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; | |
1576 | pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; | |
1577 | pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; | |
1da177e4 LT |
1578 | return pte; |
1579 | } | |
1580 | ||
a1c843b8 MS |
1581 | static inline unsigned long __swp_type(swp_entry_t entry) |
1582 | { | |
1583 | return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; | |
1584 | } | |
1585 | ||
1586 | static inline unsigned long __swp_offset(swp_entry_t entry) | |
1587 | { | |
1588 | return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; | |
1589 | } | |
1590 | ||
1591 | static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) | |
1592 | { | |
1593 | return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; | |
1594 | } | |
1da177e4 LT |
1595 | |
1596 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1597 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1598 | ||
1da177e4 LT |
1599 | #define kern_addr_valid(addr) (1) |
1600 | ||
17f34580 HC |
1601 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1602 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1603 | extern int s390_enable_sie(void); |
3ac8e380 | 1604 | extern int s390_enable_skey(void); |
a13cff31 | 1605 | extern void s390_reset_cmma(struct mm_struct *mm); |
f4eb07c1 | 1606 | |
1f6b83e5 MS |
1607 | /* s390 has a private copy of get unmapped area to deal with cache synonyms */ |
1608 | #define HAVE_ARCH_UNMAPPED_AREA | |
1609 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1610 | ||
1da177e4 LT |
1611 | /* |
1612 | * No page table caches to initialise | |
1613 | */ | |
765a0cac HC |
1614 | static inline void pgtable_cache_init(void) { } |
1615 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1616 | |
1da177e4 LT |
1617 | #include <asm-generic/pgtable.h> |
1618 | ||
1619 | #endif /* _S390_PAGE_H */ |