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s390: remove all code using the access register mode
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 2/*
1da177e4 3 * S390 version
a53c8fab 4 * Copyright IBM Corp. 1999
1da177e4
LT
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12#ifndef __ASM_S390_PROCESSOR_H
13#define __ASM_S390_PROCESSOR_H
14
92778b99
HC
15#include <linux/const.h>
16
d3a73acb 17#define CIF_MCCK_PENDING 0 /* machine check handling is pending */
606aa4aa 18#define CIF_ASCE_PRIMARY 1 /* primary asce needs fixup / uaccess */
b5a882fc
HC
19#define CIF_ASCE_SECONDARY 2 /* secondary asce needs fixup / uaccess */
20#define CIF_NOHZ_DELAY 3 /* delay HZ disable for a tick */
21#define CIF_FPU 4 /* restore FPU registers */
22#define CIF_IGNORE_IRQ 5 /* ignore interrupt (for udelay) */
23#define CIF_ENABLED_WAIT 6 /* in enabled wait state */
c929500d 24#define CIF_MCCK_GUEST 7 /* machine check happening in guest */
1887aa07 25#define CIF_DEDICATED_CPU 8 /* this CPU is dedicated */
d3a73acb 26
92778b99 27#define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING)
606aa4aa 28#define _CIF_ASCE_PRIMARY _BITUL(CIF_ASCE_PRIMARY)
b5a882fc 29#define _CIF_ASCE_SECONDARY _BITUL(CIF_ASCE_SECONDARY)
92778b99
HC
30#define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY)
31#define _CIF_FPU _BITUL(CIF_FPU)
32#define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ)
419123f9 33#define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT)
c929500d 34#define _CIF_MCCK_GUEST _BITUL(CIF_MCCK_GUEST)
1887aa07 35#define _CIF_DEDICATED_CPU _BITUL(CIF_DEDICATED_CPU)
d3a73acb 36
eb608fb3
HC
37#ifndef __ASSEMBLY__
38
edd53787 39#include <linux/linkage.h>
a0616cde 40#include <linux/irqflags.h>
e86a6ed6 41#include <asm/cpu.h>
25097bf1 42#include <asm/page.h>
1da177e4 43#include <asm/ptrace.h>
25097bf1 44#include <asm/setup.h>
e4b8b3f3 45#include <asm/runtime_instr.h>
b0753902
HB
46#include <asm/fpu/types.h>
47#include <asm/fpu/internal.h>
1da177e4 48
d3a73acb
MS
49static inline void set_cpu_flag(int flag)
50{
ac25e790 51 S390_lowcore.cpu_flags |= (1UL << flag);
d3a73acb
MS
52}
53
54static inline void clear_cpu_flag(int flag)
55{
ac25e790 56 S390_lowcore.cpu_flags &= ~(1UL << flag);
d3a73acb
MS
57}
58
59static inline int test_cpu_flag(int flag)
60{
ac25e790 61 return !!(S390_lowcore.cpu_flags & (1UL << flag));
d3a73acb
MS
62}
63
419123f9
MS
64/*
65 * Test CIF flag of another CPU. The caller needs to ensure that
66 * CPU hotplug can not happen, e.g. by disabling preemption.
67 */
68static inline int test_cpu_flag_of(int flag, int cpu)
69{
c667aeac 70 struct lowcore *lc = lowcore_ptr[cpu];
419123f9
MS
71 return !!(lc->cpu_flags & (1UL << flag));
72}
73
fe0f4976
MS
74#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
75
1da177e4
LT
76/*
77 * Default implementation of macro that returns current
78 * instruction pointer ("program counter").
79 */
94c12cc7 80#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4 81
e86a6ed6 82static inline void get_cpu_id(struct cpuid *ptr)
72960a02 83{
987bcdac 84 asm volatile("stidp %0" : "=Q" (*ptr));
72960a02
MH
85}
86
097a116c
HC
87void s390_adjust_jiffies(void);
88void s390_update_cpu_mhz(void);
89void cpu_detect_mhz_feature(void);
90
638ad34a
MS
91extern const struct seq_operations cpuinfo_op;
92extern int sysctl_ieee_emulation_warnings;
65f22a90 93extern void execve_tail(void);
1da177e4 94
1da177e4 95/*
f481bfaf 96 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4 97 */
1da177e4 98
ee71d16d 99#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \
1aea9b3f 100 (1UL << 31) : -PAGE_SIZE)
5a216a20
MS
101#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
102 (1UL << 30) : (1UL << 41))
103#define TASK_SIZE TASK_SIZE_OF(current)
1aea9b3f 104#define TASK_SIZE_MAX (-PAGE_SIZE)
1da177e4 105
ee71d16d
MS
106#define STACK_TOP (test_thread_flag(TIF_31BIT) ? \
107 (1UL << 31) : (1UL << 42))
6252d702 108#define STACK_TOP_MAX (1UL << 42)
922a70d3 109
1da177e4
LT
110#define HAVE_ARCH_PICK_MMAP_LAYOUT
111
0aaba41b 112typedef unsigned int mm_segment_t;
1da177e4
LT
113
114/*
115 * Thread structure
116 */
117struct thread_struct {
1da177e4
LT
118 unsigned int acrs[NUM_ACRS];
119 unsigned long ksp; /* kernel stack pointer */
90c53e65 120 unsigned long user_timer; /* task cputime in user space */
b7394a5f 121 unsigned long guest_timer; /* task cputime in kvm guest */
90c53e65 122 unsigned long system_timer; /* task cputime in kernel space */
b7394a5f
MS
123 unsigned long hardirq_timer; /* task cputime in hardirq context */
124 unsigned long softirq_timer; /* task cputime in softirq context */
ef280c85 125 unsigned long sys_call_table; /* system call table address */
1da177e4 126 mm_segment_t mm_segment;
e5992f2e 127 unsigned long gmap_addr; /* address of last gmap fault. */
4be130a0 128 unsigned int gmap_write_flag; /* gmap fault write indication */
4a494439 129 unsigned int gmap_int_code; /* int code of last gmap fault */
24eb3a82 130 unsigned int gmap_pfault; /* signal of a pending guest pfault */
f8fc82b4 131 /* Per-thread information related to debugging */
5e9a2692
MS
132 struct per_regs per_user; /* User specified PER registers */
133 struct per_event per_event; /* Cause of the last PER trap */
d35339a4 134 unsigned long per_flags; /* Flags to control debug behavior */
f8fc82b4 135 unsigned int system_call; /* system call number in signal */
ef280c85 136 unsigned long last_break; /* last breaking-event-address. */
1da177e4
LT
137 /* pfault_wait is used to block the process on a pfault event */
138 unsigned long pfault_wait;
f2db2e6c 139 struct list_head list;
e4b8b3f3
JG
140 /* cpu runtime instrumentation */
141 struct runtime_instr_cb *ri_cb;
916cda1a
MS
142 struct gs_cb *gs_cb; /* Current guarded storage cb */
143 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
d35339a4 144 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
3f6813b9
MS
145 /*
146 * Warning: 'fpu' is dynamically-sized. It *MUST* be at
147 * the end.
148 */
149 struct fpu fpu; /* FP and VX register save area */
1da177e4
LT
150};
151
64597f9d
MM
152/* Flag to disable transactions. */
153#define PER_FLAG_NO_TE 1UL
154/* Flag to enable random transaction aborts. */
155#define PER_FLAG_TE_ABORT_RAND 2UL
156/* Flag to specify random transaction abort mode:
157 * - abort each transaction at a random instruction before TEND if set.
158 * - abort random transactions at a random instruction if cleared.
159 */
160#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
d35339a4 161
1da177e4
LT
162typedef struct thread_struct thread_struct;
163
164/*
165 * Stack layout of a C stack frame.
166 */
167#ifndef __PACK_STACK
168struct stack_frame {
169 unsigned long back_chain;
170 unsigned long empty1[5];
171 unsigned long gprs[10];
172 unsigned int empty2[8];
173};
174#else
175struct stack_frame {
176 unsigned long empty1[5];
177 unsigned int empty2[8];
178 unsigned long gprs[10];
179 unsigned long back_chain;
180};
181#endif
182
183#define ARCH_MIN_TASKALIGN 8
184
6f3fa3f0
MS
185#define INIT_THREAD { \
186 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
3f6813b9 187 .fpu.regs = (void *) init_task.thread.fpu.fprs, \
6f3fa3f0 188}
1da177e4
LT
189
190/*
191 * Do necessary setup to start up a new thread.
192 */
b50511e4 193#define start_thread(regs, new_psw, new_stackp) do { \
e258d719 194 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
fecc868a 195 regs->psw.addr = new_psw; \
b50511e4 196 regs->gprs[15] = new_stackp; \
65f22a90 197 execve_tail(); \
63506c41
MS
198} while (0)
199
b50511e4 200#define start_thread31(regs, new_psw, new_stackp) do { \
e258d719 201 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
fecc868a 202 regs->psw.addr = new_psw; \
b50511e4 203 regs->gprs[15] = new_stackp; \
723cacbd 204 crst_table_downgrade(current->mm); \
65f22a90 205 execve_tail(); \
1da177e4
LT
206} while (0)
207
1da177e4
LT
208/* Forward declaration, a strange C thing */
209struct task_struct;
210struct mm_struct;
df5f8314 211struct seq_file;
b5a882fc 212struct pt_regs;
1da177e4 213
d0208639 214typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable);
758d39eb
HC
215void dump_trace(dump_trace_func_t func, void *data,
216 struct task_struct *task, unsigned long sp);
b5a882fc 217void show_registers(struct pt_regs *regs);
758d39eb 218
5a79859a 219void show_cacheinfo(struct seq_file *m);
6668022c 220
1da177e4 221/* Free all resources held by a thread. */
8076428f 222static inline void release_thread(struct task_struct *tsk) { }
1da177e4 223
7b83c629
HC
224/* Free guarded storage control block */
225void guarded_storage_release(struct task_struct *tsk);
916cda1a 226
1da177e4 227unsigned long get_wchan(struct task_struct *p);
c7584fb6 228#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120 229 (task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6
AV
230#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
231#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4 232
5ebf250d
HC
233/* Has task runtime instrumentation enabled ? */
234#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
235
76737ce1
HC
236static inline unsigned long current_stack_pointer(void)
237{
238 unsigned long sp;
239
240 asm volatile("la %0,0(15)" : "=a" (sp));
241 return sp;
242}
243
a0616cde
DH
244static inline unsigned short stap(void)
245{
246 unsigned short cpu_address;
247
248 asm volatile("stap %0" : "=m" (cpu_address));
249 return cpu_address;
250}
251
1da177e4
LT
252/*
253 * Give up the time slice of the virtual PU.
254 */
6d0d2878 255#define cpu_relax_yield cpu_relax_yield
79ab11cd 256void cpu_relax_yield(void);
1da177e4 257
22b6430d 258#define cpu_relax() barrier()
083986e8 259
097a116c
HC
260#define ECAG_CACHE_ATTRIBUTE 0
261#define ECAG_CPU_ATTRIBUTE 1
262
263static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
264{
265 unsigned long val;
266
267 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
268 : "=d" (val) : "a" (asi << 8 | parm));
269 return val;
270}
271
dc74d7f9
HC
272static inline void psw_set_key(unsigned int key)
273{
274 asm volatile("spka 0(%0)" : : "d" (key));
275}
276
77fa2245
HC
277/*
278 * Set PSW to specified value.
279 */
280static inline void __load_psw(psw_t psw)
281{
987bcdac 282 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245
HC
283}
284
1da177e4
LT
285/*
286 * Set PSW mask to specified value, while leaving the
287 * PSW addr pointing to the next instruction.
288 */
ecbafda8 289static inline void __load_psw_mask(unsigned long mask)
1da177e4
LT
290{
291 unsigned long addr;
1da177e4 292 psw_t psw;
77fa2245 293
1da177e4
LT
294 psw.mask = mask;
295
94c12cc7
MS
296 asm volatile(
297 " larl %0,1f\n"
987bcdac
MS
298 " stg %0,%O1+8(%R1)\n"
299 " lpswe %1\n"
1da177e4 300 "1:"
987bcdac 301 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4 302}
ccf45caf 303
22362a0e
MS
304/*
305 * Extract current PSW mask
306 */
307static inline unsigned long __extract_psw(void)
308{
309 unsigned int reg1, reg2;
310
311 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
312 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
313}
314
ecbafda8
HC
315static inline void local_mcck_enable(void)
316{
317 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
318}
319
320static inline void local_mcck_disable(void)
321{
322 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
323}
324
ccf45caf
MS
325/*
326 * Rewind PSW instruction address by specified number of bytes.
327 */
328static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
329{
ccf45caf
MS
330 unsigned long mask;
331
332 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
333 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
334 (1UL << 24) - 1;
335 return (psw.addr - ilc) & mask;
ccf45caf 336}
b5f87f15
MS
337
338/*
339 * Function to stop a processor until the next interrupt occurs
340 */
341void enabled_wait(void);
342
1da177e4
LT
343/*
344 * Function to drop a processor into disabled wait state
345 */
ff2d8b19 346static inline void __noreturn disabled_wait(unsigned long code)
1da177e4 347{
f9e6edfb
HC
348 psw_t psw;
349
350 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
351 psw.addr = code;
352 __load_psw(psw);
edd53787 353 while (1);
1da177e4
LT
354}
355
ab14de6c
HC
356/*
357 * Basic Machine Check/Program Check Handler.
358 */
359
360extern void s390_base_mcck_handler(void);
361extern void s390_base_pgm_handler(void);
362extern void s390_base_ext_handler(void);
363
364extern void (*s390_base_mcck_handler_fn)(void);
365extern void (*s390_base_pgm_handler_fn)(void);
366extern void (*s390_base_ext_handler_fn)(void);
367
dfd54cbc
HC
368#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
369
fbe76568
HC
370extern int memcpy_real(void *, void *, size_t);
371extern void memcpy_absolute(void *, void *, size_t);
372
1228f7be 373#define mem_assign_absolute(dest, val) do { \
fbe76568
HC
374 __typeof__(dest) __tmp = (val); \
375 \
376 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
377 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
1228f7be 378} while (0)
fbe76568 379
eb608fb3
HC
380#endif /* __ASSEMBLY__ */
381
382#endif /* __ASM_S390_PROCESSOR_H */