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1da177e4
LT
1#ifndef _S390_RWSEM_H
2#define _S390_RWSEM_H
3
4/*
1da177e4 5 * S390 version
a53c8fab 6 * Copyright IBM Corp. 2002
1da177e4
LT
7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Based on asm-alpha/semaphore.h and asm-i386/rwsem.h
10 */
11
12/*
13 *
14 * The MSW of the count is the negated number of active writers and waiting
15 * lockers, and the LSW is the total number of active locks
16 *
17 * The lock count is initialized to 0 (no active and no waiting lockers).
18 *
19 * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
20 * uncontended lock. This can be determined because XADD returns the old value.
21 * Readers increment by 1 and see a positive value when uncontended, negative
22 * if there are writers (and maybe) readers waiting (in which case it goes to
23 * sleep).
24 *
25 * The value of WAITING_BIAS supports up to 32766 waiting processes. This can
26 * be extended to 65534 by manually checking the whole MSW rather than relying
27 * on the S flag.
28 *
29 * The value of ACTIVE_BIAS supports up to 65535 active processes.
30 *
31 * This should be totally fair - if anything is waiting, a process that wants a
32 * lock will go to the back of the queue. When the currently active lock is
33 * released, if there's a writer at the front of the queue, then that and only
34 * that will be woken up; if there's a bunch of consequtive readers at the
35 * front, then they'll all be woken up, but no other readers will be.
36 */
37
38#ifndef _LINUX_RWSEM_H
39#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
40#endif
41
f4815ac6 42#ifndef CONFIG_64BIT
1da177e4
LT
43#define RWSEM_UNLOCKED_VALUE 0x00000000
44#define RWSEM_ACTIVE_BIAS 0x00000001
45#define RWSEM_ACTIVE_MASK 0x0000ffff
46#define RWSEM_WAITING_BIAS (-0x00010000)
f4815ac6 47#else /* CONFIG_64BIT */
1da177e4
LT
48#define RWSEM_UNLOCKED_VALUE 0x0000000000000000L
49#define RWSEM_ACTIVE_BIAS 0x0000000000000001L
50#define RWSEM_ACTIVE_MASK 0x00000000ffffffffL
51#define RWSEM_WAITING_BIAS (-0x0000000100000000L)
f4815ac6 52#endif /* CONFIG_64BIT */
1da177e4
LT
53#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
54#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
55
1da177e4
LT
56/*
57 * lock for reading
58 */
59static inline void __down_read(struct rw_semaphore *sem)
60{
61 signed long old, new;
62
94c12cc7 63 asm volatile(
f4815ac6 64#ifndef CONFIG_64BIT
987bcdac 65 " l %0,%2\n"
94c12cc7 66 "0: lr %1,%0\n"
987bcdac
MS
67 " ahi %1,%4\n"
68 " cs %0,%1,%2\n"
94c12cc7 69 " jl 0b"
f4815ac6 70#else /* CONFIG_64BIT */
987bcdac 71 " lg %0,%2\n"
94c12cc7 72 "0: lgr %1,%0\n"
987bcdac
MS
73 " aghi %1,%4\n"
74 " csg %0,%1,%2\n"
94c12cc7 75 " jl 0b"
f4815ac6 76#endif /* CONFIG_64BIT */
987bcdac
MS
77 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
78 : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS)
79 : "cc", "memory");
1da177e4
LT
80 if (old < 0)
81 rwsem_down_read_failed(sem);
82}
83
84/*
85 * trylock for reading -- returns 1 if successful, 0 if contention
86 */
87static inline int __down_read_trylock(struct rw_semaphore *sem)
88{
89 signed long old, new;
90
94c12cc7 91 asm volatile(
f4815ac6 92#ifndef CONFIG_64BIT
987bcdac 93 " l %0,%2\n"
94c12cc7
MS
94 "0: ltr %1,%0\n"
95 " jm 1f\n"
987bcdac
MS
96 " ahi %1,%4\n"
97 " cs %0,%1,%2\n"
94c12cc7 98 " jl 0b\n"
1da177e4 99 "1:"
f4815ac6 100#else /* CONFIG_64BIT */
987bcdac 101 " lg %0,%2\n"
94c12cc7
MS
102 "0: ltgr %1,%0\n"
103 " jm 1f\n"
987bcdac
MS
104 " aghi %1,%4\n"
105 " csg %0,%1,%2\n"
94c12cc7 106 " jl 0b\n"
1da177e4 107 "1:"
f4815ac6 108#endif /* CONFIG_64BIT */
987bcdac
MS
109 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
110 : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS)
111 : "cc", "memory");
1da177e4
LT
112 return old >= 0 ? 1 : 0;
113}
114
115/*
116 * lock for writing
117 */
4ea2176d 118static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
1da177e4
LT
119{
120 signed long old, new, tmp;
121
122 tmp = RWSEM_ACTIVE_WRITE_BIAS;
94c12cc7 123 asm volatile(
f4815ac6 124#ifndef CONFIG_64BIT
987bcdac 125 " l %0,%2\n"
94c12cc7 126 "0: lr %1,%0\n"
987bcdac
MS
127 " a %1,%4\n"
128 " cs %0,%1,%2\n"
94c12cc7 129 " jl 0b"
f4815ac6 130#else /* CONFIG_64BIT */
987bcdac 131 " lg %0,%2\n"
94c12cc7 132 "0: lgr %1,%0\n"
987bcdac
MS
133 " ag %1,%4\n"
134 " csg %0,%1,%2\n"
94c12cc7 135 " jl 0b"
f4815ac6 136#endif /* CONFIG_64BIT */
987bcdac
MS
137 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
138 : "Q" (sem->count), "m" (tmp)
94c12cc7 139 : "cc", "memory");
1da177e4
LT
140 if (old != 0)
141 rwsem_down_write_failed(sem);
142}
143
4ea2176d
IM
144static inline void __down_write(struct rw_semaphore *sem)
145{
146 __down_write_nested(sem, 0);
147}
148
1da177e4
LT
149/*
150 * trylock for writing -- returns 1 if successful, 0 if contention
151 */
152static inline int __down_write_trylock(struct rw_semaphore *sem)
153{
154 signed long old;
155
94c12cc7 156 asm volatile(
f4815ac6 157#ifndef CONFIG_64BIT
987bcdac 158 " l %0,%1\n"
94c12cc7
MS
159 "0: ltr %0,%0\n"
160 " jnz 1f\n"
987bcdac 161 " cs %0,%3,%1\n"
94c12cc7 162 " jl 0b\n"
f4815ac6 163#else /* CONFIG_64BIT */
987bcdac 164 " lg %0,%1\n"
94c12cc7
MS
165 "0: ltgr %0,%0\n"
166 " jnz 1f\n"
987bcdac 167 " csg %0,%3,%1\n"
94c12cc7 168 " jl 0b\n"
f4815ac6 169#endif /* CONFIG_64BIT */
1da177e4 170 "1:"
987bcdac
MS
171 : "=&d" (old), "=Q" (sem->count)
172 : "Q" (sem->count), "d" (RWSEM_ACTIVE_WRITE_BIAS)
173 : "cc", "memory");
1da177e4
LT
174 return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0;
175}
176
177/*
178 * unlock after reading
179 */
180static inline void __up_read(struct rw_semaphore *sem)
181{
182 signed long old, new;
183
94c12cc7 184 asm volatile(
f4815ac6 185#ifndef CONFIG_64BIT
987bcdac 186 " l %0,%2\n"
94c12cc7 187 "0: lr %1,%0\n"
987bcdac
MS
188 " ahi %1,%4\n"
189 " cs %0,%1,%2\n"
94c12cc7 190 " jl 0b"
f4815ac6 191#else /* CONFIG_64BIT */
987bcdac 192 " lg %0,%2\n"
94c12cc7 193 "0: lgr %1,%0\n"
987bcdac
MS
194 " aghi %1,%4\n"
195 " csg %0,%1,%2\n"
94c12cc7 196 " jl 0b"
f4815ac6 197#endif /* CONFIG_64BIT */
987bcdac
MS
198 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
199 : "Q" (sem->count), "i" (-RWSEM_ACTIVE_READ_BIAS)
94c12cc7 200 : "cc", "memory");
1da177e4
LT
201 if (new < 0)
202 if ((new & RWSEM_ACTIVE_MASK) == 0)
203 rwsem_wake(sem);
204}
205
206/*
207 * unlock after writing
208 */
209static inline void __up_write(struct rw_semaphore *sem)
210{
211 signed long old, new, tmp;
212
213 tmp = -RWSEM_ACTIVE_WRITE_BIAS;
94c12cc7 214 asm volatile(
f4815ac6 215#ifndef CONFIG_64BIT
987bcdac 216 " l %0,%2\n"
94c12cc7 217 "0: lr %1,%0\n"
987bcdac
MS
218 " a %1,%4\n"
219 " cs %0,%1,%2\n"
94c12cc7 220 " jl 0b"
f4815ac6 221#else /* CONFIG_64BIT */
987bcdac 222 " lg %0,%2\n"
94c12cc7 223 "0: lgr %1,%0\n"
987bcdac
MS
224 " ag %1,%4\n"
225 " csg %0,%1,%2\n"
94c12cc7 226 " jl 0b"
f4815ac6 227#endif /* CONFIG_64BIT */
987bcdac
MS
228 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
229 : "Q" (sem->count), "m" (tmp)
94c12cc7 230 : "cc", "memory");
1da177e4
LT
231 if (new < 0)
232 if ((new & RWSEM_ACTIVE_MASK) == 0)
233 rwsem_wake(sem);
234}
235
236/*
237 * downgrade write lock to read lock
238 */
239static inline void __downgrade_write(struct rw_semaphore *sem)
240{
241 signed long old, new, tmp;
242
243 tmp = -RWSEM_WAITING_BIAS;
94c12cc7 244 asm volatile(
f4815ac6 245#ifndef CONFIG_64BIT
987bcdac 246 " l %0,%2\n"
94c12cc7 247 "0: lr %1,%0\n"
987bcdac
MS
248 " a %1,%4\n"
249 " cs %0,%1,%2\n"
94c12cc7 250 " jl 0b"
f4815ac6 251#else /* CONFIG_64BIT */
987bcdac 252 " lg %0,%2\n"
94c12cc7 253 "0: lgr %1,%0\n"
987bcdac
MS
254 " ag %1,%4\n"
255 " csg %0,%1,%2\n"
94c12cc7 256 " jl 0b"
f4815ac6 257#endif /* CONFIG_64BIT */
987bcdac
MS
258 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
259 : "Q" (sem->count), "m" (tmp)
94c12cc7 260 : "cc", "memory");
1da177e4
LT
261 if (new > 1)
262 rwsem_downgrade_wake(sem);
263}
264
265/*
266 * implement atomic add functionality
267 */
268static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
269{
270 signed long old, new;
271
94c12cc7 272 asm volatile(
f4815ac6 273#ifndef CONFIG_64BIT
987bcdac 274 " l %0,%2\n"
94c12cc7 275 "0: lr %1,%0\n"
987bcdac
MS
276 " ar %1,%4\n"
277 " cs %0,%1,%2\n"
94c12cc7 278 " jl 0b"
f4815ac6 279#else /* CONFIG_64BIT */
987bcdac 280 " lg %0,%2\n"
94c12cc7 281 "0: lgr %1,%0\n"
987bcdac
MS
282 " agr %1,%4\n"
283 " csg %0,%1,%2\n"
94c12cc7 284 " jl 0b"
f4815ac6 285#endif /* CONFIG_64BIT */
987bcdac
MS
286 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
287 : "Q" (sem->count), "d" (delta)
94c12cc7 288 : "cc", "memory");
1da177e4
LT
289}
290
291/*
292 * implement exchange and add functionality
293 */
294static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
295{
296 signed long old, new;
297
94c12cc7 298 asm volatile(
f4815ac6 299#ifndef CONFIG_64BIT
987bcdac 300 " l %0,%2\n"
94c12cc7 301 "0: lr %1,%0\n"
987bcdac
MS
302 " ar %1,%4\n"
303 " cs %0,%1,%2\n"
94c12cc7 304 " jl 0b"
f4815ac6 305#else /* CONFIG_64BIT */
987bcdac 306 " lg %0,%2\n"
94c12cc7 307 "0: lgr %1,%0\n"
987bcdac
MS
308 " agr %1,%4\n"
309 " csg %0,%1,%2\n"
94c12cc7 310 " jl 0b"
f4815ac6 311#endif /* CONFIG_64BIT */
987bcdac
MS
312 : "=&d" (old), "=&d" (new), "=Q" (sem->count)
313 : "Q" (sem->count), "d" (delta)
94c12cc7 314 : "cc", "memory");
1da177e4
LT
315 return new;
316}
317
1da177e4 318#endif /* _S390_RWSEM_H */