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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
9b747530 HC |
2 | #ifndef __S390_ASM_SIGP_H |
3 | #define __S390_ASM_SIGP_H | |
4 | ||
5 | /* SIGP order codes */ | |
6 | #define SIGP_SENSE 1 | |
7 | #define SIGP_EXTERNAL_CALL 2 | |
8 | #define SIGP_EMERGENCY_SIGNAL 3 | |
58bc33b2 | 9 | #define SIGP_START 4 |
9b747530 HC |
10 | #define SIGP_STOP 5 |
11 | #define SIGP_RESTART 6 | |
12 | #define SIGP_STOP_AND_STORE_STATUS 9 | |
13 | #define SIGP_INITIAL_CPU_RESET 11 | |
b8983830 | 14 | #define SIGP_CPU_RESET 12 |
9b747530 HC |
15 | #define SIGP_SET_PREFIX 13 |
16 | #define SIGP_STORE_STATUS_AT_ADDRESS 14 | |
17 | #define SIGP_SET_ARCHITECTURE 18 | |
b13d3580 | 18 | #define SIGP_COND_EMERGENCY_SIGNAL 19 |
9b747530 | 19 | #define SIGP_SENSE_RUNNING 21 |
10ad34bc | 20 | #define SIGP_SET_MULTI_THREADING 22 |
a62bc073 | 21 | #define SIGP_STORE_ADDITIONAL_STATUS 23 |
9b747530 HC |
22 | |
23 | /* SIGP condition codes */ | |
24 | #define SIGP_CC_ORDER_CODE_ACCEPTED 0 | |
25 | #define SIGP_CC_STATUS_STORED 1 | |
26 | #define SIGP_CC_BUSY 2 | |
27 | #define SIGP_CC_NOT_OPERATIONAL 3 | |
28 | ||
29 | /* SIGP cpu status bits */ | |
30 | ||
bd50e8ec | 31 | #define SIGP_STATUS_INVALID_ORDER 0x00000002UL |
9b747530 HC |
32 | #define SIGP_STATUS_CHECK_STOP 0x00000010UL |
33 | #define SIGP_STATUS_STOPPED 0x00000040UL | |
21b26c08 | 34 | #define SIGP_STATUS_EXT_CALL_PENDING 0x00000080UL |
9b747530 HC |
35 | #define SIGP_STATUS_INVALID_PARAMETER 0x00000100UL |
36 | #define SIGP_STATUS_INCORRECT_STATE 0x00000200UL | |
37 | #define SIGP_STATUS_NOT_RUNNING 0x00000400UL | |
38 | ||
e7c46c66 HC |
39 | #ifndef __ASSEMBLY__ |
40 | ||
80a60f6e HC |
41 | static inline int ____pcpu_sigp(u16 addr, u8 order, unsigned long parm, |
42 | u32 *status) | |
e7c46c66 | 43 | { |
25130c1a | 44 | union register_pair r1 = { .odd = parm, }; |
e7c46c66 HC |
45 | int cc; |
46 | ||
47 | asm volatile( | |
25130c1a HC |
48 | " sigp %[r1],%[addr],0(%[order])\n" |
49 | " ipm %[cc]\n" | |
50 | " srl %[cc],28\n" | |
51 | : [cc] "=&d" (cc), [r1] "+&d" (r1.pair) | |
52 | : [addr] "d" (addr), [order] "a" (order) | |
53 | : "cc"); | |
54 | *status = r1.even; | |
80a60f6e HC |
55 | return cc; |
56 | } | |
57 | ||
58 | static inline int __pcpu_sigp(u16 addr, u8 order, unsigned long parm, | |
59 | u32 *status) | |
60 | { | |
61 | u32 _status; | |
62 | int cc; | |
63 | ||
64 | cc = ____pcpu_sigp(addr, order, parm, &_status); | |
bf10b668 | 65 | if (status && cc == SIGP_CC_STATUS_STORED) |
80a60f6e | 66 | *status = _status; |
e7c46c66 HC |
67 | return cc; |
68 | } | |
69 | ||
70 | #endif /* __ASSEMBLY__ */ | |
71 | ||
9b747530 | 72 | #endif /* __S390_ASM_SIGP_H */ |