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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/entry.S | |
3 | * S390 low-level entry points. | |
4 | * | |
54dfe5dd | 5 | * Copyright (C) IBM Corp. 1999,2006 |
1da177e4 | 6 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), |
25d83cbf HC |
7 | * Hartmut Penner (hp@de.ibm.com), |
8 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
77fa2245 | 9 | * Heiko Carstens <heiko.carstens@de.ibm.com> |
1da177e4 LT |
10 | */ |
11 | ||
12 | #include <linux/sys.h> | |
13 | #include <linux/linkage.h> | |
1da177e4 LT |
14 | #include <asm/cache.h> |
15 | #include <asm/lowcore.h> | |
16 | #include <asm/errno.h> | |
17 | #include <asm/ptrace.h> | |
18 | #include <asm/thread_info.h> | |
0013a854 | 19 | #include <asm/asm-offsets.h> |
1da177e4 LT |
20 | #include <asm/unistd.h> |
21 | #include <asm/page.h> | |
22 | ||
23 | /* | |
24 | * Stack layout for the system_call stack entry. | |
25 | * The first few entries are identical to the user_regs_struct. | |
26 | */ | |
25d83cbf HC |
27 | SP_PTREGS = STACK_FRAME_OVERHEAD |
28 | SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS | |
29 | SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW | |
30 | SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS | |
31 | SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 4 | |
32 | SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8 | |
33 | SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 12 | |
34 | SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16 | |
35 | SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 20 | |
36 | SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24 | |
37 | SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 28 | |
38 | SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32 | |
39 | SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 36 | |
40 | SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40 | |
41 | SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 44 | |
42 | SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48 | |
43 | SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 52 | |
44 | SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56 | |
45 | SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 60 | |
46 | SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2 | |
47 | SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC | |
48 | SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP | |
49 | SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE | |
1da177e4 | 50 | |
54dfe5dd HC |
51 | _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \ |
52 | _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) | |
53 | _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \ | |
54 | _TIF_MCCK_PENDING) | |
1da177e4 LT |
55 | |
56 | STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER | |
57 | STACK_SIZE = 1 << STACK_SHIFT | |
58 | ||
59 | #define BASED(name) name-system_call(%r13) | |
60 | ||
1f194a4c HC |
61 | #ifdef CONFIG_TRACE_IRQFLAGS |
62 | .macro TRACE_IRQS_ON | |
63 | l %r1,BASED(.Ltrace_irq_on) | |
64 | basr %r14,%r1 | |
65 | .endm | |
66 | ||
67 | .macro TRACE_IRQS_OFF | |
68 | l %r1,BASED(.Ltrace_irq_off) | |
69 | basr %r14,%r1 | |
70 | .endm | |
523b44cf HC |
71 | |
72 | .macro LOCKDEP_SYS_EXIT | |
73 | l %r1,BASED(.Llockdep_sys_exit) | |
74 | basr %r14,%r1 | |
75 | .endm | |
1f194a4c HC |
76 | #else |
77 | #define TRACE_IRQS_ON | |
78 | #define TRACE_IRQS_OFF | |
523b44cf | 79 | #define LOCKDEP_SYS_EXIT |
1f194a4c HC |
80 | #endif |
81 | ||
1da177e4 LT |
82 | /* |
83 | * Register usage in interrupt handlers: | |
84 | * R9 - pointer to current task structure | |
85 | * R13 - pointer to literal pool | |
86 | * R14 - return register for function calls | |
87 | * R15 - kernel stack pointer | |
88 | */ | |
89 | ||
25d83cbf | 90 | .macro STORE_TIMER lc_offset |
1da177e4 LT |
91 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
92 | stpt \lc_offset | |
93 | #endif | |
94 | .endm | |
95 | ||
96 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
25d83cbf | 97 | .macro UPDATE_VTIME lc_from,lc_to,lc_sum |
1da177e4 LT |
98 | lm %r10,%r11,\lc_from |
99 | sl %r10,\lc_to | |
100 | sl %r11,\lc_to+4 | |
101 | bc 3,BASED(0f) | |
102 | sl %r10,BASED(.Lc_1) | |
103 | 0: al %r10,\lc_sum | |
104 | al %r11,\lc_sum+4 | |
105 | bc 12,BASED(1f) | |
106 | al %r10,BASED(.Lc_1) | |
107 | 1: stm %r10,%r11,\lc_sum | |
108 | .endm | |
109 | #endif | |
110 | ||
111 | .macro SAVE_ALL_BASE savearea | |
112 | stm %r12,%r15,\savearea | |
113 | l %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13 | |
114 | .endm | |
115 | ||
987ad70a MS |
116 | .macro SAVE_ALL_SVC psworg,savearea |
117 | la %r12,\psworg | |
118 | l %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
119 | .endm | |
120 | ||
63b12246 | 121 | .macro SAVE_ALL_SYNC psworg,savearea |
1da177e4 | 122 | la %r12,\psworg |
1da177e4 LT |
123 | tm \psworg+1,0x01 # test problem state bit |
124 | bz BASED(2f) # skip stack setup save | |
125 | l %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
63b12246 MS |
126 | #ifdef CONFIG_CHECK_STACK |
127 | b BASED(3f) | |
128 | 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
129 | bz BASED(stack_overflow) | |
130 | 3: | |
131 | #endif | |
132 | 2: | |
133 | .endm | |
134 | ||
135 | .macro SAVE_ALL_ASYNC psworg,savearea | |
136 | la %r12,\psworg | |
1da177e4 LT |
137 | tm \psworg+1,0x01 # test problem state bit |
138 | bnz BASED(1f) # from user -> load async stack | |
139 | clc \psworg+4(4),BASED(.Lcritical_end) | |
140 | bhe BASED(0f) | |
141 | clc \psworg+4(4),BASED(.Lcritical_start) | |
142 | bl BASED(0f) | |
143 | l %r14,BASED(.Lcleanup_critical) | |
144 | basr %r14,%r14 | |
6add9f7f | 145 | tm 1(%r12),0x01 # retest problem state after cleanup |
1da177e4 LT |
146 | bnz BASED(1f) |
147 | 0: l %r14,__LC_ASYNC_STACK # are we already on the async stack ? | |
148 | slr %r14,%r15 | |
149 | sra %r14,STACK_SHIFT | |
150 | be BASED(2f) | |
151 | 1: l %r15,__LC_ASYNC_STACK | |
1da177e4 LT |
152 | #ifdef CONFIG_CHECK_STACK |
153 | b BASED(3f) | |
154 | 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
155 | bz BASED(stack_overflow) | |
156 | 3: | |
157 | #endif | |
77fa2245 HC |
158 | 2: |
159 | .endm | |
160 | ||
25d83cbf | 161 | .macro CREATE_STACK_FRAME psworg,savearea |
77fa2245 | 162 | s %r15,BASED(.Lc_spsize) # make room for registers & psw |
1da177e4 LT |
163 | mvc SP_PSW(8,%r15),0(%r12) # move user PSW to stack |
164 | la %r12,\psworg | |
165 | st %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 | |
166 | icm %r12,12,__LC_SVC_ILC | |
167 | stm %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack | |
168 | st %r12,SP_ILC(%r15) | |
169 | mvc SP_R12(16,%r15),\savearea # move %r12-%r15 to stack | |
170 | la %r12,0 | |
171 | st %r12,__SF_BACKCHAIN(%r15) # clear back chain | |
172 | .endm | |
173 | ||
25d83cbf | 174 | .macro RESTORE_ALL psworg,sync |
ae6aa2ea | 175 | mvc \psworg(8),SP_PSW(%r15) # move user PSW to lowcore |
1da177e4 | 176 | .if !\sync |
ae6aa2ea | 177 | ni \psworg+1,0xfd # clear wait state bit |
1da177e4 LT |
178 | .endif |
179 | lm %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user | |
180 | STORE_TIMER __LC_EXIT_TIMER | |
ae6aa2ea | 181 | lpsw \psworg # back to caller |
1da177e4 LT |
182 | .endm |
183 | ||
184 | /* | |
185 | * Scheduler resume function, called by switch_to | |
186 | * gpr2 = (task_struct *) prev | |
187 | * gpr3 = (task_struct *) next | |
188 | * Returns: | |
189 | * gpr2 = prev | |
190 | */ | |
25d83cbf | 191 | .globl __switch_to |
1da177e4 | 192 | __switch_to: |
25d83cbf | 193 | basr %r1,0 |
1da177e4 LT |
194 | __switch_to_base: |
195 | tm __THREAD_per(%r3),0xe8 # new process is using per ? | |
196 | bz __switch_to_noper-__switch_to_base(%r1) # if not we're fine | |
25d83cbf HC |
197 | stctl %c9,%c11,__SF_EMPTY(%r15) # We are using per stuff |
198 | clc __THREAD_per(12,%r3),__SF_EMPTY(%r15) | |
199 | be __switch_to_noper-__switch_to_base(%r1) # we got away w/o bashing TLB's | |
200 | lctl %c9,%c11,__THREAD_per(%r3) # Nope we didn't | |
1da177e4 | 201 | __switch_to_noper: |
77fa2245 HC |
202 | l %r4,__THREAD_info(%r2) # get thread_info of prev |
203 | tm __TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending? | |
204 | bz __switch_to_no_mcck-__switch_to_base(%r1) | |
205 | ni __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev | |
206 | l %r4,__THREAD_info(%r3) # get thread_info of next | |
207 | oi __TI_flags+3(%r4),_TIF_MCCK_PENDING # set it in next | |
208 | __switch_to_no_mcck: | |
25d83cbf | 209 | stm %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task |
1da177e4 LT |
210 | st %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp |
211 | l %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp | |
212 | lm %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task | |
213 | st %r3,__LC_CURRENT # __LC_CURRENT = current task struct | |
214 | lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 | |
25d83cbf | 215 | l %r3,__THREAD_info(%r3) # load thread_info from task struct |
1da177e4 LT |
216 | st %r3,__LC_THREAD_INFO |
217 | ahi %r3,STACK_SIZE | |
218 | st %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack | |
219 | br %r14 | |
220 | ||
221 | __critical_start: | |
222 | /* | |
223 | * SVC interrupt handler routine. System calls are synchronous events and | |
224 | * are executed with interrupts enabled. | |
225 | */ | |
226 | ||
25d83cbf | 227 | .globl system_call |
1da177e4 LT |
228 | system_call: |
229 | STORE_TIMER __LC_SYNC_ENTER_TIMER | |
230 | sysc_saveall: | |
231 | SAVE_ALL_BASE __LC_SAVE_AREA | |
987ad70a | 232 | SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 233 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
234 | lh %r7,0x8a # get svc number from lowcore |
235 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
236 | sysc_vtime: | |
237 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
238 | bz BASED(sysc_do_svc) | |
239 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
240 | sysc_stime: | |
241 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
242 | sysc_update: | |
243 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
244 | #endif | |
245 | sysc_do_svc: | |
246 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
25d83cbf HC |
247 | sla %r7,2 # *4 and test for svc 0 |
248 | bnz BASED(sysc_nr_ok) # svc number > 0 | |
1da177e4 LT |
249 | # svc 0: system call number in %r1 |
250 | cl %r1,BASED(.Lnr_syscalls) | |
251 | bnl BASED(sysc_nr_ok) | |
25d83cbf HC |
252 | lr %r7,%r1 # copy svc number to %r7 |
253 | sla %r7,2 # *4 | |
1da177e4 LT |
254 | sysc_nr_ok: |
255 | mvc SP_ARGS(4,%r15),SP_R7(%r15) | |
256 | sysc_do_restart: | |
d882b172 | 257 | l %r8,BASED(.Lsysc_table) |
1da177e4 | 258 | tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) |
d882b172 | 259 | l %r8,0(%r7,%r8) # get system call addr. |
25d83cbf HC |
260 | bnz BASED(sysc_tracesys) |
261 | basr %r14,%r8 # call sys_xxxx | |
262 | st %r2,SP_R2(%r15) # store return value (change R2 on stack) | |
1da177e4 LT |
263 | |
264 | sysc_return: | |
265 | tm SP_PSW+1(%r15),0x01 # returning to user ? | |
266 | bno BASED(sysc_leave) | |
267 | tm __TI_flags+3(%r9),_TIF_WORK_SVC | |
268 | bnz BASED(sysc_work) # there is work to do (signals etc.) | |
523b44cf | 269 | LOCKDEP_SYS_EXIT |
1da177e4 | 270 | sysc_leave: |
25d83cbf | 271 | RESTORE_ALL __LC_RETURN_PSW,1 |
1da177e4 LT |
272 | |
273 | # | |
274 | # recheck if there is more work to do | |
275 | # | |
276 | sysc_work_loop: | |
277 | tm __TI_flags+3(%r9),_TIF_WORK_SVC | |
25d83cbf | 278 | bz BASED(sysc_leave) # there is no work to do |
1da177e4 LT |
279 | # |
280 | # One of the work bits is on. Find out which one. | |
281 | # | |
282 | sysc_work: | |
77fa2245 HC |
283 | tm __TI_flags+3(%r9),_TIF_MCCK_PENDING |
284 | bo BASED(sysc_mcck_pending) | |
1da177e4 LT |
285 | tm __TI_flags+3(%r9),_TIF_NEED_RESCHED |
286 | bo BASED(sysc_reschedule) | |
54dfe5dd HC |
287 | tm __TI_flags+3(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK) |
288 | bnz BASED(sysc_sigpending) | |
1da177e4 LT |
289 | tm __TI_flags+3(%r9),_TIF_RESTART_SVC |
290 | bo BASED(sysc_restart) | |
291 | tm __TI_flags+3(%r9),_TIF_SINGLE_STEP | |
292 | bo BASED(sysc_singlestep) | |
523b44cf | 293 | LOCKDEP_SYS_EXIT |
1da177e4 LT |
294 | b BASED(sysc_leave) |
295 | ||
296 | # | |
297 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
298 | # |
299 | sysc_reschedule: | |
300 | l %r1,BASED(.Lschedule) | |
301 | la %r14,BASED(sysc_work_loop) | |
302 | br %r1 # call scheduler | |
1da177e4 | 303 | |
77fa2245 HC |
304 | # |
305 | # _TIF_MCCK_PENDING is set, call handler | |
306 | # | |
307 | sysc_mcck_pending: | |
308 | l %r1,BASED(.Ls390_handle_mcck) | |
309 | la %r14,BASED(sysc_work_loop) | |
310 | br %r1 # TIF bit will be cleared by handler | |
311 | ||
1da177e4 | 312 | # |
54dfe5dd | 313 | # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal |
1da177e4 | 314 | # |
25d83cbf | 315 | sysc_sigpending: |
1da177e4 | 316 | ni __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP |
25d83cbf HC |
317 | la %r2,SP_PTREGS(%r15) # load pt_regs |
318 | l %r1,BASED(.Ldo_signal) | |
319 | basr %r14,%r1 # call do_signal | |
1da177e4 LT |
320 | tm __TI_flags+3(%r9),_TIF_RESTART_SVC |
321 | bo BASED(sysc_restart) | |
322 | tm __TI_flags+3(%r9),_TIF_SINGLE_STEP | |
323 | bo BASED(sysc_singlestep) | |
e1c3ad96 | 324 | b BASED(sysc_work_loop) |
1da177e4 LT |
325 | |
326 | # | |
327 | # _TIF_RESTART_SVC is set, set up registers and restart svc | |
328 | # | |
329 | sysc_restart: | |
330 | ni __TI_flags+3(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC | |
25d83cbf | 331 | l %r7,SP_R2(%r15) # load new svc number |
1da177e4 LT |
332 | sla %r7,2 |
333 | mvc SP_R2(4,%r15),SP_ORIG_R2(%r15) # restore first argument | |
25d83cbf HC |
334 | lm %r2,%r6,SP_R2(%r15) # load svc arguments |
335 | b BASED(sysc_do_restart) # restart svc | |
1da177e4 LT |
336 | |
337 | # | |
338 | # _TIF_SINGLE_STEP is set, call do_single_step | |
339 | # | |
340 | sysc_singlestep: | |
341 | ni __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP | |
342 | mvi SP_TRAP+1(%r15),0x28 # set trap indication to pgm check | |
343 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
344 | l %r1,BASED(.Lhandle_per) # load adr. of per handler | |
345 | la %r14,BASED(sysc_return) # load adr. of system return | |
346 | br %r1 # branch to do_single_step | |
347 | ||
1da177e4 LT |
348 | # |
349 | # call trace before and after sys_call | |
350 | # | |
351 | sysc_tracesys: | |
25d83cbf HC |
352 | l %r1,BASED(.Ltrace) |
353 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 LT |
354 | la %r3,0 |
355 | srl %r7,2 | |
356 | st %r7,SP_R2(%r15) | |
357 | basr %r14,%r1 | |
358 | clc SP_R2(4,%r15),BASED(.Lnr_syscalls) | |
359 | bnl BASED(sysc_tracenogo) | |
d882b172 | 360 | l %r8,BASED(.Lsysc_table) |
25d83cbf HC |
361 | l %r7,SP_R2(%r15) # strace might have changed the |
362 | sll %r7,2 # system call | |
d882b172 | 363 | l %r8,0(%r7,%r8) |
1da177e4 LT |
364 | sysc_tracego: |
365 | lm %r3,%r6,SP_R3(%r15) | |
366 | l %r2,SP_ORIG_R2(%r15) | |
25d83cbf HC |
367 | basr %r14,%r8 # call sys_xxx |
368 | st %r2,SP_R2(%r15) # store return value | |
1da177e4 LT |
369 | sysc_tracenogo: |
370 | tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) | |
25d83cbf | 371 | bz BASED(sysc_return) |
1da177e4 | 372 | l %r1,BASED(.Ltrace) |
25d83cbf | 373 | la %r2,SP_PTREGS(%r15) # load pt_regs |
1da177e4 LT |
374 | la %r3,1 |
375 | la %r14,BASED(sysc_return) | |
376 | br %r1 | |
377 | ||
378 | # | |
379 | # a new process exits the kernel with ret_from_fork | |
380 | # | |
25d83cbf | 381 | .globl ret_from_fork |
1da177e4 LT |
382 | ret_from_fork: |
383 | l %r13,__LC_SVC_NEW_PSW+4 | |
384 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
385 | tm SP_PSW+1(%r15),0x01 # forking a kernel thread ? | |
386 | bo BASED(0f) | |
387 | st %r15,SP_R15(%r15) # store stack pointer for new kthread | |
25d83cbf HC |
388 | 0: l %r1,BASED(.Lschedtail) |
389 | basr %r14,%r1 | |
1f194a4c | 390 | TRACE_IRQS_ON |
25d83cbf | 391 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
1da177e4 LT |
392 | b BASED(sysc_return) |
393 | ||
394 | # | |
03ff9a23 MS |
395 | # kernel_execve function needs to deal with pt_regs that is not |
396 | # at the usual place | |
1da177e4 | 397 | # |
03ff9a23 MS |
398 | .globl kernel_execve |
399 | kernel_execve: | |
400 | stm %r12,%r15,48(%r15) | |
401 | lr %r14,%r15 | |
402 | l %r13,__LC_SVC_NEW_PSW+4 | |
403 | s %r15,BASED(.Lc_spsize) | |
404 | st %r14,__SF_BACKCHAIN(%r15) | |
405 | la %r12,SP_PTREGS(%r15) | |
406 | xc 0(__PT_SIZE,%r12),0(%r12) | |
407 | l %r1,BASED(.Ldo_execve) | |
408 | lr %r5,%r12 | |
409 | basr %r14,%r1 | |
410 | ltr %r2,%r2 | |
411 | be BASED(0f) | |
412 | a %r15,BASED(.Lc_spsize) | |
413 | lm %r12,%r15,48(%r15) | |
414 | br %r14 | |
415 | # execve succeeded. | |
416 | 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts | |
417 | l %r15,__LC_KERNEL_STACK # load ksp | |
418 | s %r15,BASED(.Lc_spsize) # make room for registers & psw | |
419 | l %r9,__LC_THREAD_INFO | |
420 | mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs | |
421 | xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) | |
422 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
423 | l %r1,BASED(.Lexecve_tail) | |
424 | basr %r14,%r1 | |
425 | b BASED(sysc_return) | |
1da177e4 LT |
426 | |
427 | /* | |
428 | * Program check handler routine | |
429 | */ | |
430 | ||
25d83cbf | 431 | .globl pgm_check_handler |
1da177e4 LT |
432 | pgm_check_handler: |
433 | /* | |
434 | * First we need to check for a special case: | |
435 | * Single stepping an instruction that disables the PER event mask will | |
436 | * cause a PER event AFTER the mask has been set. Example: SVC or LPSW. | |
437 | * For a single stepped SVC the program check handler gets control after | |
438 | * the SVC new PSW has been loaded. But we want to execute the SVC first and | |
439 | * then handle the PER event. Therefore we update the SVC old PSW to point | |
440 | * to the pgm_check_handler and branch to the SVC handler after we checked | |
441 | * if we have to load the kernel stack register. | |
442 | * For every other possible cause for PER event without the PER mask set | |
443 | * we just ignore the PER event (FIXME: is there anything we have to do | |
444 | * for LPSW?). | |
445 | */ | |
446 | STORE_TIMER __LC_SYNC_ENTER_TIMER | |
447 | SAVE_ALL_BASE __LC_SAVE_AREA | |
25d83cbf HC |
448 | tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception |
449 | bnz BASED(pgm_per) # got per exception -> special case | |
63b12246 | 450 | SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 451 | CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
452 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
453 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
454 | bz BASED(pgm_no_vtime) | |
455 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
456 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
457 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
458 | pgm_no_vtime: | |
459 | #endif | |
460 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
25d83cbf | 461 | l %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 LT |
462 | la %r8,0x7f |
463 | nr %r8,%r3 | |
464 | pgm_do_call: | |
25d83cbf HC |
465 | l %r7,BASED(.Ljump_table) |
466 | sll %r8,2 | |
467 | l %r7,0(%r8,%r7) # load address of handler routine | |
468 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
469 | la %r14,BASED(sysc_return) | |
470 | br %r7 # branch to interrupt-handler | |
1da177e4 LT |
471 | |
472 | # | |
473 | # handle per exception | |
474 | # | |
475 | pgm_per: | |
25d83cbf HC |
476 | tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on |
477 | bnz BASED(pgm_per_std) # ok, normal per event from user space | |
1da177e4 | 478 | # ok its one of the special cases, now we need to find out which one |
25d83cbf HC |
479 | clc __LC_PGM_OLD_PSW(8),__LC_SVC_NEW_PSW |
480 | be BASED(pgm_svcper) | |
1da177e4 | 481 | # no interesting special case, ignore PER event |
25d83cbf HC |
482 | lm %r12,%r15,__LC_SAVE_AREA |
483 | lpsw 0x28 | |
1da177e4 LT |
484 | |
485 | # | |
486 | # Normal per exception | |
487 | # | |
488 | pgm_per_std: | |
63b12246 | 489 | SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 490 | CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
491 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
492 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
493 | bz BASED(pgm_no_vtime2) | |
494 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
495 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
496 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
497 | pgm_no_vtime2: | |
498 | #endif | |
499 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
500 | l %r1,__TI_task(%r9) | |
501 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID | |
502 | mvc __THREAD_per+__PER_address(4,%r1),__LC_PER_ADDRESS | |
503 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
504 | oi __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP | |
4ba069b8 MG |
505 | tm SP_PSW+1(%r15),0x01 # kernel per event ? |
506 | bz BASED(kernel_per) | |
25d83cbf | 507 | l %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 | 508 | la %r8,0x7f |
25d83cbf HC |
509 | nr %r8,%r3 # clear per-event-bit and ilc |
510 | be BASED(sysc_return) # only per or per+check ? | |
1da177e4 LT |
511 | b BASED(pgm_do_call) |
512 | ||
513 | # | |
514 | # it was a single stepped SVC that is causing all the trouble | |
515 | # | |
516 | pgm_svcper: | |
63b12246 | 517 | SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 518 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
519 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
520 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
521 | bz BASED(pgm_no_vtime3) | |
522 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
523 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
524 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
525 | pgm_no_vtime3: | |
526 | #endif | |
527 | lh %r7,0x8a # get svc number from lowcore | |
528 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
529 | l %r1,__TI_task(%r9) | |
530 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID | |
531 | mvc __THREAD_per+__PER_address(4,%r1),__LC_PER_ADDRESS | |
532 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
533 | oi __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP | |
1f194a4c | 534 | TRACE_IRQS_ON |
1da177e4 LT |
535 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
536 | b BASED(sysc_do_svc) | |
537 | ||
4ba069b8 MG |
538 | # |
539 | # per was called from kernel, must be kprobes | |
540 | # | |
541 | kernel_per: | |
542 | mvi SP_TRAP+1(%r15),0x28 # set trap indication to pgm check | |
543 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
544 | l %r1,BASED(.Lhandle_per) # load adr. of per handler | |
545 | la %r14,BASED(sysc_leave) # load adr. of system return | |
546 | br %r1 # branch to do_single_step | |
547 | ||
1da177e4 LT |
548 | /* |
549 | * IO interrupt handler routine | |
550 | */ | |
551 | ||
25d83cbf | 552 | .globl io_int_handler |
1da177e4 LT |
553 | io_int_handler: |
554 | STORE_TIMER __LC_ASYNC_ENTER_TIMER | |
555 | stck __LC_INT_CLOCK | |
556 | SAVE_ALL_BASE __LC_SAVE_AREA+16 | |
63b12246 | 557 | SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+16 |
77fa2245 | 558 | CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+16 |
1da177e4 LT |
559 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
560 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
561 | bz BASED(io_no_vtime) | |
562 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
563 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
564 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
565 | io_no_vtime: | |
566 | #endif | |
567 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
1f194a4c | 568 | TRACE_IRQS_OFF |
25d83cbf HC |
569 | l %r1,BASED(.Ldo_IRQ) # load address of do_IRQ |
570 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
571 | basr %r14,%r1 # branch to standard irq handler | |
1f194a4c | 572 | TRACE_IRQS_ON |
1da177e4 LT |
573 | |
574 | io_return: | |
25d83cbf | 575 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
1da177e4 | 576 | #ifdef CONFIG_PREEMPT |
25d83cbf | 577 | bno BASED(io_preempt) # no -> check for preemptive scheduling |
1da177e4 | 578 | #else |
25d83cbf | 579 | bno BASED(io_leave) # no-> skip resched & signal |
1da177e4 LT |
580 | #endif |
581 | tm __TI_flags+3(%r9),_TIF_WORK_INT | |
25d83cbf | 582 | bnz BASED(io_work) # there is work to do (signals etc.) |
523b44cf | 583 | LOCKDEP_SYS_EXIT |
1da177e4 | 584 | io_leave: |
25d83cbf | 585 | RESTORE_ALL __LC_RETURN_PSW,0 |
ae6aa2ea | 586 | io_done: |
1da177e4 LT |
587 | |
588 | #ifdef CONFIG_PREEMPT | |
589 | io_preempt: | |
590 | icm %r0,15,__TI_precount(%r9) | |
25d83cbf | 591 | bnz BASED(io_leave) |
1da177e4 LT |
592 | l %r1,SP_R15(%r15) |
593 | s %r1,BASED(.Lc_spsize) | |
594 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 595 | xc __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 LT |
596 | lr %r15,%r1 |
597 | io_resume_loop: | |
598 | tm __TI_flags+3(%r9),_TIF_NEED_RESCHED | |
599 | bno BASED(io_leave) | |
25d83cbf HC |
600 | mvc __TI_precount(4,%r9),BASED(.Lc_pactive) |
601 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
602 | l %r1,BASED(.Lschedule) | |
1da177e4 | 603 | basr %r14,%r1 # call schedule |
25d83cbf HC |
604 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts |
605 | xc __TI_precount(4,%r9),__TI_precount(%r9) | |
1da177e4 LT |
606 | b BASED(io_resume_loop) |
607 | #endif | |
608 | ||
609 | # | |
610 | # switch to kernel stack, then check the TIF bits | |
611 | # | |
612 | io_work: | |
613 | l %r1,__LC_KERNEL_STACK | |
614 | s %r1,BASED(.Lc_spsize) | |
615 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 616 | xc __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 LT |
617 | lr %r15,%r1 |
618 | # | |
619 | # One of the work bits is on. Find out which one. | |
54dfe5dd | 620 | # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGMASK, _TIF_NEED_RESCHED |
25d83cbf | 621 | # and _TIF_MCCK_PENDING |
1da177e4 LT |
622 | # |
623 | io_work_loop: | |
77fa2245 | 624 | tm __TI_flags+3(%r9),_TIF_MCCK_PENDING |
25d83cbf | 625 | bo BASED(io_mcck_pending) |
1da177e4 LT |
626 | tm __TI_flags+3(%r9),_TIF_NEED_RESCHED |
627 | bo BASED(io_reschedule) | |
54dfe5dd HC |
628 | tm __TI_flags+3(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK) |
629 | bnz BASED(io_sigpending) | |
523b44cf | 630 | LOCKDEP_SYS_EXIT |
1da177e4 LT |
631 | b BASED(io_leave) |
632 | ||
77fa2245 HC |
633 | # |
634 | # _TIF_MCCK_PENDING is set, call handler | |
635 | # | |
636 | io_mcck_pending: | |
b771aeac | 637 | TRACE_IRQS_OFF |
77fa2245 | 638 | l %r1,BASED(.Ls390_handle_mcck) |
b771aeac HC |
639 | basr %r14,%r1 # TIF bit will be cleared by handler |
640 | TRACE_IRQS_ON | |
641 | b BASED(io_work_loop) | |
77fa2245 | 642 | |
1da177e4 LT |
643 | # |
644 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
645 | # |
646 | io_reschedule: | |
647 | l %r1,BASED(.Lschedule) | |
648 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
649 | basr %r14,%r1 # call scheduler | |
650 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
1da177e4 | 651 | tm __TI_flags+3(%r9),_TIF_WORK_INT |
25d83cbf | 652 | bz BASED(io_leave) # there is no work to do |
1da177e4 LT |
653 | b BASED(io_work_loop) |
654 | ||
655 | # | |
54dfe5dd | 656 | # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal |
1da177e4 | 657 | # |
25d83cbf HC |
658 | io_sigpending: |
659 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
660 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
661 | l %r1,BASED(.Ldo_signal) | |
662 | basr %r14,%r1 # call do_signal | |
663 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
e1c3ad96 | 664 | b BASED(io_work_loop) |
1da177e4 LT |
665 | |
666 | /* | |
667 | * External interrupt handler routine | |
668 | */ | |
669 | ||
25d83cbf | 670 | .globl ext_int_handler |
1da177e4 LT |
671 | ext_int_handler: |
672 | STORE_TIMER __LC_ASYNC_ENTER_TIMER | |
673 | stck __LC_INT_CLOCK | |
674 | SAVE_ALL_BASE __LC_SAVE_AREA+16 | |
63b12246 | 675 | SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16 |
77fa2245 | 676 | CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16 |
1da177e4 LT |
677 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
678 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
679 | bz BASED(ext_no_vtime) | |
680 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
681 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
682 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
683 | ext_no_vtime: | |
684 | #endif | |
685 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
1f194a4c | 686 | TRACE_IRQS_OFF |
25d83cbf HC |
687 | la %r2,SP_PTREGS(%r15) # address of register-save area |
688 | lh %r3,__LC_EXT_INT_CODE # get interruption code | |
1da177e4 LT |
689 | l %r1,BASED(.Ldo_extint) |
690 | basr %r14,%r1 | |
1f194a4c | 691 | TRACE_IRQS_ON |
1da177e4 LT |
692 | b BASED(io_return) |
693 | ||
ae6aa2ea MS |
694 | __critical_end: |
695 | ||
1da177e4 LT |
696 | /* |
697 | * Machine check handler routines | |
698 | */ | |
699 | ||
25d83cbf | 700 | .globl mcck_int_handler |
1da177e4 | 701 | mcck_int_handler: |
77fa2245 HC |
702 | spt __LC_CPU_TIMER_SAVE_AREA # revalidate cpu timer |
703 | lm %r0,%r15,__LC_GPREGS_SAVE_AREA # revalidate gprs | |
1da177e4 | 704 | SAVE_ALL_BASE __LC_SAVE_AREA+32 |
77fa2245 | 705 | la %r12,__LC_MCK_OLD_PSW |
25d83cbf | 706 | tm __LC_MCCK_CODE,0x80 # system damage? |
77fa2245 | 707 | bo BASED(mcck_int_main) # yes -> rest of mcck code invalid |
1da177e4 | 708 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
63b12246 MS |
709 | mvc __LC_SAVE_AREA+52(8),__LC_ASYNC_ENTER_TIMER |
710 | mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA | |
711 | tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid? | |
712 | bo BASED(1f) | |
713 | la %r14,__LC_SYNC_ENTER_TIMER | |
714 | clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER | |
715 | bl BASED(0f) | |
716 | la %r14,__LC_ASYNC_ENTER_TIMER | |
717 | 0: clc 0(8,%r14),__LC_EXIT_TIMER | |
718 | bl BASED(0f) | |
719 | la %r14,__LC_EXIT_TIMER | |
720 | 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER | |
721 | bl BASED(0f) | |
722 | la %r14,__LC_LAST_UPDATE_TIMER | |
723 | 0: spt 0(%r14) | |
724 | mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14) | |
725 | 1: | |
1da177e4 | 726 | #endif |
63b12246 | 727 | tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid? |
77fa2245 HC |
728 | bno BASED(mcck_int_main) # no -> skip cleanup critical |
729 | tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit | |
730 | bnz BASED(mcck_int_main) # from user -> load async stack | |
731 | clc __LC_MCK_OLD_PSW+4(4),BASED(.Lcritical_end) | |
732 | bhe BASED(mcck_int_main) | |
733 | clc __LC_MCK_OLD_PSW+4(4),BASED(.Lcritical_start) | |
734 | bl BASED(mcck_int_main) | |
735 | l %r14,BASED(.Lcleanup_critical) | |
736 | basr %r14,%r14 | |
737 | mcck_int_main: | |
738 | l %r14,__LC_PANIC_STACK # are we already on the panic stack? | |
739 | slr %r14,%r15 | |
740 | sra %r14,PAGE_SHIFT | |
741 | be BASED(0f) | |
742 | l %r15,__LC_PANIC_STACK # load panic stack | |
743 | 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+32 | |
ae6aa2ea | 744 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
25d83cbf | 745 | tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid? |
ae6aa2ea | 746 | bno BASED(mcck_no_vtime) # no -> skip cleanup critical |
63b12246 | 747 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
ae6aa2ea MS |
748 | bz BASED(mcck_no_vtime) |
749 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
750 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
751 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
752 | mcck_no_vtime: | |
753 | #endif | |
77fa2245 HC |
754 | l %r9,__LC_THREAD_INFO # load pointer to thread_info struct |
755 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
25d83cbf HC |
756 | l %r1,BASED(.Ls390_mcck) |
757 | basr %r14,%r1 # call machine check handler | |
758 | tm SP_PSW+1(%r15),0x01 # returning to user ? | |
77fa2245 | 759 | bno BASED(mcck_return) |
25d83cbf | 760 | l %r1,__LC_KERNEL_STACK # switch to kernel stack |
77fa2245 HC |
761 | s %r1,BASED(.Lc_spsize) |
762 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 763 | xc __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
77fa2245 HC |
764 | lr %r15,%r1 |
765 | stosm __SF_EMPTY(%r15),0x04 # turn dat on | |
766 | tm __TI_flags+3(%r9),_TIF_MCCK_PENDING | |
767 | bno BASED(mcck_return) | |
1f194a4c | 768 | TRACE_IRQS_OFF |
77fa2245 HC |
769 | l %r1,BASED(.Ls390_handle_mcck) |
770 | basr %r14,%r1 # call machine check handler | |
1f194a4c | 771 | TRACE_IRQS_ON |
1da177e4 | 772 | mcck_return: |
63b12246 MS |
773 | mvc __LC_RETURN_MCCK_PSW(8),SP_PSW(%r15) # move return PSW |
774 | ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit | |
775 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
776 | mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+52 | |
777 | tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ? | |
778 | bno BASED(0f) | |
779 | lm %r0,%r15,SP_R0(%r15) # load gprs 0-15 | |
780 | stpt __LC_EXIT_TIMER | |
781 | lpsw __LC_RETURN_MCCK_PSW # back to caller | |
782 | 0: | |
783 | #endif | |
784 | lm %r0,%r15,SP_R0(%r15) # load gprs 0-15 | |
785 | lpsw __LC_RETURN_MCCK_PSW # back to caller | |
786 | ||
25d83cbf | 787 | RESTORE_ALL __LC_RETURN_MCCK_PSW,0 |
1da177e4 | 788 | |
1da177e4 LT |
789 | /* |
790 | * Restart interruption handler, kick starter for additional CPUs | |
791 | */ | |
84b36a8e HC |
792 | #ifdef CONFIG_SMP |
793 | #ifndef CONFIG_HOTPLUG_CPU | |
794 | .section .init.text,"ax" | |
795 | #endif | |
25d83cbf | 796 | .globl restart_int_handler |
1da177e4 | 797 | restart_int_handler: |
25d83cbf HC |
798 | l %r15,__LC_SAVE_AREA+60 # load ksp |
799 | lctl %c0,%c15,__LC_CREGS_SAVE_AREA # get new ctl regs | |
800 | lam %a0,%a15,__LC_AREGS_SAVE_AREA | |
801 | lm %r6,%r15,__SF_GPRS(%r15) # load registers from clone | |
802 | stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on | |
803 | basr %r14,0 | |
804 | l %r14,restart_addr-.(%r14) | |
805 | br %r14 # branch to start_secondary | |
1da177e4 | 806 | restart_addr: |
25d83cbf | 807 | .long start_secondary |
84b36a8e HC |
808 | #ifndef CONFIG_HOTPLUG_CPU |
809 | .previous | |
810 | #endif | |
1da177e4 LT |
811 | #else |
812 | /* | |
813 | * If we do not run with SMP enabled, let the new CPU crash ... | |
814 | */ | |
25d83cbf | 815 | .globl restart_int_handler |
1da177e4 | 816 | restart_int_handler: |
25d83cbf | 817 | basr %r1,0 |
1da177e4 | 818 | restart_base: |
25d83cbf HC |
819 | lpsw restart_crash-restart_base(%r1) |
820 | .align 8 | |
1da177e4 | 821 | restart_crash: |
25d83cbf | 822 | .long 0x000a0000,0x00000000 |
1da177e4 LT |
823 | restart_go: |
824 | #endif | |
825 | ||
826 | #ifdef CONFIG_CHECK_STACK | |
827 | /* | |
828 | * The synchronous or the asynchronous stack overflowed. We are dead. | |
829 | * No need to properly save the registers, we are going to panic anyway. | |
830 | * Setup a pt_regs so that show_trace can provide a good call trace. | |
831 | */ | |
832 | stack_overflow: | |
833 | l %r15,__LC_PANIC_STACK # change to panic stack | |
834 | sl %r15,BASED(.Lc_spsize) | |
835 | mvc SP_PSW(8,%r15),0(%r12) # move user PSW to stack | |
836 | stm %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack | |
837 | la %r1,__LC_SAVE_AREA | |
838 | ch %r12,BASED(.L0x020) # old psw addr == __LC_SVC_OLD_PSW ? | |
839 | be BASED(0f) | |
840 | ch %r12,BASED(.L0x028) # old psw addr == __LC_PGM_OLD_PSW ? | |
841 | be BASED(0f) | |
842 | la %r1,__LC_SAVE_AREA+16 | |
843 | 0: mvc SP_R12(16,%r15),0(%r1) # move %r12-%r15 to stack | |
25d83cbf | 844 | xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear back chain |
1da177e4 | 845 | l %r1,BASED(1f) # branch to kernel_stack_overflow |
25d83cbf | 846 | la %r2,SP_PTREGS(%r15) # load pt_regs |
1da177e4 | 847 | br %r1 |
25d83cbf | 848 | 1: .long kernel_stack_overflow |
1da177e4 LT |
849 | #endif |
850 | ||
851 | cleanup_table_system_call: | |
852 | .long system_call + 0x80000000, sysc_do_svc + 0x80000000 | |
853 | cleanup_table_sysc_return: | |
854 | .long sysc_return + 0x80000000, sysc_leave + 0x80000000 | |
855 | cleanup_table_sysc_leave: | |
856 | .long sysc_leave + 0x80000000, sysc_work_loop + 0x80000000 | |
857 | cleanup_table_sysc_work_loop: | |
858 | .long sysc_work_loop + 0x80000000, sysc_reschedule + 0x80000000 | |
63b12246 MS |
859 | cleanup_table_io_return: |
860 | .long io_return + 0x80000000, io_leave + 0x80000000 | |
ae6aa2ea MS |
861 | cleanup_table_io_leave: |
862 | .long io_leave + 0x80000000, io_done + 0x80000000 | |
863 | cleanup_table_io_work_loop: | |
864 | .long io_work_loop + 0x80000000, io_mcck_pending + 0x80000000 | |
1da177e4 LT |
865 | |
866 | cleanup_critical: | |
867 | clc 4(4,%r12),BASED(cleanup_table_system_call) | |
868 | bl BASED(0f) | |
869 | clc 4(4,%r12),BASED(cleanup_table_system_call+4) | |
870 | bl BASED(cleanup_system_call) | |
871 | 0: | |
872 | clc 4(4,%r12),BASED(cleanup_table_sysc_return) | |
873 | bl BASED(0f) | |
874 | clc 4(4,%r12),BASED(cleanup_table_sysc_return+4) | |
875 | bl BASED(cleanup_sysc_return) | |
876 | 0: | |
877 | clc 4(4,%r12),BASED(cleanup_table_sysc_leave) | |
878 | bl BASED(0f) | |
879 | clc 4(4,%r12),BASED(cleanup_table_sysc_leave+4) | |
880 | bl BASED(cleanup_sysc_leave) | |
881 | 0: | |
882 | clc 4(4,%r12),BASED(cleanup_table_sysc_work_loop) | |
883 | bl BASED(0f) | |
884 | clc 4(4,%r12),BASED(cleanup_table_sysc_work_loop+4) | |
77fa2245 | 885 | bl BASED(cleanup_sysc_return) |
63b12246 MS |
886 | 0: |
887 | clc 4(4,%r12),BASED(cleanup_table_io_return) | |
888 | bl BASED(0f) | |
889 | clc 4(4,%r12),BASED(cleanup_table_io_return+4) | |
890 | bl BASED(cleanup_io_return) | |
ae6aa2ea MS |
891 | 0: |
892 | clc 4(4,%r12),BASED(cleanup_table_io_leave) | |
893 | bl BASED(0f) | |
894 | clc 4(4,%r12),BASED(cleanup_table_io_leave+4) | |
895 | bl BASED(cleanup_io_leave) | |
896 | 0: | |
897 | clc 4(4,%r12),BASED(cleanup_table_io_work_loop) | |
898 | bl BASED(0f) | |
899 | clc 4(4,%r12),BASED(cleanup_table_io_work_loop+4) | |
900 | bl BASED(cleanup_io_return) | |
1da177e4 LT |
901 | 0: |
902 | br %r14 | |
903 | ||
904 | cleanup_system_call: | |
905 | mvc __LC_RETURN_PSW(8),0(%r12) | |
ae6aa2ea MS |
906 | c %r12,BASED(.Lmck_old_psw) |
907 | be BASED(0f) | |
908 | la %r12,__LC_SAVE_AREA+16 | |
909 | b BASED(1f) | |
910 | 0: la %r12,__LC_SAVE_AREA+32 | |
911 | 1: | |
1da177e4 LT |
912 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
913 | clc __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+4) | |
914 | bh BASED(0f) | |
915 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
916 | 0: clc __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+8) | |
917 | bhe BASED(cleanup_vtime) | |
918 | #endif | |
919 | clc __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn) | |
920 | bh BASED(0f) | |
ae6aa2ea MS |
921 | mvc __LC_SAVE_AREA(16),0(%r12) |
922 | 0: st %r13,4(%r12) | |
923 | st %r12,__LC_SAVE_AREA+48 # argh | |
63b12246 | 924 | SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 925 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
ae6aa2ea MS |
926 | l %r12,__LC_SAVE_AREA+48 # argh |
927 | st %r15,12(%r12) | |
1da177e4 LT |
928 | lh %r7,0x8a |
929 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
930 | cleanup_vtime: | |
931 | clc __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+12) | |
932 | bhe BASED(cleanup_stime) | |
933 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
934 | bz BASED(cleanup_novtime) | |
935 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
936 | cleanup_stime: | |
937 | clc __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+16) | |
938 | bh BASED(cleanup_update) | |
939 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
940 | cleanup_update: | |
941 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
942 | cleanup_novtime: | |
943 | #endif | |
944 | mvc __LC_RETURN_PSW+4(4),BASED(cleanup_table_system_call+4) | |
945 | la %r12,__LC_RETURN_PSW | |
946 | br %r14 | |
947 | cleanup_system_call_insn: | |
948 | .long sysc_saveall + 0x80000000 | |
949 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
25d83cbf HC |
950 | .long system_call + 0x80000000 |
951 | .long sysc_vtime + 0x80000000 | |
952 | .long sysc_stime + 0x80000000 | |
953 | .long sysc_update + 0x80000000 | |
1da177e4 LT |
954 | #endif |
955 | ||
956 | cleanup_sysc_return: | |
957 | mvc __LC_RETURN_PSW(4),0(%r12) | |
958 | mvc __LC_RETURN_PSW+4(4),BASED(cleanup_table_sysc_return) | |
959 | la %r12,__LC_RETURN_PSW | |
960 | br %r14 | |
961 | ||
962 | cleanup_sysc_leave: | |
963 | clc 4(4,%r12),BASED(cleanup_sysc_leave_insn) | |
ae6aa2ea | 964 | be BASED(2f) |
1da177e4 LT |
965 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
966 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
967 | clc 4(4,%r12),BASED(cleanup_sysc_leave_insn+4) | |
ae6aa2ea | 968 | be BASED(2f) |
1da177e4 LT |
969 | #endif |
970 | mvc __LC_RETURN_PSW(8),SP_PSW(%r15) | |
ae6aa2ea MS |
971 | c %r12,BASED(.Lmck_old_psw) |
972 | bne BASED(0f) | |
973 | mvc __LC_SAVE_AREA+32(16),SP_R12(%r15) | |
974 | b BASED(1f) | |
975 | 0: mvc __LC_SAVE_AREA+16(16),SP_R12(%r15) | |
976 | 1: lm %r0,%r11,SP_R0(%r15) | |
1da177e4 | 977 | l %r15,SP_R15(%r15) |
ae6aa2ea | 978 | 2: la %r12,__LC_RETURN_PSW |
1da177e4 LT |
979 | br %r14 |
980 | cleanup_sysc_leave_insn: | |
981 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
982 | .long sysc_leave + 14 + 0x80000000 | |
983 | #endif | |
984 | .long sysc_leave + 10 + 0x80000000 | |
985 | ||
ae6aa2ea MS |
986 | cleanup_io_return: |
987 | mvc __LC_RETURN_PSW(4),0(%r12) | |
988 | mvc __LC_RETURN_PSW+4(4),BASED(cleanup_table_io_work_loop) | |
989 | la %r12,__LC_RETURN_PSW | |
990 | br %r14 | |
991 | ||
992 | cleanup_io_leave: | |
993 | clc 4(4,%r12),BASED(cleanup_io_leave_insn) | |
994 | be BASED(2f) | |
995 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
996 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
997 | clc 4(4,%r12),BASED(cleanup_io_leave_insn+4) | |
998 | be BASED(2f) | |
999 | #endif | |
1000 | mvc __LC_RETURN_PSW(8),SP_PSW(%r15) | |
1001 | c %r12,BASED(.Lmck_old_psw) | |
1002 | bne BASED(0f) | |
1003 | mvc __LC_SAVE_AREA+32(16),SP_R12(%r15) | |
1004 | b BASED(1f) | |
1005 | 0: mvc __LC_SAVE_AREA+16(16),SP_R12(%r15) | |
1006 | 1: lm %r0,%r11,SP_R0(%r15) | |
1007 | l %r15,SP_R15(%r15) | |
1008 | 2: la %r12,__LC_RETURN_PSW | |
1009 | br %r14 | |
1010 | cleanup_io_leave_insn: | |
1011 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
1012 | .long io_leave + 18 + 0x80000000 | |
1013 | #endif | |
1014 | .long io_leave + 14 + 0x80000000 | |
1015 | ||
1da177e4 LT |
1016 | /* |
1017 | * Integer constants | |
1018 | */ | |
25d83cbf HC |
1019 | .align 4 |
1020 | .Lc_spsize: .long SP_SIZE | |
1021 | .Lc_overhead: .long STACK_FRAME_OVERHEAD | |
1022 | .Lc_pactive: .long PREEMPT_ACTIVE | |
1023 | .Lnr_syscalls: .long NR_syscalls | |
1024 | .L0x018: .short 0x018 | |
1025 | .L0x020: .short 0x020 | |
1026 | .L0x028: .short 0x028 | |
1027 | .L0x030: .short 0x030 | |
1028 | .L0x038: .short 0x038 | |
1029 | .Lc_1: .long 1 | |
1da177e4 LT |
1030 | |
1031 | /* | |
1032 | * Symbol constants | |
1033 | */ | |
25d83cbf | 1034 | .Ls390_mcck: .long s390_do_machine_check |
77fa2245 | 1035 | .Ls390_handle_mcck: |
25d83cbf HC |
1036 | .long s390_handle_mcck |
1037 | .Lmck_old_psw: .long __LC_MCK_OLD_PSW | |
1038 | .Ldo_IRQ: .long do_IRQ | |
1039 | .Ldo_extint: .long do_extint | |
1040 | .Ldo_signal: .long do_signal | |
1041 | .Lhandle_per: .long do_single_step | |
03ff9a23 MS |
1042 | .Ldo_execve: .long do_execve |
1043 | .Lexecve_tail: .long execve_tail | |
25d83cbf HC |
1044 | .Ljump_table: .long pgm_check_table |
1045 | .Lschedule: .long schedule | |
25d83cbf | 1046 | .Ltrace: .long syscall_trace |
25d83cbf HC |
1047 | .Lschedtail: .long schedule_tail |
1048 | .Lsysc_table: .long sys_call_table | |
1f194a4c | 1049 | #ifdef CONFIG_TRACE_IRQFLAGS |
25d83cbf | 1050 | .Ltrace_irq_on: .long trace_hardirqs_on |
1f194a4c | 1051 | .Ltrace_irq_off: |
25d83cbf | 1052 | .long trace_hardirqs_off |
523b44cf HC |
1053 | .Llockdep_sys_exit: |
1054 | .long lockdep_sys_exit | |
1f194a4c | 1055 | #endif |
1da177e4 | 1056 | .Lcritical_start: |
25d83cbf | 1057 | .long __critical_start + 0x80000000 |
1da177e4 | 1058 | .Lcritical_end: |
25d83cbf | 1059 | .long __critical_end + 0x80000000 |
1da177e4 | 1060 | .Lcleanup_critical: |
25d83cbf | 1061 | .long cleanup_critical |
1da177e4 | 1062 | |
25d83cbf | 1063 | .section .rodata, "a" |
1da177e4 | 1064 | #define SYSCALL(esa,esame,emu) .long esa |
1da177e4 LT |
1065 | sys_call_table: |
1066 | #include "syscalls.S" | |
1067 | #undef SYSCALL |