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Commit | Line | Data |
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1da177e4 | 1 | /* |
54dfe5dd | 2 | * arch/s390/kernel/entry64.S |
1da177e4 LT |
3 | * S390 low-level entry points. |
4 | * | |
54dfe5dd | 5 | * Copyright (C) IBM Corp. 1999,2006 |
1da177e4 | 6 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), |
25d83cbf HC |
7 | * Hartmut Penner (hp@de.ibm.com), |
8 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
77fa2245 | 9 | * Heiko Carstens <heiko.carstens@de.ibm.com> |
1da177e4 LT |
10 | */ |
11 | ||
12 | #include <linux/sys.h> | |
13 | #include <linux/linkage.h> | |
1da177e4 LT |
14 | #include <asm/cache.h> |
15 | #include <asm/lowcore.h> | |
16 | #include <asm/errno.h> | |
17 | #include <asm/ptrace.h> | |
18 | #include <asm/thread_info.h> | |
0013a854 | 19 | #include <asm/asm-offsets.h> |
1da177e4 LT |
20 | #include <asm/unistd.h> |
21 | #include <asm/page.h> | |
22 | ||
23 | /* | |
24 | * Stack layout for the system_call stack entry. | |
25 | * The first few entries are identical to the user_regs_struct. | |
26 | */ | |
25d83cbf HC |
27 | SP_PTREGS = STACK_FRAME_OVERHEAD |
28 | SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS | |
29 | SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW | |
30 | SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS | |
31 | SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8 | |
32 | SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16 | |
33 | SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24 | |
34 | SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32 | |
35 | SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40 | |
36 | SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48 | |
37 | SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56 | |
38 | SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64 | |
39 | SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72 | |
40 | SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80 | |
41 | SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88 | |
42 | SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96 | |
43 | SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104 | |
44 | SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112 | |
45 | SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120 | |
46 | SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2 | |
47 | SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC | |
48 | SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP | |
49 | SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE | |
1da177e4 LT |
50 | |
51 | STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER | |
52 | STACK_SIZE = 1 << STACK_SHIFT | |
53 | ||
54dfe5dd HC |
54 | _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \ |
55 | _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) | |
56 | _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \ | |
57 | _TIF_MCCK_PENDING) | |
1da177e4 LT |
58 | |
59 | #define BASED(name) name-system_call(%r13) | |
60 | ||
1f194a4c HC |
61 | #ifdef CONFIG_TRACE_IRQFLAGS |
62 | .macro TRACE_IRQS_ON | |
63 | brasl %r14,trace_hardirqs_on | |
64 | .endm | |
65 | ||
66 | .macro TRACE_IRQS_OFF | |
67 | brasl %r14,trace_hardirqs_off | |
68 | .endm | |
69 | #else | |
70 | #define TRACE_IRQS_ON | |
71 | #define TRACE_IRQS_OFF | |
72 | #endif | |
73 | ||
25d83cbf | 74 | .macro STORE_TIMER lc_offset |
1da177e4 LT |
75 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
76 | stpt \lc_offset | |
77 | #endif | |
78 | .endm | |
79 | ||
80 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
25d83cbf | 81 | .macro UPDATE_VTIME lc_from,lc_to,lc_sum |
1da177e4 LT |
82 | lg %r10,\lc_from |
83 | slg %r10,\lc_to | |
84 | alg %r10,\lc_sum | |
85 | stg %r10,\lc_sum | |
86 | .endm | |
87 | #endif | |
88 | ||
89 | /* | |
90 | * Register usage in interrupt handlers: | |
91 | * R9 - pointer to current task structure | |
92 | * R13 - pointer to literal pool | |
93 | * R14 - return register for function calls | |
94 | * R15 - kernel stack pointer | |
95 | */ | |
96 | ||
25d83cbf | 97 | .macro SAVE_ALL_BASE savearea |
1da177e4 LT |
98 | stmg %r12,%r15,\savearea |
99 | larl %r13,system_call | |
100 | .endm | |
101 | ||
987ad70a MS |
102 | .macro SAVE_ALL_SVC psworg,savearea |
103 | la %r12,\psworg | |
104 | lg %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
105 | .endm | |
106 | ||
63b12246 | 107 | .macro SAVE_ALL_SYNC psworg,savearea |
1da177e4 | 108 | la %r12,\psworg |
1da177e4 LT |
109 | tm \psworg+1,0x01 # test problem state bit |
110 | jz 2f # skip stack setup save | |
111 | lg %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
63b12246 MS |
112 | #ifdef CONFIG_CHECK_STACK |
113 | j 3f | |
114 | 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
115 | jz stack_overflow | |
116 | 3: | |
117 | #endif | |
118 | 2: | |
119 | .endm | |
120 | ||
121 | .macro SAVE_ALL_ASYNC psworg,savearea | |
122 | la %r12,\psworg | |
1da177e4 LT |
123 | tm \psworg+1,0x01 # test problem state bit |
124 | jnz 1f # from user -> load kernel stack | |
125 | clc \psworg+8(8),BASED(.Lcritical_end) | |
126 | jhe 0f | |
127 | clc \psworg+8(8),BASED(.Lcritical_start) | |
128 | jl 0f | |
129 | brasl %r14,cleanup_critical | |
6add9f7f | 130 | tm 1(%r12),0x01 # retest problem state after cleanup |
1da177e4 LT |
131 | jnz 1f |
132 | 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ? | |
133 | slgr %r14,%r15 | |
134 | srag %r14,%r14,STACK_SHIFT | |
135 | jz 2f | |
136 | 1: lg %r15,__LC_ASYNC_STACK # load async stack | |
1da177e4 LT |
137 | #ifdef CONFIG_CHECK_STACK |
138 | j 3f | |
139 | 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
140 | jz stack_overflow | |
141 | 3: | |
142 | #endif | |
77fa2245 HC |
143 | 2: |
144 | .endm | |
145 | ||
146 | .macro CREATE_STACK_FRAME psworg,savearea | |
25d83cbf HC |
147 | aghi %r15,-SP_SIZE # make room for registers & psw |
148 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack | |
1da177e4 LT |
149 | la %r12,\psworg |
150 | stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 | |
151 | icm %r12,12,__LC_SVC_ILC | |
152 | stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack | |
153 | st %r12,SP_ILC(%r15) | |
154 | mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack | |
155 | la %r12,0 | |
156 | stg %r12,__SF_BACKCHAIN(%r15) | |
25d83cbf | 157 | .endm |
1da177e4 | 158 | |
ae6aa2ea MS |
159 | .macro RESTORE_ALL psworg,sync |
160 | mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore | |
1da177e4 | 161 | .if !\sync |
ae6aa2ea | 162 | ni \psworg+1,0xfd # clear wait state bit |
1da177e4 LT |
163 | .endif |
164 | lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user | |
165 | STORE_TIMER __LC_EXIT_TIMER | |
ae6aa2ea | 166 | lpswe \psworg # back to caller |
1da177e4 LT |
167 | .endm |
168 | ||
169 | /* | |
170 | * Scheduler resume function, called by switch_to | |
171 | * gpr2 = (task_struct *) prev | |
172 | * gpr3 = (task_struct *) next | |
173 | * Returns: | |
174 | * gpr2 = prev | |
175 | */ | |
25d83cbf | 176 | .globl __switch_to |
1da177e4 LT |
177 | __switch_to: |
178 | tm __THREAD_per+4(%r3),0xe8 # is the new process using per ? | |
179 | jz __switch_to_noper # if not we're fine | |
25d83cbf HC |
180 | stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff |
181 | clc __THREAD_per(24,%r3),__SF_EMPTY(%r15) | |
182 | je __switch_to_noper # we got away without bashing TLB's | |
183 | lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't | |
1da177e4 | 184 | __switch_to_noper: |
25d83cbf | 185 | lg %r4,__THREAD_info(%r2) # get thread_info of prev |
77fa2245 HC |
186 | tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending? |
187 | jz __switch_to_no_mcck | |
188 | ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev | |
189 | lg %r4,__THREAD_info(%r3) # get thread_info of next | |
190 | oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next | |
191 | __switch_to_no_mcck: | |
25d83cbf | 192 | stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task |
1da177e4 LT |
193 | stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp |
194 | lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp | |
25d83cbf | 195 | lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task |
1da177e4 LT |
196 | stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct |
197 | lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 | |
25d83cbf | 198 | lg %r3,__THREAD_info(%r3) # load thread_info from task struct |
1da177e4 LT |
199 | stg %r3,__LC_THREAD_INFO |
200 | aghi %r3,STACK_SIZE | |
201 | stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack | |
202 | br %r14 | |
203 | ||
204 | __critical_start: | |
205 | /* | |
206 | * SVC interrupt handler routine. System calls are synchronous events and | |
207 | * are executed with interrupts enabled. | |
208 | */ | |
209 | ||
25d83cbf | 210 | .globl system_call |
1da177e4 LT |
211 | system_call: |
212 | STORE_TIMER __LC_SYNC_ENTER_TIMER | |
213 | sysc_saveall: | |
214 | SAVE_ALL_BASE __LC_SAVE_AREA | |
987ad70a | 215 | SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
25d83cbf HC |
216 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
217 | llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore | |
1da177e4 LT |
218 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
219 | sysc_vtime: | |
220 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
221 | jz sysc_do_svc | |
222 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
223 | sysc_stime: | |
224 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
225 | sysc_update: | |
226 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
227 | #endif | |
228 | sysc_do_svc: | |
229 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
25d83cbf | 230 | slag %r7,%r7,2 # *4 and test for svc 0 |
1da177e4 LT |
231 | jnz sysc_nr_ok |
232 | # svc 0: system call number in %r1 | |
233 | cl %r1,BASED(.Lnr_syscalls) | |
234 | jnl sysc_nr_ok | |
25d83cbf HC |
235 | lgfr %r7,%r1 # clear high word in r1 |
236 | slag %r7,%r7,2 # svc 0: system call number in %r1 | |
1da177e4 LT |
237 | sysc_nr_ok: |
238 | mvc SP_ARGS(8,%r15),SP_R7(%r15) | |
239 | sysc_do_restart: | |
25d83cbf | 240 | larl %r10,sys_call_table |
347a8dc3 | 241 | #ifdef CONFIG_COMPAT |
c563077e HC |
242 | tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ? |
243 | jno sysc_noemu | |
25d83cbf | 244 | larl %r10,sys_call_table_emu # use 31 bit emulation system calls |
1da177e4 LT |
245 | sysc_noemu: |
246 | #endif | |
247 | tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) | |
25d83cbf HC |
248 | lgf %r8,0(%r7,%r10) # load address of system call routine |
249 | jnz sysc_tracesys | |
250 | basr %r14,%r8 # call sys_xxxx | |
251 | stg %r2,SP_R2(%r15) # store return value (change R2 on stack) | |
1da177e4 LT |
252 | |
253 | sysc_return: | |
25d83cbf HC |
254 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
255 | jno sysc_leave | |
1da177e4 | 256 | tm __TI_flags+7(%r9),_TIF_WORK_SVC |
25d83cbf | 257 | jnz sysc_work # there is work to do (signals etc.) |
1da177e4 | 258 | sysc_leave: |
25d83cbf | 259 | RESTORE_ALL __LC_RETURN_PSW,1 |
1da177e4 LT |
260 | |
261 | # | |
262 | # recheck if there is more work to do | |
263 | # | |
264 | sysc_work_loop: | |
265 | tm __TI_flags+7(%r9),_TIF_WORK_SVC | |
25d83cbf | 266 | jz sysc_leave # there is no work to do |
1da177e4 LT |
267 | # |
268 | # One of the work bits is on. Find out which one. | |
269 | # | |
270 | sysc_work: | |
77fa2245 HC |
271 | tm __TI_flags+7(%r9),_TIF_MCCK_PENDING |
272 | jo sysc_mcck_pending | |
1da177e4 LT |
273 | tm __TI_flags+7(%r9),_TIF_NEED_RESCHED |
274 | jo sysc_reschedule | |
54dfe5dd HC |
275 | tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK) |
276 | jnz sysc_sigpending | |
1da177e4 LT |
277 | tm __TI_flags+7(%r9),_TIF_RESTART_SVC |
278 | jo sysc_restart | |
279 | tm __TI_flags+7(%r9),_TIF_SINGLE_STEP | |
280 | jo sysc_singlestep | |
281 | j sysc_leave | |
282 | ||
283 | # | |
284 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
285 | # |
286 | sysc_reschedule: | |
287 | larl %r14,sysc_work_loop | |
288 | jg schedule # return point is sysc_return | |
1da177e4 | 289 | |
77fa2245 HC |
290 | # |
291 | # _TIF_MCCK_PENDING is set, call handler | |
292 | # | |
293 | sysc_mcck_pending: | |
294 | larl %r14,sysc_work_loop | |
25d83cbf | 295 | jg s390_handle_mcck # TIF bit will be cleared by handler |
77fa2245 | 296 | |
1da177e4 | 297 | # |
54dfe5dd | 298 | # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal |
1da177e4 | 299 | # |
25d83cbf | 300 | sysc_sigpending: |
1da177e4 | 301 | ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP |
25d83cbf HC |
302 | la %r2,SP_PTREGS(%r15) # load pt_regs |
303 | brasl %r14,do_signal # call do_signal | |
1da177e4 LT |
304 | tm __TI_flags+7(%r9),_TIF_RESTART_SVC |
305 | jo sysc_restart | |
306 | tm __TI_flags+7(%r9),_TIF_SINGLE_STEP | |
307 | jo sysc_singlestep | |
e1c3ad96 | 308 | j sysc_work_loop |
1da177e4 LT |
309 | |
310 | # | |
311 | # _TIF_RESTART_SVC is set, set up registers and restart svc | |
312 | # | |
313 | sysc_restart: | |
314 | ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC | |
25d83cbf HC |
315 | lg %r7,SP_R2(%r15) # load new svc number |
316 | slag %r7,%r7,2 # *4 | |
1da177e4 | 317 | mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument |
25d83cbf HC |
318 | lmg %r2,%r6,SP_R2(%r15) # load svc arguments |
319 | j sysc_do_restart # restart svc | |
1da177e4 LT |
320 | |
321 | # | |
322 | # _TIF_SINGLE_STEP is set, call do_single_step | |
323 | # | |
324 | sysc_singlestep: | |
325 | ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP | |
326 | lhi %r0,__LC_PGM_OLD_PSW | |
327 | sth %r0,SP_TRAP(%r15) # set trap indication to pgm check | |
328 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
329 | larl %r14,sysc_return # load adr. of system return | |
330 | jg do_single_step # branch to do_sigtrap | |
331 | ||
1da177e4 LT |
332 | # |
333 | # call syscall_trace before and after system call | |
334 | # special linkage: %r12 contains the return address for trace_svc | |
335 | # | |
336 | sysc_tracesys: | |
25d83cbf | 337 | la %r2,SP_PTREGS(%r15) # load pt_regs |
1da177e4 LT |
338 | la %r3,0 |
339 | srl %r7,2 | |
25d83cbf HC |
340 | stg %r7,SP_R2(%r15) |
341 | brasl %r14,syscall_trace | |
1da177e4 LT |
342 | lghi %r0,NR_syscalls |
343 | clg %r0,SP_R2(%r15) | |
344 | jnh sysc_tracenogo | |
25d83cbf HC |
345 | lg %r7,SP_R2(%r15) # strace might have changed the |
346 | sll %r7,2 # system call | |
1da177e4 LT |
347 | lgf %r8,0(%r7,%r10) |
348 | sysc_tracego: | |
25d83cbf HC |
349 | lmg %r3,%r6,SP_R3(%r15) |
350 | lg %r2,SP_ORIG_R2(%r15) | |
351 | basr %r14,%r8 # call sys_xxx | |
352 | stg %r2,SP_R2(%r15) # store return value | |
1da177e4 LT |
353 | sysc_tracenogo: |
354 | tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) | |
25d83cbf HC |
355 | jz sysc_return |
356 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 | 357 | la %r3,1 |
25d83cbf | 358 | larl %r14,sysc_return # return point is sysc_return |
1da177e4 LT |
359 | jg syscall_trace |
360 | ||
361 | # | |
362 | # a new process exits the kernel with ret_from_fork | |
363 | # | |
25d83cbf | 364 | .globl ret_from_fork |
1da177e4 LT |
365 | ret_from_fork: |
366 | lg %r13,__LC_SVC_NEW_PSW+8 | |
367 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
368 | tm SP_PSW+1(%r15),0x01 # forking a kernel thread ? | |
369 | jo 0f | |
370 | stg %r15,SP_R15(%r15) # store stack pointer for new kthread | |
25d83cbf | 371 | 0: brasl %r14,schedule_tail |
1f194a4c | 372 | TRACE_IRQS_ON |
25d83cbf | 373 | stosm 24(%r15),0x03 # reenable interrupts |
1da177e4 LT |
374 | j sysc_return |
375 | ||
376 | # | |
03ff9a23 MS |
377 | # kernel_execve function needs to deal with pt_regs that is not |
378 | # at the usual place | |
1da177e4 | 379 | # |
03ff9a23 MS |
380 | .globl kernel_execve |
381 | kernel_execve: | |
382 | stmg %r12,%r15,96(%r15) | |
383 | lgr %r14,%r15 | |
384 | aghi %r15,-SP_SIZE | |
385 | stg %r14,__SF_BACKCHAIN(%r15) | |
386 | la %r12,SP_PTREGS(%r15) | |
387 | xc 0(__PT_SIZE,%r12),0(%r12) | |
388 | lgr %r5,%r12 | |
389 | brasl %r14,do_execve | |
390 | ltgfr %r2,%r2 | |
391 | je 0f | |
392 | aghi %r15,SP_SIZE | |
393 | lmg %r12,%r15,96(%r15) | |
394 | br %r14 | |
395 | # execve succeeded. | |
396 | 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts | |
397 | lg %r15,__LC_KERNEL_STACK # load ksp | |
398 | aghi %r15,-SP_SIZE # make room for registers & psw | |
399 | lg %r13,__LC_SVC_NEW_PSW+8 | |
400 | lg %r9,__LC_THREAD_INFO | |
401 | mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs | |
402 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) | |
403 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
404 | brasl %r14,execve_tail | |
405 | j sysc_return | |
1da177e4 LT |
406 | |
407 | /* | |
408 | * Program check handler routine | |
409 | */ | |
410 | ||
25d83cbf | 411 | .globl pgm_check_handler |
1da177e4 LT |
412 | pgm_check_handler: |
413 | /* | |
414 | * First we need to check for a special case: | |
415 | * Single stepping an instruction that disables the PER event mask will | |
416 | * cause a PER event AFTER the mask has been set. Example: SVC or LPSW. | |
417 | * For a single stepped SVC the program check handler gets control after | |
418 | * the SVC new PSW has been loaded. But we want to execute the SVC first and | |
419 | * then handle the PER event. Therefore we update the SVC old PSW to point | |
420 | * to the pgm_check_handler and branch to the SVC handler after we checked | |
421 | * if we have to load the kernel stack register. | |
422 | * For every other possible cause for PER event without the PER mask set | |
423 | * we just ignore the PER event (FIXME: is there anything we have to do | |
424 | * for LPSW?). | |
425 | */ | |
426 | STORE_TIMER __LC_SYNC_ENTER_TIMER | |
427 | SAVE_ALL_BASE __LC_SAVE_AREA | |
25d83cbf HC |
428 | tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception |
429 | jnz pgm_per # got per exception -> special case | |
63b12246 | 430 | SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 431 | CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
432 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
433 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
434 | jz pgm_no_vtime | |
435 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
436 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
437 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
438 | pgm_no_vtime: | |
439 | #endif | |
440 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
25d83cbf | 441 | lgf %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 LT |
442 | lghi %r8,0x7f |
443 | ngr %r8,%r3 | |
444 | pgm_do_call: | |
25d83cbf HC |
445 | sll %r8,3 |
446 | larl %r1,pgm_check_table | |
447 | lg %r1,0(%r8,%r1) # load address of handler routine | |
448 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
1da177e4 | 449 | larl %r14,sysc_return |
25d83cbf | 450 | br %r1 # branch to interrupt-handler |
1da177e4 LT |
451 | |
452 | # | |
453 | # handle per exception | |
454 | # | |
455 | pgm_per: | |
25d83cbf HC |
456 | tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on |
457 | jnz pgm_per_std # ok, normal per event from user space | |
1da177e4 | 458 | # ok its one of the special cases, now we need to find out which one |
25d83cbf HC |
459 | clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW |
460 | je pgm_svcper | |
1da177e4 LT |
461 | # no interesting special case, ignore PER event |
462 | lmg %r12,%r15,__LC_SAVE_AREA | |
25d83cbf | 463 | lpswe __LC_PGM_OLD_PSW |
1da177e4 LT |
464 | |
465 | # | |
466 | # Normal per exception | |
467 | # | |
468 | pgm_per_std: | |
63b12246 | 469 | SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 470 | CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
471 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
472 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
473 | jz pgm_no_vtime2 | |
474 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
475 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
476 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
477 | pgm_no_vtime2: | |
478 | #endif | |
479 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
480 | lg %r1,__TI_task(%r9) | |
4ba069b8 MG |
481 | tm SP_PSW+1(%r15),0x01 # kernel per event ? |
482 | jz kernel_per | |
1da177e4 LT |
483 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID |
484 | mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS | |
485 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
486 | oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP | |
25d83cbf | 487 | lgf %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 | 488 | lghi %r8,0x7f |
25d83cbf | 489 | ngr %r8,%r3 # clear per-event-bit and ilc |
1da177e4 LT |
490 | je sysc_return |
491 | j pgm_do_call | |
492 | ||
493 | # | |
494 | # it was a single stepped SVC that is causing all the trouble | |
495 | # | |
496 | pgm_svcper: | |
63b12246 | 497 | SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 498 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
499 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
500 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
501 | jz pgm_no_vtime3 | |
502 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
503 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
504 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
505 | pgm_no_vtime3: | |
506 | #endif | |
25d83cbf | 507 | llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore |
1da177e4 LT |
508 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct |
509 | lg %r1,__TI_task(%r9) | |
510 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID | |
511 | mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS | |
512 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
513 | oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP | |
1f194a4c | 514 | TRACE_IRQS_ON |
1da177e4 LT |
515 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
516 | j sysc_do_svc | |
517 | ||
4ba069b8 MG |
518 | # |
519 | # per was called from kernel, must be kprobes | |
520 | # | |
521 | kernel_per: | |
522 | lhi %r0,__LC_PGM_OLD_PSW | |
523 | sth %r0,SP_TRAP(%r15) # set trap indication to pgm check | |
524 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
525 | larl %r14,sysc_leave # load adr. of system ret, no work | |
526 | jg do_single_step # branch to do_single_step | |
527 | ||
1da177e4 LT |
528 | /* |
529 | * IO interrupt handler routine | |
530 | */ | |
25d83cbf | 531 | .globl io_int_handler |
1da177e4 LT |
532 | io_int_handler: |
533 | STORE_TIMER __LC_ASYNC_ENTER_TIMER | |
534 | stck __LC_INT_CLOCK | |
535 | SAVE_ALL_BASE __LC_SAVE_AREA+32 | |
63b12246 | 536 | SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32 |
77fa2245 | 537 | CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32 |
1da177e4 LT |
538 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
539 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
540 | jz io_no_vtime | |
541 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
542 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
543 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
544 | io_no_vtime: | |
545 | #endif | |
546 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
1f194a4c | 547 | TRACE_IRQS_OFF |
25d83cbf HC |
548 | la %r2,SP_PTREGS(%r15) # address of register-save area |
549 | brasl %r14,do_IRQ # call standard irq handler | |
1f194a4c | 550 | TRACE_IRQS_ON |
1da177e4 LT |
551 | |
552 | io_return: | |
25d83cbf | 553 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
1da177e4 | 554 | #ifdef CONFIG_PREEMPT |
25d83cbf | 555 | jno io_preempt # no -> check for preemptive scheduling |
1da177e4 | 556 | #else |
25d83cbf | 557 | jno io_leave # no-> skip resched & signal |
1da177e4 LT |
558 | #endif |
559 | tm __TI_flags+7(%r9),_TIF_WORK_INT | |
25d83cbf | 560 | jnz io_work # there is work to do (signals etc.) |
1da177e4 | 561 | io_leave: |
25d83cbf | 562 | RESTORE_ALL __LC_RETURN_PSW,0 |
ae6aa2ea | 563 | io_done: |
1da177e4 LT |
564 | |
565 | #ifdef CONFIG_PREEMPT | |
566 | io_preempt: | |
25d83cbf HC |
567 | icm %r0,15,__TI_precount(%r9) |
568 | jnz io_leave | |
1da177e4 LT |
569 | # switch to kernel stack |
570 | lg %r1,SP_R15(%r15) | |
571 | aghi %r1,-SP_SIZE | |
572 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 573 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 LT |
574 | lgr %r15,%r1 |
575 | io_resume_loop: | |
576 | tm __TI_flags+7(%r9),_TIF_NEED_RESCHED | |
577 | jno io_leave | |
25d83cbf HC |
578 | larl %r1,.Lc_pactive |
579 | mvc __TI_precount(4,%r9),0(%r1) | |
580 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
581 | brasl %r14,schedule # call schedule | |
582 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
583 | xc __TI_precount(4,%r9),__TI_precount(%r9) | |
1da177e4 LT |
584 | j io_resume_loop |
585 | #endif | |
586 | ||
587 | # | |
588 | # switch to kernel stack, then check TIF bits | |
589 | # | |
590 | io_work: | |
591 | lg %r1,__LC_KERNEL_STACK | |
592 | aghi %r1,-SP_SIZE | |
593 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 594 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 LT |
595 | lgr %r15,%r1 |
596 | # | |
597 | # One of the work bits is on. Find out which one. | |
54dfe5dd HC |
598 | # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED |
599 | # and _TIF_MCCK_PENDING | |
1da177e4 LT |
600 | # |
601 | io_work_loop: | |
77fa2245 HC |
602 | tm __TI_flags+7(%r9),_TIF_MCCK_PENDING |
603 | jo io_mcck_pending | |
1da177e4 LT |
604 | tm __TI_flags+7(%r9),_TIF_NEED_RESCHED |
605 | jo io_reschedule | |
54dfe5dd HC |
606 | tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK) |
607 | jnz io_sigpending | |
1da177e4 LT |
608 | j io_leave |
609 | ||
77fa2245 HC |
610 | # |
611 | # _TIF_MCCK_PENDING is set, call handler | |
612 | # | |
613 | io_mcck_pending: | |
b771aeac HC |
614 | TRACE_IRQS_OFF |
615 | brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler | |
616 | TRACE_IRQS_ON | |
617 | j io_work_loop | |
77fa2245 | 618 | |
1da177e4 LT |
619 | # |
620 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
621 | # |
622 | io_reschedule: | |
623 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
624 | brasl %r14,schedule # call scheduler | |
625 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
1da177e4 LT |
626 | tm __TI_flags+7(%r9),_TIF_WORK_INT |
627 | jz io_leave # there is no work to do | |
628 | j io_work_loop | |
629 | ||
630 | # | |
54dfe5dd | 631 | # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal |
1da177e4 | 632 | # |
25d83cbf HC |
633 | io_sigpending: |
634 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
635 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 | 636 | brasl %r14,do_signal # call do_signal |
25d83cbf | 637 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts |
e1c3ad96 | 638 | j io_work_loop |
1da177e4 LT |
639 | |
640 | /* | |
641 | * External interrupt handler routine | |
642 | */ | |
25d83cbf | 643 | .globl ext_int_handler |
1da177e4 LT |
644 | ext_int_handler: |
645 | STORE_TIMER __LC_ASYNC_ENTER_TIMER | |
646 | stck __LC_INT_CLOCK | |
647 | SAVE_ALL_BASE __LC_SAVE_AREA+32 | |
63b12246 | 648 | SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32 |
77fa2245 | 649 | CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32 |
1da177e4 LT |
650 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
651 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
652 | jz ext_no_vtime | |
653 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
654 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
655 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
656 | ext_no_vtime: | |
657 | #endif | |
658 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
1f194a4c | 659 | TRACE_IRQS_OFF |
25d83cbf HC |
660 | la %r2,SP_PTREGS(%r15) # address of register-save area |
661 | llgh %r3,__LC_EXT_INT_CODE # get interruption code | |
662 | brasl %r14,do_extint | |
1f194a4c | 663 | TRACE_IRQS_ON |
1da177e4 LT |
664 | j io_return |
665 | ||
ae6aa2ea MS |
666 | __critical_end: |
667 | ||
1da177e4 LT |
668 | /* |
669 | * Machine check handler routines | |
670 | */ | |
25d83cbf | 671 | .globl mcck_int_handler |
1da177e4 | 672 | mcck_int_handler: |
77fa2245 HC |
673 | la %r1,4095 # revalidate r1 |
674 | spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer | |
25d83cbf | 675 | lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs |
1da177e4 | 676 | SAVE_ALL_BASE __LC_SAVE_AREA+64 |
77fa2245 | 677 | la %r12,__LC_MCK_OLD_PSW |
25d83cbf | 678 | tm __LC_MCCK_CODE,0x80 # system damage? |
77fa2245 | 679 | jo mcck_int_main # yes -> rest of mcck code invalid |
1da177e4 | 680 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
63b12246 MS |
681 | la %r14,4095 |
682 | mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER | |
683 | mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14) | |
684 | tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid? | |
685 | jo 1f | |
686 | la %r14,__LC_SYNC_ENTER_TIMER | |
687 | clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER | |
688 | jl 0f | |
689 | la %r14,__LC_ASYNC_ENTER_TIMER | |
690 | 0: clc 0(8,%r14),__LC_EXIT_TIMER | |
691 | jl 0f | |
692 | la %r14,__LC_EXIT_TIMER | |
693 | 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER | |
694 | jl 0f | |
695 | la %r14,__LC_LAST_UPDATE_TIMER | |
696 | 0: spt 0(%r14) | |
697 | mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14) | |
698 | 1: | |
1da177e4 | 699 | #endif |
63b12246 | 700 | tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid? |
77fa2245 | 701 | jno mcck_int_main # no -> skip cleanup critical |
25d83cbf | 702 | tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit |
77fa2245 HC |
703 | jnz mcck_int_main # from user -> load kernel stack |
704 | clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end) | |
705 | jhe mcck_int_main | |
25d83cbf | 706 | clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start) |
77fa2245 | 707 | jl mcck_int_main |
25d83cbf | 708 | brasl %r14,cleanup_critical |
77fa2245 | 709 | mcck_int_main: |
25d83cbf | 710 | lg %r14,__LC_PANIC_STACK # are we already on the panic stack? |
77fa2245 HC |
711 | slgr %r14,%r15 |
712 | srag %r14,%r14,PAGE_SHIFT | |
713 | jz 0f | |
25d83cbf | 714 | lg %r15,__LC_PANIC_STACK # load panic stack |
77fa2245 | 715 | 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64 |
ae6aa2ea MS |
716 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
717 | tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid? | |
718 | jno mcck_no_vtime # no -> no timer update | |
63b12246 | 719 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
ae6aa2ea MS |
720 | jz mcck_no_vtime |
721 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
722 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
723 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
724 | mcck_no_vtime: | |
725 | #endif | |
77fa2245 HC |
726 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct |
727 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
728 | brasl %r14,s390_do_machine_check | |
25d83cbf | 729 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
77fa2245 HC |
730 | jno mcck_return |
731 | lg %r1,__LC_KERNEL_STACK # switch to kernel stack | |
732 | aghi %r1,-SP_SIZE | |
733 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
734 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain | |
735 | lgr %r15,%r1 | |
736 | stosm __SF_EMPTY(%r15),0x04 # turn dat on | |
737 | tm __TI_flags+7(%r9),_TIF_MCCK_PENDING | |
738 | jno mcck_return | |
1f194a4c | 739 | TRACE_IRQS_OFF |
77fa2245 | 740 | brasl %r14,s390_handle_mcck |
1f194a4c | 741 | TRACE_IRQS_ON |
1da177e4 | 742 | mcck_return: |
63b12246 MS |
743 | mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW |
744 | ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit | |
745 | lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 | |
746 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
747 | mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104 | |
748 | tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ? | |
749 | jno 0f | |
750 | stpt __LC_EXIT_TIMER | |
751 | 0: | |
752 | #endif | |
753 | lpswe __LC_RETURN_MCCK_PSW # back to caller | |
1da177e4 | 754 | |
1da177e4 LT |
755 | /* |
756 | * Restart interruption handler, kick starter for additional CPUs | |
757 | */ | |
84b36a8e HC |
758 | #ifdef CONFIG_SMP |
759 | #ifndef CONFIG_HOTPLUG_CPU | |
760 | .section .init.text,"ax" | |
761 | #endif | |
25d83cbf | 762 | .globl restart_int_handler |
1da177e4 | 763 | restart_int_handler: |
25d83cbf HC |
764 | lg %r15,__LC_SAVE_AREA+120 # load ksp |
765 | lghi %r10,__LC_CREGS_SAVE_AREA | |
766 | lctlg %c0,%c15,0(%r10) # get new ctl regs | |
767 | lghi %r10,__LC_AREGS_SAVE_AREA | |
768 | lam %a0,%a15,0(%r10) | |
769 | lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone | |
770 | stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on | |
771 | jg start_secondary | |
84b36a8e HC |
772 | #ifndef CONFIG_HOTPLUG_CPU |
773 | .previous | |
774 | #endif | |
1da177e4 LT |
775 | #else |
776 | /* | |
777 | * If we do not run with SMP enabled, let the new CPU crash ... | |
778 | */ | |
25d83cbf | 779 | .globl restart_int_handler |
1da177e4 | 780 | restart_int_handler: |
25d83cbf | 781 | basr %r1,0 |
1da177e4 | 782 | restart_base: |
25d83cbf HC |
783 | lpswe restart_crash-restart_base(%r1) |
784 | .align 8 | |
1da177e4 | 785 | restart_crash: |
25d83cbf | 786 | .long 0x000a0000,0x00000000,0x00000000,0x00000000 |
1da177e4 LT |
787 | restart_go: |
788 | #endif | |
789 | ||
790 | #ifdef CONFIG_CHECK_STACK | |
791 | /* | |
792 | * The synchronous or the asynchronous stack overflowed. We are dead. | |
793 | * No need to properly save the registers, we are going to panic anyway. | |
794 | * Setup a pt_regs so that show_trace can provide a good call trace. | |
795 | */ | |
796 | stack_overflow: | |
797 | lg %r15,__LC_PANIC_STACK # change to panic stack | |
9514e231 | 798 | aghi %r15,-SP_SIZE |
1da177e4 LT |
799 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack |
800 | stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack | |
801 | la %r1,__LC_SAVE_AREA | |
802 | chi %r12,__LC_SVC_OLD_PSW | |
803 | je 0f | |
804 | chi %r12,__LC_PGM_OLD_PSW | |
805 | je 0f | |
9514e231 | 806 | la %r1,__LC_SAVE_AREA+32 |
25d83cbf HC |
807 | 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack |
808 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain | |
809 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 LT |
810 | jg kernel_stack_overflow |
811 | #endif | |
812 | ||
813 | cleanup_table_system_call: | |
814 | .quad system_call, sysc_do_svc | |
815 | cleanup_table_sysc_return: | |
816 | .quad sysc_return, sysc_leave | |
817 | cleanup_table_sysc_leave: | |
818 | .quad sysc_leave, sysc_work_loop | |
819 | cleanup_table_sysc_work_loop: | |
820 | .quad sysc_work_loop, sysc_reschedule | |
63b12246 MS |
821 | cleanup_table_io_return: |
822 | .quad io_return, io_leave | |
ae6aa2ea MS |
823 | cleanup_table_io_leave: |
824 | .quad io_leave, io_done | |
825 | cleanup_table_io_work_loop: | |
826 | .quad io_work_loop, io_mcck_pending | |
1da177e4 LT |
827 | |
828 | cleanup_critical: | |
829 | clc 8(8,%r12),BASED(cleanup_table_system_call) | |
830 | jl 0f | |
831 | clc 8(8,%r12),BASED(cleanup_table_system_call+8) | |
832 | jl cleanup_system_call | |
833 | 0: | |
834 | clc 8(8,%r12),BASED(cleanup_table_sysc_return) | |
835 | jl 0f | |
836 | clc 8(8,%r12),BASED(cleanup_table_sysc_return+8) | |
837 | jl cleanup_sysc_return | |
838 | 0: | |
839 | clc 8(8,%r12),BASED(cleanup_table_sysc_leave) | |
840 | jl 0f | |
841 | clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8) | |
842 | jl cleanup_sysc_leave | |
843 | 0: | |
844 | clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop) | |
845 | jl 0f | |
846 | clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8) | |
77fa2245 | 847 | jl cleanup_sysc_return |
63b12246 MS |
848 | 0: |
849 | clc 8(8,%r12),BASED(cleanup_table_io_return) | |
850 | jl 0f | |
851 | clc 8(8,%r12),BASED(cleanup_table_io_return+8) | |
852 | jl cleanup_io_return | |
ae6aa2ea MS |
853 | 0: |
854 | clc 8(8,%r12),BASED(cleanup_table_io_leave) | |
855 | jl 0f | |
856 | clc 8(8,%r12),BASED(cleanup_table_io_leave+8) | |
857 | jl cleanup_io_leave | |
858 | 0: | |
859 | clc 8(8,%r12),BASED(cleanup_table_io_work_loop) | |
860 | jl 0f | |
861 | clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8) | |
862 | jl cleanup_io_return | |
1da177e4 LT |
863 | 0: |
864 | br %r14 | |
865 | ||
866 | cleanup_system_call: | |
867 | mvc __LC_RETURN_PSW(16),0(%r12) | |
ae6aa2ea MS |
868 | cghi %r12,__LC_MCK_OLD_PSW |
869 | je 0f | |
870 | la %r12,__LC_SAVE_AREA+32 | |
871 | j 1f | |
872 | 0: la %r12,__LC_SAVE_AREA+64 | |
873 | 1: | |
1da177e4 LT |
874 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
875 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8) | |
876 | jh 0f | |
877 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
878 | 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16) | |
879 | jhe cleanup_vtime | |
880 | #endif | |
881 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn) | |
882 | jh 0f | |
ae6aa2ea MS |
883 | mvc __LC_SAVE_AREA(32),0(%r12) |
884 | 0: stg %r13,8(%r12) | |
885 | stg %r12,__LC_SAVE_AREA+96 # argh | |
63b12246 | 886 | SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 887 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
ae6aa2ea MS |
888 | lg %r12,__LC_SAVE_AREA+96 # argh |
889 | stg %r15,24(%r12) | |
1da177e4 LT |
890 | llgh %r7,__LC_SVC_INT_CODE |
891 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
892 | cleanup_vtime: | |
893 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24) | |
894 | jhe cleanup_stime | |
895 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
896 | jz cleanup_novtime | |
897 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
898 | cleanup_stime: | |
899 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32) | |
900 | jh cleanup_update | |
901 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
902 | cleanup_update: | |
903 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
904 | cleanup_novtime: | |
905 | #endif | |
906 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8) | |
907 | la %r12,__LC_RETURN_PSW | |
908 | br %r14 | |
909 | cleanup_system_call_insn: | |
910 | .quad sysc_saveall | |
911 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
25d83cbf HC |
912 | .quad system_call |
913 | .quad sysc_vtime | |
914 | .quad sysc_stime | |
915 | .quad sysc_update | |
1da177e4 LT |
916 | #endif |
917 | ||
918 | cleanup_sysc_return: | |
919 | mvc __LC_RETURN_PSW(8),0(%r12) | |
920 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return) | |
921 | la %r12,__LC_RETURN_PSW | |
922 | br %r14 | |
923 | ||
924 | cleanup_sysc_leave: | |
925 | clc 8(8,%r12),BASED(cleanup_sysc_leave_insn) | |
ae6aa2ea | 926 | je 2f |
1da177e4 LT |
927 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
928 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
929 | clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8) | |
ae6aa2ea | 930 | je 2f |
1da177e4 LT |
931 | #endif |
932 | mvc __LC_RETURN_PSW(16),SP_PSW(%r15) | |
ae6aa2ea MS |
933 | cghi %r12,__LC_MCK_OLD_PSW |
934 | jne 0f | |
935 | mvc __LC_SAVE_AREA+64(32),SP_R12(%r15) | |
936 | j 1f | |
937 | 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15) | |
938 | 1: lmg %r0,%r11,SP_R0(%r15) | |
1da177e4 | 939 | lg %r15,SP_R15(%r15) |
ae6aa2ea | 940 | 2: la %r12,__LC_RETURN_PSW |
1da177e4 LT |
941 | br %r14 |
942 | cleanup_sysc_leave_insn: | |
943 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
944 | .quad sysc_leave + 16 | |
945 | #endif | |
946 | .quad sysc_leave + 12 | |
947 | ||
ae6aa2ea MS |
948 | cleanup_io_return: |
949 | mvc __LC_RETURN_PSW(8),0(%r12) | |
950 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop) | |
951 | la %r12,__LC_RETURN_PSW | |
952 | br %r14 | |
953 | ||
954 | cleanup_io_leave: | |
955 | clc 8(8,%r12),BASED(cleanup_io_leave_insn) | |
956 | je 2f | |
957 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
958 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
959 | clc 8(8,%r12),BASED(cleanup_io_leave_insn+8) | |
960 | je 2f | |
961 | #endif | |
962 | mvc __LC_RETURN_PSW(16),SP_PSW(%r15) | |
963 | cghi %r12,__LC_MCK_OLD_PSW | |
964 | jne 0f | |
965 | mvc __LC_SAVE_AREA+64(32),SP_R12(%r15) | |
966 | j 1f | |
967 | 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15) | |
968 | 1: lmg %r0,%r11,SP_R0(%r15) | |
969 | lg %r15,SP_R15(%r15) | |
970 | 2: la %r12,__LC_RETURN_PSW | |
971 | br %r14 | |
972 | cleanup_io_leave_insn: | |
973 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
974 | .quad io_leave + 20 | |
975 | #endif | |
976 | .quad io_leave + 16 | |
977 | ||
1da177e4 LT |
978 | /* |
979 | * Integer constants | |
980 | */ | |
25d83cbf | 981 | .align 4 |
1da177e4 | 982 | .Lconst: |
25d83cbf HC |
983 | .Lc_pactive: .long PREEMPT_ACTIVE |
984 | .Lnr_syscalls: .long NR_syscalls | |
985 | .L0x0130: .short 0x130 | |
986 | .L0x0140: .short 0x140 | |
987 | .L0x0150: .short 0x150 | |
988 | .L0x0160: .short 0x160 | |
989 | .L0x0170: .short 0x170 | |
1da177e4 | 990 | .Lcritical_start: |
25d83cbf | 991 | .quad __critical_start |
1da177e4 | 992 | .Lcritical_end: |
25d83cbf | 993 | .quad __critical_end |
1da177e4 | 994 | |
25d83cbf | 995 | .section .rodata, "a" |
1da177e4 | 996 | #define SYSCALL(esa,esame,emu) .long esame |
1da177e4 LT |
997 | sys_call_table: |
998 | #include "syscalls.S" | |
999 | #undef SYSCALL | |
1000 | ||
347a8dc3 | 1001 | #ifdef CONFIG_COMPAT |
1da177e4 LT |
1002 | |
1003 | #define SYSCALL(esa,esame,emu) .long emu | |
1da177e4 LT |
1004 | sys_call_table_emu: |
1005 | #include "syscalls.S" | |
1006 | #undef SYSCALL | |
1007 | #endif |